OV - exec - Function main

	Function: main	Module: exec	Source: main.c:50-194 [...]	Coverage (incl. loops): 0.03% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c: 50 - 194

--------------------------------------------------------------------------------

50: {

[...]

65:   rank = 0;

[...]

73:       printf( "count is set %d\n", count );

74:       printf( "Total MPI ranks %d\n", nprocs );

75:   }

76:

77:   if (argc == 2 && strncmp(argv[1], "-s", 2) == 0)

78:       NN = 15000;

79:

80:   if (argc == 2 && strncmp(argv[1], "-l", 2) == 0)

81:   	  count = 6000;

82:

83:   printf( "N is set %ld\n", NN );

84:

85: #pragma omp parallel

[...]

100:   for ( n = 400; n < NN; n = n + 20 )

101:   {

102:       /* Initial data preparation */

103:       fcoeff = 0.23f;

104:       fsrrmax2 = 0.5f;

105:       mp_rsm2 = 0.03f;

106:       dx1 = 1.0f/(float)n;

107:       dy1 = 2.0f/(float)n;

108:       dz1 = 3.0f/(float)n;

109:       xx[0] = 0.f;

110:       yy[0] = 0.f;

111:       zz[0] = 0.f;

112:       mass[0] = 2.f;

113:

114:       for ( i = 1; i < n; i++ )

115:       {

116:           xx[i] = xx[i-1] + dx1;

117:           yy[i] = yy[i-1] + dy1;

118:           zz[i] = zz[i-1] + dz1;

119:           mass[i] = (float)i * 0.01f + xx[i];

120:       }

121:

122:       for ( i = 0; i < n; i++ )

123:       {

124:           vx1[i] = 0.f;

125:           vy1[i] = 0.f;

126:           vz1[i] = 0.f;

[...]

139:       t1 = mysecond();

140: #endif

141:

142:     #pragma omp parallel for private( dx1, dy1, dz1 )

[...]

155:       t2 = mysecond();

[...]

169:       t3 = (t2 - t1) * 1e6;

170: #endif

171:

172:       elapsed = elapsed + t3;

[...]

186:   if ( rank == 0 )

187:   {

188:       printf( "\nKernel elapsed time, s: %18.8lf\n", elapsed*1e-6 );

[...]

194:   return 0;

0x410260 STR	D14, [SP, #352]!

0x410264 STP	D13, D12, [SP, #16]

0x410268 STP	D11, D10, [SP, #32]

0x41026c STP	D9, D8, [SP, #48]

0x410270 STP	X29, X30, [SP, #64]

0x410274 STP	X28, X27, [SP, #80]

0x410278 STP	X26, X25, [SP, #96]

0x41027c STP	X24, X23, [SP, #112]

0x410280 STP	X22, X21, [SP, #128]

0x410284 STP	X20, X19, [SP, #144]

0x410288 ADD	X29, SP, #64

0x41028c SUB	SP, SP, #32

0x410290 ADDVL	SP, SP, #61

0x410294 ORR	X20, XZR, X1

0x410298 ORR	W21, WZR, W0

0x41029c MOVZ	W19, #34464

0x4102a0 MOVZ	W8, #3000

0x4102a4 ADRP	X0,

0x4102a8 ADD	X0, X0, #24

0x4102ac STP	WZR, W8, [SP, #16]

0x4102b0 MOVZ	W1, #3000

0x4102b4 MOVK	W19, #1

0x4102b8 BL	410080

0x4102bc ADRP	X0,

0x4102c0 ADD	X0, X0, #41

0x4102c4 MOVZ	W1, #1

0x4102c8 BL	410080

0x4102cc CMP	W21, #2

0x4102d0 B.NE	410304

0x4102d4 LDR	X8, [X20, #8]

0x4102d8 LDRB	W9, [X8]

0x4102dc CMP	W9, #45

0x4102e0 B.NE	410304

0x4102e4 LDRB	W8, [X8, #1]

0x4102e8 MOVZ	W9, #15000

0x4102ec CMP	W8, #115

0x4102f0 CSEL	X19, X9, X19, #0

0x4102f4 CMP	W8, #108

0x4102f8 B.NE	410304

0x4102fc MOVZ	W8, #6000

0x410300 STR	W8, [SP, #20]

0x410304 ADRP	X0,

0x410308 ADD	X0, X0, #61

0x41030c ORR	X1, XZR, X19

0x410310 BL	410080

0x410314 ADRP	X0,

0x410318 ADD	X0, X0, #3384

0x41031c ADRP	X2, 41031c

0x410320 ADD	X2, X2, #1520

0x410324 ADD	X3, SP, #16

0x410328 MOVZ	W1, #1

0x41032c BL	410070

0x410330 INDEX	Z0.S, #0, #1

0x410334 PTRUE	P1.S, ALL

0x410338 SUB	X9, X29, #64

0x41033c MOVI	D9, #0

0x410340 FMOV	S10, #1.0000000

0x410344 FMOV	S11, #3.0000000

0x410348 FMOV	S12, #24.0000000

0x41034c MOVZ	W8, #400

0x410350 FMOV	S13, #8.0000000

0x410354 MOVZ	W27, #16384

0x410358 ADRP	X28,

0x41035c ADD	X28, X28, #96

0x410360 MOVZ	X20, #1

0x410364 ADRP	X21,

0x410368 ADD	X21, X21, #2784

0x41036c MOVPRFX	Z1, Z0

0x410370 UCVTF	Z1.S, P1/M, Z0.S

0x410374 ADD	Z0.S, Z0.S, #1

0x410378 ADRP	X22,

0x41037c ADD	X22, X22, #1376

0x410380 ADRP	X26,

0x410384 ADD	X26, X26, #4064

0x410388 ADRP	X23,

0x41038c ADD	X23, X23, #3456

0x410390 ADRP	X24, 410390

0x410394 ADD	X24, X24, #1584

0x410398 STR	W8, [SP, #24]

0x41039c STR	Z0, [X9, #510, MUL VL]

0x4103a0 STR	Z1, [X9, #509, MUL VL]

0x4103a4 MOVZ	W9, #55050

0x4103a8 MOVK	W9, #15395

0x4103ac DUP	Z20.S, W9

0x4103b0 MOVZ	X9, #33920

0x4103b4 MOVK	X9, #16686

0x4103b8 FMOV	D14, X9

0x4103bc SUB	X9, X29, #64

0x4103c0 STR	Z20, [X9, #511, MUL VL]

0x4103c4 B	410468

  (2) 0x4103c8 UBFM	X25, X8, #62, #31

  (2) 0x4103cc ADRP	X0,

  (2) 0x4103d0 ADD	X0, X0, #2656

  (2) 0x4103d4 ORR	W1, WZR, WZR

  (2) 0x4103d8 ORR	X2, XZR, X25

  (2) 0x4103dc BL	4100a0

  (2) 0x4103e0 ADRP	X0,

  (2) 0x4103e4 ADD	X0, X0, #1248

  (2) 0x4103e8 ORR	W1, WZR, WZR

  (2) 0x4103ec ORR	X2, XZR, X25

  (2) 0x4103f0 BL	4100a0

  (2) 0x4103f4 ADRP	X0,

  (2) 0x4103f8 ADD	X0, X0, #3936

  (2) 0x4103fc ORR	W1, WZR, WZR

  (2) 0x410400 ORR	X2, XZR, X25

  (2) 0x410404 BL	4100a0

  (2) 0x410408 BL	4107c0

  (2) 0x41040c ADD	X5, SP, #44

  (2) 0x410410 ADD	X6, SP, #40

  (2) 0x410414 ADD	X3, SP, #20

  (2) 0x410418 ADD	X4, SP, #24

  (2) 0x41041c FMOV	D8, D0

  (2) 0x410420 ORR	X0, XZR, X23

  (2) 0x410424 ORR	X2, XZR, X24

  (2) 0x410428 ADD	X7, SP, #28

  (2) 0x41042c ADDVL	X5, X5, #3

  (2) 0x410430 ADDVL	X6, X6, #3

  (2) 0x410434 MOVZ	W1, #5

  (2) 0x410438 BL	410070

  (2) 0x41043c BL	4107c0

  (2) 0x410440 SUB	X8, X29, #64

  (2) 0x410444 FSUB	D0, D0, S8

  (2) 0x410448 PTRUE	P1.S, ALL

  (2) 0x41044c LDR	Z20, [X8, #511, MUL VL]

  (2) 0x410450 LDRSW	X8, [SP, #24]

  (2) 0x410454 FMADD	D9, D0, D14, D9

  (2) 0x410458 ADD	X8, X8, #20

  (2) 0x41045c CMP	X19, X8

  (2) 0x410460 STR	W8, [SP, #24]

  (2) 0x410464 B.LE	41058c

  (2) 0x410468 MOVZ	W9, #34079

  (2) 0x41046c ADDVL	X10, SP, #3

  (2) 0x410470 CMP	W8, #2

  (2) 0x410474 MOVK	W9, #15979

  (2) 0x410478 STR	W9, [SP, #28]

  (2) 0x41047c MOVZ	W9, #16128

  (2) 0x410480 STR	W9, [X10, #44]

  (2) 0x410484 MOVZ	W9, #49807

  (2) 0x410488 ADDVL	X10, SP, #3

  (2) 0x41048c MOVK	W9, #15605

  (2) 0x410490 STR	W9, [X10, #40]

  (2) 0x410494 ADRP	X9,

  (2) 0x410498 STR	WZR, [X9, #96]

  (2) 0x41049c ADRP	X9,

  (2) 0x4104a0 STR	WZR, [X9, #2784]

  (2) 0x4104a4 ADRP	X9,

  (2) 0x4104a8 STR	WZR, [X9, #1376]

  (2) 0x4104ac ADRP	X9,

  (2) 0x4104b0 STR	W27, [X9, #4064]

  (2) 0x4104b4 B.LT	410580

  (2) 0x4104b8 SCVTF	S0, W8

  (2) 0x4104bc SUB	X11, X29, #64

  (2) 0x4104c0 ORR	W10, WZR, W8

  (2) 0x4104c4 SUB	X10, X10, #1

  (2) 0x4104c8 ORR	X9, XZR, XZR

  (2) 0x4104cc LDR	Z7, [X11, #509, MUL VL]

  (2) 0x4104d0 LDR	Z17, [X11, #510, MUL VL]

  (2) 0x4104d4 FDIV	S16, S10, S0

  (2) 0x4104d8 WHILELO	P0.S, XZR, X10

  (2) 0x4104dc FMUL	S2, S16, S11

  (2) 0x4104e0 FADD	S6, S16, S16

  (2) 0x4104e4 DUP	Z0.S, Z16.S[0]

  (2) 0x4104e8 FMUL	S4, S16, S12

  (2) 0x4104ec FMUL	S16, S16, S13

  (2) 0x4104f0 DUP	Z1.S, Z6.S[0]

  (2) 0x4104f4 FMUL	S6, S6, S13

  (2) 0x4104f8 DUP	Z2.S, Z2.S[0]

  (2) 0x4104fc DUP	Z4.S, Z4.S[0]

  (2) 0x410500 DUP	Z16.S, Z16.S[0]

  (2) 0x410504 FMUL	Z5.S, Z1.S, Z7.S

  (2) 0x410508 FMUL	Z3.S, Z2.S, Z7.S

  (2) 0x41050c FMUL	Z7.S, Z0.S, Z7.S

  (2) 0x410510 DUP	Z6.S, Z6.S[0]

  (2) 0x410514 HINT	#0

  (2) 0x410518 HINT	#0

  (2) 0x41051c HINT	#0

    (1) 0x410520 FADD	Z18.S, Z7.S, Z0.S

    (1) 0x410524 ADD	X11, X28, X9,LSL #2

    (1) 0x410528 FADD	Z19.S, Z5.S, Z1.S

    (1) 0x41052c ST1W	{Z18.S}, P0, [X11, X20,LSL #2]

    (1) 0x410530 ADD	X11, X21, X9,LSL #2

    (1) 0x410534 FADD	Z5.S, Z5.S, Z6.S

    (1) 0x410538 FADD	Z7.S, Z7.S, Z16.S

    (1) 0x41053c ST1W	{Z19.S}, P0, [X11, X20,LSL #2]

    (1) 0x410540 FADD	Z19.S, Z3.S, Z2.S

    (1) 0x410544 ADD	X11, X22, X9,LSL #2

    (1) 0x410548 FADD	Z3.S, Z3.S, Z4.S

    (1) 0x41054c ST1W	{Z19.S}, P0, [X11, X20,LSL #2]

    (1) 0x410550 MOVPRFX	Z19, Z17

    (1) 0x410554 UCVTF	Z19.S, P1/M, Z17.S

    (1) 0x410558 ADD	X11, X26, X9,LSL #2

    (1) 0x41055c ADD	X9, X9, #8

    (1) 0x410560 ADD	Z17.S, Z17.S, #8

    (1) 0x410564 FMLA	Z18.S, P1/M, Z19.S, Z20.S

    (1) 0x410568 ST1W	{Z18.S}, P0, [X11, X20,LSL #2]

    (1) 0x41056c WHILELO	P0.S, X9, X10

    (1) 0x410570 B.MI	410520

  (2) 0x410574 B	4103c8

0x410578 HINT	#0

0x41057c HINT	#0

(0) 0x410580 CMP	W8, #1

(0) 0x410584 B.EQ	4103c8

(0) 0x410588 B	410408

0x41058c LDR	W8, [SP, #16]

0x410590 CBNZ	W8, 4105ac

0x410594 ADRP	X8,

0x410598 ADRP	X0,

0x41059c ADD	X0, X0, #102

0x4105a0 LDR	D0, [X8, #16]

0x4105a4 FMUL	D0, D9, D0

0x4105a8 BL	410080

0x4105ac ORR	W0, WZR, WZR

0x4105b0 ADDVL	SP, SP, #3

0x4105b4 ADD	SP, SP, #32

0x4105b8 LDP	D9, D8, [SP, #48]

0x4105bc LDP	D11, D10, [SP, #32]

0x4105c0 LDP	D13, D12, [SP, #16]

0x4105c4 LDP	X20, X19, [SP, #144]

0x4105c8 LDP	X22, X21, [SP, #128]

0x4105cc LDP	X24, X23, [SP, #112]

0x4105d0 LDP	X26, X25, [SP, #96]

0x4105d4 LDP	X28, X27, [SP, #80]

0x4105d8 LDP	X29, X30, [SP, #64]

0x4105dc LDR	D14, [SP], #160

0x4105e0 RET

0x4105e4 HINT	#0

0x4105e8 HINT	#0

0x4105ec HINT	#0

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_7

Source file and lines	main.c:50-194
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:50,65,73-85,100-126,139-142,155,169-172,186-188,194.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.25 to 4.17 cycles (3.90x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 34% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 16.25 to 9.28 cycles (1.75x speedup).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

30% of VPU loads are used in vector version.
37% of VPU stores are used in vector version.
3% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
4% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 5 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:73
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:74
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:83
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:85
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:188

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:85

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 5 bytes. The binary function is storing 102 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	117
nb uops	112
loop length	468
used w registers	8
used x registers	19
used b registers	0
used h registers	0
used s registers	5
used d registers	8
used q registers	0
used v registers	0
used z registers	3
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	16.25	16.25	16.25	16.25	4.50	4.50	4.50	4.50	10.33	10.33	10.33	4.50	4.50
cycles	5.50	5.50	16.25	16.25	16.25	16.25	4.50	4.50	4.50	4.50	10.33	10.33	10.33	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.00
Dispatch	16.25
Overall L1	16.25

Vectorization ratios

INT

all	15%
load	30%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	3%
fma	NA (no fma vectorizable/vectorized instructions)
other	5%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	14%
load	30%
store	37%
mul	0%
add-sub	3%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

INT

all	35%
load	45%
store	51%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	27%
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	16%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	34%
load	45%
store	51%
mul	25%
add-sub	27%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.25 cycles. At this rate:

0% of peak load performance is reached (0.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.28 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 410260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STR D14, [SP, #352]!	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB SP, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #61	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W19, #34464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W8, #3000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4202a4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP WZR, W8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W1, #3000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410080 <@plt_start@+0x60>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4202bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #41	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410080 <@plt_start@+0x60>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W21, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 410304 <main+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDRB W9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W9, #45	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 410304 <main+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRB W8, [X8, #1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W9, #15000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W8, #115	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL X19, X9, X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W8, #108	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 410304 <main+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W8, #6000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W8, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADRP X0, <420304>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 410080 <@plt_start@+0x60>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <43f314>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X2, 41031c <main+0xbc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X2, #1520	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410070 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INDEX Z0.S, #0, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	1	N/A
PTRUE P1.S, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUB X9, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D9, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV S10, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
FMOV S11, #3.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
FMOV S12, #24.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W8, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S13, #8.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W27, #16384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X28, <440358>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X28, X28, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X21, <4a1364>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X21, X21, #2784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVPRFX Z1, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
UCVTF Z1.S, P1/M, Z0.S	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	2	vect (100.0%)
ADD Z0.S, Z0.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADRP X22, <503378>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X22, X22, #1376	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X26, <564380>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X26, X26, #4064	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X23, <43f388>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X23, X23, #3456	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X24, 410390 <main+0x130>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X24, X24, #1584	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR Z0, [X9, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z1, [X9, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVZ W9, #55050	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W9, #15395	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z20.S, W9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ X9, #33920	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X9, #16686	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D14, X9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB X9, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z20, [X9, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 410468 <main+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ W8, 4105ac <main+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X8, <420594>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <420598>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #102	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D0, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D0, D9, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
BL 410080 <@plt_start@+0x60>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W0, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADDVL SP, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_7

Source file and lines	main.c:50-194
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:50,65,73-85,100-126,139-142,155,169-172,186-188,194.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.25 to 4.17 cycles (3.90x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

30% of VPU loads are used in vector version.
37% of VPU stores are used in vector version.
3% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
4% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 5 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:73
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:74
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:83
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:85
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:188

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:85

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 5 bytes. The binary function is storing 102 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	117
nb uops	112
loop length	468
used w registers	8
used x registers	19
used b registers	0
used h registers	0
used s registers	5
used d registers	8
used q registers	0
used v registers	0
used z registers	3
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	16.25	16.25	16.25	16.25	4.50	4.50	4.50	4.50	10.33	10.33	10.33	4.50	4.50
cycles	5.50	5.50	16.25	16.25	16.25	16.25	4.50	4.50	4.50	4.50	10.33	10.33	10.33	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.00
Dispatch	16.25
Overall L1	16.25

Vectorization ratios

INT

all	15%
load	30%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	3%
fma	NA (no fma vectorizable/vectorized instructions)
other	5%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	14%
load	30%
store	37%
mul	0%
add-sub	3%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

INT

all	35%
load	45%
store	51%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	27%
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	16%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	34%
load	45%
store	51%
mul	25%
add-sub	27%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.25 cycles. At this rate:

0% of peak load performance is reached (0.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.28 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 410260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STR D14, [SP, #352]!	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB SP, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #61	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W19, #34464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W8, #3000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4202a4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP WZR, W8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W1, #3000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410080 <@plt_start@+0x60>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4202bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #41	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410080 <@plt_start@+0x60>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W21, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 410304 <main+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDRB W9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W9, #45	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 410304 <main+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRB W8, [X8, #1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W9, #15000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W8, #115	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL X19, X9, X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W8, #108	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 410304 <main+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W8, #6000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W8, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADRP X0, <420304>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 410080 <@plt_start@+0x60>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <43f314>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X2, 41031c <main+0xbc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X2, #1520	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410070 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INDEX Z0.S, #0, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	1	N/A
PTRUE P1.S, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUB X9, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D9, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV S10, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
FMOV S11, #3.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
FMOV S12, #24.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W8, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S13, #8.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W27, #16384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X28, <440358>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X28, X28, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X21, <4a1364>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X21, X21, #2784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVPRFX Z1, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
UCVTF Z1.S, P1/M, Z0.S	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	2	vect (100.0%)
ADD Z0.S, Z0.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADRP X22, <503378>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X22, X22, #1376	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X26, <564380>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X26, X26, #4064	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X23, <43f388>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X23, X23, #3456	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X24, 410390 <main+0x130>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X24, X24, #1584	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR Z0, [X9, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z1, [X9, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVZ W9, #55050	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W9, #15395	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z20.S, W9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ X9, #33920	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X9, #16686	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D14, X9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB X9, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z20, [X9, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 410468 <main+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ W8, 4105ac <main+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X8, <420594>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <420598>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #102	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D0, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D0, D9, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
BL 410080 <@plt_start@+0x60>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W0, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADDVL SP, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼main–	0.03	0.01
▼Loop 0 - main.c:100-172 - exec–	0.00	0.00
▼Loop 2 - main.c:100-172 - exec–	0.00	0.00
○Loop 1 - main.c:116-119 - exec	0.03	0.51

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Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Conversion instructions

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code