OV - exec - Loop 5

	Loop Id: 5	Module: exec	Source: Step10_orig.c:19-35	Coverage: 97.62%

0x41096c LDR	Z8, [X11, #511, MUL VL]    [2]

0x410970 LDR	Z0, [SP, #5, MUL VL]    [1]

0x410974 SUBS	X15, X15, #16

0x410978 FSUB	Z8.S, Z8.S, Z0.S

0x41097c LDR	Z9, [X13, #511, MUL VL]    [4]

0x410980 LDR	Z10, [X14, #511, MUL VL]    [5]

0x410984 FSUB	Z9.S, Z9.S, Z7.S

0x410988 FSUB	Z10.S, Z10.S, Z16.S

0x41098c LDR	Z6, [X11, MUL VL]    [2]

0x410990 LDR	Z13, [X14, MUL VL]    [5]

0x410994 FSUB	Z13.S, Z13.S, Z16.S

0x410998 ADD	X11, X11, #64

0x41099c ADD	X14, X14, #64

0x4109a0 FMUL	Z11.S, Z8.S, Z8.S

0x4109a4 FMLA	Z11.S, P0/M, Z9.S, Z9.S

0x4109a8 MOVPRFX	Z14, Z11

0x4109ac FMLA	Z14.S, P0/M, Z10.S, Z10.S

0x4109b0 FADD	Z11.S, Z14.S, Z20.S

0x4109b4 MOVPRFX	Z18, Z22

0x4109b8 FMLS	Z18.S, P0/M, Z14.S, Z1.S

0x4109bc FCMGT	P3.S, P0/Z, Z17.S, Z14.S

0x4109c0 FCMGT	P4.S, P0/Z, Z14.S, #0.0000000

0x4109c4 MOVPRFX	Z12, Z11

0x4109c8 EXT	Z12.B, Z12.B, Z11.B, #16

0x4109cc FMAD	Z18.S, P0/M, Z14.S, Z23.S

0x4109d0 UUNPKLO	Z5.D, Z11.S

0x4109d4 FSUB	Z11.S, Z6.S, Z0.S

0x4109d8 LDR	Z6, [X13, MUL VL]    [4]

0x4109dc ADD	X13, X13, #64

0x4109e0 UUNPKLO	Z12.D, Z12.S

0x4109e4 FMAD	Z18.S, P0/M, Z14.S, Z24.S

0x4109e8 FCVT	Z5.D, P1/M, Z5.S

0x4109ec FMUL	Z15.S, Z11.S, Z11.S

0x4109f0 FCVT	Z12.D, P1/M, Z12.S

0x4109f4 FMAD	Z18.S, P0/M, Z14.S, Z25.S

0x4109f8 FMAD	Z18.S, P0/M, Z14.S, Z26.S

0x4109fc FSUB	Z6.S, Z6.S, Z7.S

0x410a00 MOVPRFX	Z4, Z12

0x410a04 FSQRT	Z4.D, P1/M, Z12.D

0x410a08 FMUL	Z12.D, Z12.D, Z12.D

0x410a0c FMLA	Z15.S, P0/M, Z6.S, Z6.S

0x410a10 FDIVR	Z12.D, P1/M, Z12.D, Z21.D

0x410a14 MOVPRFX	Z0, Z18

0x410a18 EXT	Z0.B, Z0.B, Z18.B, #16

0x410a1c FMLA	Z15.S, P0/M, Z13.S, Z13.S

0x410a20 UUNPKLO	Z18.D, Z18.S

0x410a24 UUNPKLO	Z0.D, Z0.S

0x410a28 FCVT	Z18.D, P1/M, Z18.S

0x410a2c FCVT	Z0.D, P1/M, Z0.S

0x410a30 FADD	Z3.S, Z15.S, Z20.S

0x410a34 MOVPRFX	Z2, Z3

0x410a38 EXT	Z2.B, Z2.B, Z3.B, #16

0x410a3c UUNPKLO	Z3.D, Z3.S

0x410a40 UUNPKLO	Z2.D, Z2.S

0x410a44 FCVT	Z3.D, P1/M, Z3.S

0x410a48 FCVT	Z2.D, P1/M, Z2.S

0x410a4c FNMLS	Z0.D, P1/M, Z12.D, Z4.D

0x410a50 MOVPRFX	Z4, Z5

0x410a54 FSQRT	Z4.D, P1/M, Z5.D

0x410a58 FMUL	Z5.D, Z5.D, Z5.D

0x410a5c MOVPRFX	Z12, Z2

0x410a60 FSQRT	Z12.D, P1/M, Z2.D

0x410a64 FMUL	Z2.D, Z2.D, Z2.D

0x410a68 FDIVR	Z5.D, P1/M, Z5.D, Z21.D

0x410a6c FDIVR	Z2.D, P1/M, Z2.D, Z21.D

0x410a70 FCVT	Z0.S, P1/M, Z0.D

0x410a74 UZP1	Z0.S, Z0.S, Z0.S

0x410a78 FNMSB	Z4.D, P1/M, Z5.D, Z18.D

0x410a7c MOVPRFX	Z5, Z22

0x410a80 FMLS	Z5.S, P0/M, Z15.S, Z1.S

0x410a84 FMAD	Z5.S, P0/M, Z15.S, Z23.S

0x410a88 FMAD	Z5.S, P0/M, Z15.S, Z24.S

0x410a8c FCVT	Z4.S, P1/M, Z4.D

0x410a90 FMAD	Z5.S, P0/M, Z15.S, Z25.S

0x410a94 UZP1	Z4.S, Z4.S, Z4.S

0x410a98 FMAD	Z5.S, P0/M, Z15.S, Z26.S

0x410a9c SPLICE	Z4.S, P2, Z4.S, Z0.S

0x410aa0 LD1W	{Z0.S}, P3/Z, [X12, #15, MUL VL]    [3]

0x410aa4 FCMGT	P3.S, P0/Z, Z17.S, Z15.S

0x410aa8 MOVPRFX	Z18, Z5

0x410aac EXT	Z18.B, Z18.B, Z5.B, #16

0x410ab0 UUNPKLO	Z5.D, Z5.S

0x410ab4 UUNPKLO	Z18.D, Z18.S

0x410ab8 FCVT	Z5.D, P1/M, Z5.S

0x410abc FMUL	Z0.S, Z0.S, Z4.S

0x410ac0 CPY	Z4.S, P4/Z, #255

0x410ac4 FCVT	Z18.D, P1/M, Z18.S

0x410ac8 AND	Z0.D, Z4.D, Z0.D

0x410acc FNMSB	Z2.D, P1/M, Z12.D, Z18.D

0x410ad0 MOVPRFX	Z18, Z3

0x410ad4 FSQRT	Z18.D, P1/M, Z3.D

0x410ad8 FMUL	Z3.D, Z3.D, Z3.D

0x410adc FMLA	Z27.S, P0/M, Z0.S, Z8.S

0x410ae0 FMLA	Z28.S, P0/M, Z0.S, Z9.S

0x410ae4 FMLA	Z19.S, P0/M, Z0.S, Z10.S

0x410ae8 FDIVR	Z3.D, P1/M, Z3.D, Z21.D

0x410aec FCVT	Z2.S, P1/M, Z2.D

0x410af0 UZP1	Z2.S, Z2.S, Z2.S

0x410af4 FNMSB	Z3.D, P1/M, Z18.D, Z5.D

0x410af8 FCVT	Z3.S, P1/M, Z3.D

0x410afc UZP1	Z0.S, Z3.S, Z3.S

0x410b00 SPLICE	Z0.S, P2, Z0.S, Z2.S

0x410b04 LD1W	{Z2.S}, P3/Z, [X12, MUL VL]    [3]

0x410b08 FCMGT	P3.S, P0/Z, Z15.S, #0.0000000

0x410b0c ADD	X12, X12, #64

0x410b10 FMUL	Z0.S, Z2.S, Z0.S

0x410b14 CPY	Z2.S, P3/Z, #255

0x410b18 AND	Z0.D, Z2.D, Z0.D

0x410b1c FMLA	Z29.S, P0/M, Z0.S, Z11.S

0x410b20 FMLA	Z30.S, P0/M, Z0.S, Z6.S

0x410b24 FMLA	Z31.S, P0/M, Z0.S, Z13.S

0x410b28 B.NE	41096c

/home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 35

--------------------------------------------------------------------------------

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

32:

33:         xi = xi + f * dxc;

34:         yi = yi + f * dyc;

35:         zi = zi + f * dzc;

Coverage (%)	Name	Source Location	Module
►98.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	main.c:155	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15 - 2.32
Bottlenecks	P6, P8,
Function	Step10_orig
Source	Step10_orig.c:19-35
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	16
CQA cycles	55.94 - 112.68
CQA cycles if no scalar integer	55.94 - 112.68
CQA cycles if FP arith vectorized	55.94 - 112.68
CQA cycles if fully vectorized	55.94 - 112.68
Front-end cycles	14.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	1.25
P6 cycles	48.50
P7 cycles	48.50
P8 cycles	20.00
P9 cycles	20.00
P10 cycles	4.50
P11 cycles	4.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	55.94 - 112.68
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	112.00
Nb uops	112.00
Nb loads	NA
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	8.87 - 4.40
Nb FLOP add-sub	64.00
Nb FLOP mul	48.00
Nb FLOP fma	176.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.56 - 5.15
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	86.92
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	88.89
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	73.47
Vector-efficiency ratio all	97.49
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	91.67
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	96.05

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15 - 2.32
Bottlenecks	P6, P8,
Function	Step10_orig
Source	Step10_orig.c:19-35
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	16
CQA cycles	55.94 - 112.68
CQA cycles if no scalar integer	55.94 - 112.68
CQA cycles if FP arith vectorized	55.94 - 112.68
CQA cycles if fully vectorized	55.94 - 112.68
Front-end cycles	14.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	1.25
P6 cycles	48.50
P7 cycles	48.50
P8 cycles	20.00
P9 cycles	20.00
P10 cycles	4.50
P11 cycles	4.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	55.94 - 112.68
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	112.00
Nb uops	112.00
Nb loads	NA
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	8.87 - 4.40
Nb FLOP add-sub	64.00
Nb FLOP mul	48.00
Nb FLOP fma	176.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.56 - 5.15
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	86.92
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	88.89
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	73.47
Vector-efficiency ratio all	97.49
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	91.67
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	96.05

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	Step10_orig
Source file and lines	Step10_orig.c:19-35
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

86% of VPU instructions are used in vector version (process two or more data elements in vector registers):

88% of VPU addition or subtraction instructions are used in vector version.
73% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 112.68 to 44.50 cycles (2.53x speedup).

FMA

Detected 176 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 12 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 496 FP arithmetical operations:

240: addition or subtraction (176 inside FMA instructions)
224: multiply (176 inside FMA instructions)
16: divide
16: square root

The binary loop is loading 288 bytes.

Arithmetic intensity

Arithmetic intensity is 1.72 FP operations per loaded or stored byte.

General properties

nb instructions	112
nb uops	112
loop length	448
used w registers	0
used x registers	5
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	32
nb stack references	1
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	48.50	48.50	0.00	0.00	4.50	4.50	0.00	0.00	0.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	48.50	48.50	20.00	20.00	4.50	4.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	55.94-112.68
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	14.00
Dispatch	48.50
DIV/SQRT	55.94-112.68
Data deps.	2.00
Overall L1	55.94-112.68

Vectorization ratios

INT

all	67%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	60%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	86%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	88%
fma	100%
div/sqrt	100%
other	73%

Vector efficiency ratios

INT

all	93%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	94%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	97%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	91%
fma	100%
div/sqrt	100%
other	96%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 112.68 cycles. At this rate:

2% of peak load performance is reached (2.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41096c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
LDR Z8, [X11, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z0, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUBS X15, X15, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (25.0%)
FSUB Z8.S, Z8.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LDR Z9, [X13, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z10, [X14, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z9.S, Z9.S, Z7.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FSUB Z10.S, Z10.S, Z16.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LDR Z6, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z13, [X14, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z13.S, Z13.S, Z16.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
ADD X11, X11, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X14, X14, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z11.S, Z8.S, Z8.S	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z11.S, P0/M, Z9.S, Z9.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z14, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z14.S, P0/M, Z10.S, Z10.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z11.S, Z14.S, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOVPRFX Z18, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLS Z18.S, P0/M, Z14.S, Z1.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCMGT P3.S, P0/Z, Z17.S, Z14.S	1	0	0	0	0	0	0	1	0	0	0	2	1	vect (100.0%)
FCMGT P4.S, P0/Z, Z14.S, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	2	1	vect (100.0%)
MOVPRFX Z12, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
EXT Z12.B, Z12.B, Z11.B, #16	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMAD Z18.S, P0/M, Z14.S, Z23.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
UUNPKLO Z5.D, Z11.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FSUB Z11.S, Z6.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LDR Z6, [X13, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X13, X13, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
UUNPKLO Z12.D, Z12.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMAD Z18.S, P0/M, Z14.S, Z24.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCVT Z5.D, P1/M, Z5.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FMUL Z15.S, Z11.S, Z11.S	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FCVT Z12.D, P1/M, Z12.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FMAD Z18.S, P0/M, Z14.S, Z25.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMAD Z18.S, P0/M, Z14.S, Z26.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FSUB Z6.S, Z6.S, Z7.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOVPRFX Z4, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FSQRT Z4.D, P1/M, Z12.D	1	0	0	0	0	0	0	1	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z12.D, Z12.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z15.S, P0/M, Z6.S, Z6.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FDIVR Z12.D, P1/M, Z12.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z0, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
EXT Z0.B, Z0.B, Z18.B, #16	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z15.S, P0/M, Z13.S, Z13.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
UUNPKLO Z18.D, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
UUNPKLO Z0.D, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FCVT Z18.D, P1/M, Z18.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FCVT Z0.D, P1/M, Z0.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FADD Z3.S, Z15.S, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOVPRFX Z2, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
EXT Z2.B, Z2.B, Z3.B, #16	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
UUNPKLO Z3.D, Z3.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
UUNPKLO Z2.D, Z2.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FCVT Z3.D, P1/M, Z3.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FCVT Z2.D, P1/M, Z2.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FNMLS Z0.D, P1/M, Z12.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z4, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FSQRT Z4.D, P1/M, Z5.D	1	0	0	0	0	0	0	1	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z5.D, Z5.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
MOVPRFX Z12, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FSQRT Z12.D, P1/M, Z2.D	1	0	0	0	0	0	0	1	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z2.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FDIVR Z5.D, P1/M, Z5.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIVR Z2.D, P1/M, Z2.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCVT Z0.S, P1/M, Z0.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
UZP1 Z0.S, Z0.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FNMSB Z4.D, P1/M, Z5.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z5, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLS Z5.S, P0/M, Z15.S, Z1.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMAD Z5.S, P0/M, Z15.S, Z23.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMAD Z5.S, P0/M, Z15.S, Z24.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCVT Z4.S, P1/M, Z4.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FMAD Z5.S, P0/M, Z15.S, Z25.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
UZP1 Z4.S, Z4.S, Z4.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMAD Z5.S, P0/M, Z15.S, Z26.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
SPLICE Z4.S, P2, Z4.S, Z0.S	1	0	0	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
LD1W {Z0.S}, P3/Z, [X12, #15, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGT P3.S, P0/Z, Z17.S, Z15.S	1	0	0	0	0	0	0	1	0	0	0	2	1	vect (100.0%)
MOVPRFX Z18, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
EXT Z18.B, Z18.B, Z5.B, #16	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
UUNPKLO Z5.D, Z5.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
UUNPKLO Z18.D, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FCVT Z5.D, P1/M, Z5.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FMUL Z0.S, Z0.S, Z4.S	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
CPY Z4.S, P4/Z, #255	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (3.1%)
FCVT Z18.D, P1/M, Z18.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
AND Z0.D, Z4.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FNMSB Z2.D, P1/M, Z12.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z18, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FSQRT Z18.D, P1/M, Z3.D	1	0	0	0	0	0	0	1	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z3.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z27.S, P0/M, Z0.S, Z8.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z28.S, P0/M, Z0.S, Z9.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z19.S, P0/M, Z0.S, Z10.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FDIVR Z3.D, P1/M, Z3.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCVT Z2.S, P1/M, Z2.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
UZP1 Z2.S, Z2.S, Z2.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FNMSB Z3.D, P1/M, Z18.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCVT Z3.S, P1/M, Z3.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
UZP1 Z0.S, Z3.S, Z3.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
SPLICE Z0.S, P2, Z0.S, Z2.S	1	0	0	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
LD1W {Z2.S}, P3/Z, [X12, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGT P3.S, P0/Z, Z15.S, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	2	1	vect (100.0%)
ADD X12, X12, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z0.S, Z2.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
CPY Z2.S, P3/Z, #255	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (3.1%)
AND Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z29.S, P0/M, Z0.S, Z11.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z30.S, P0/M, Z0.S, Z6.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z31.S, P0/M, Z0.S, Z13.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
B.NE 41096c <Step10_orig+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	Step10_orig
Source file and lines	Step10_orig.c:19-35
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

86% of VPU instructions are used in vector version (process two or more data elements in vector registers):

88% of VPU addition or subtraction instructions are used in vector version.
73% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 112.68 to 44.50 cycles (2.53x speedup).

FMA

Detected 176 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 12 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 496 FP arithmetical operations:

240: addition or subtraction (176 inside FMA instructions)
224: multiply (176 inside FMA instructions)
16: divide
16: square root

The binary loop is loading 288 bytes.

Arithmetic intensity

Arithmetic intensity is 1.72 FP operations per loaded or stored byte.

General properties

nb instructions	112
nb uops	112
loop length	448
used w registers	0
used x registers	5
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	32
nb stack references	1
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	48.50	48.50	0.00	0.00	4.50	4.50	0.00	0.00	0.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	48.50	48.50	20.00	20.00	4.50	4.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	55.94-112.68
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	14.00
Dispatch	48.50
DIV/SQRT	55.94-112.68
Data deps.	2.00
Overall L1	55.94-112.68

Vectorization ratios

INT

all	67%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	60%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	86%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	88%
fma	100%
div/sqrt	100%
other	73%

Vector efficiency ratios

INT

all	93%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	94%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	97%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	91%
fma	100%
div/sqrt	100%
other	96%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 112.68 cycles. At this rate:

2% of peak load performance is reached (2.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41096c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
LDR Z8, [X11, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z0, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUBS X15, X15, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (25.0%)
FSUB Z8.S, Z8.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LDR Z9, [X13, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z10, [X14, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z9.S, Z9.S, Z7.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FSUB Z10.S, Z10.S, Z16.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LDR Z6, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z13, [X14, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z13.S, Z13.S, Z16.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
ADD X11, X11, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X14, X14, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z11.S, Z8.S, Z8.S	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z11.S, P0/M, Z9.S, Z9.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z14, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z14.S, P0/M, Z10.S, Z10.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z11.S, Z14.S, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOVPRFX Z18, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLS Z18.S, P0/M, Z14.S, Z1.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCMGT P3.S, P0/Z, Z17.S, Z14.S	1	0	0	0	0	0	0	1	0	0	0	2	1	vect (100.0%)
FCMGT P4.S, P0/Z, Z14.S, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	2	1	vect (100.0%)
MOVPRFX Z12, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
EXT Z12.B, Z12.B, Z11.B, #16	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMAD Z18.S, P0/M, Z14.S, Z23.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
UUNPKLO Z5.D, Z11.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FSUB Z11.S, Z6.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LDR Z6, [X13, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X13, X13, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
UUNPKLO Z12.D, Z12.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMAD Z18.S, P0/M, Z14.S, Z24.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCVT Z5.D, P1/M, Z5.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FMUL Z15.S, Z11.S, Z11.S	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FCVT Z12.D, P1/M, Z12.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FMAD Z18.S, P0/M, Z14.S, Z25.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMAD Z18.S, P0/M, Z14.S, Z26.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FSUB Z6.S, Z6.S, Z7.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOVPRFX Z4, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FSQRT Z4.D, P1/M, Z12.D	1	0	0	0	0	0	0	1	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z12.D, Z12.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z15.S, P0/M, Z6.S, Z6.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FDIVR Z12.D, P1/M, Z12.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z0, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
EXT Z0.B, Z0.B, Z18.B, #16	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z15.S, P0/M, Z13.S, Z13.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
UUNPKLO Z18.D, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
UUNPKLO Z0.D, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FCVT Z18.D, P1/M, Z18.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FCVT Z0.D, P1/M, Z0.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FADD Z3.S, Z15.S, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOVPRFX Z2, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
EXT Z2.B, Z2.B, Z3.B, #16	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
UUNPKLO Z3.D, Z3.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
UUNPKLO Z2.D, Z2.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FCVT Z3.D, P1/M, Z3.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FCVT Z2.D, P1/M, Z2.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FNMLS Z0.D, P1/M, Z12.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z4, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FSQRT Z4.D, P1/M, Z5.D	1	0	0	0	0	0	0	1	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z5.D, Z5.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
MOVPRFX Z12, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FSQRT Z12.D, P1/M, Z2.D	1	0	0	0	0	0	0	1	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z2.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FDIVR Z5.D, P1/M, Z5.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIVR Z2.D, P1/M, Z2.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCVT Z0.S, P1/M, Z0.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
UZP1 Z0.S, Z0.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FNMSB Z4.D, P1/M, Z5.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z5, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLS Z5.S, P0/M, Z15.S, Z1.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMAD Z5.S, P0/M, Z15.S, Z23.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMAD Z5.S, P0/M, Z15.S, Z24.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCVT Z4.S, P1/M, Z4.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FMAD Z5.S, P0/M, Z15.S, Z25.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
UZP1 Z4.S, Z4.S, Z4.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMAD Z5.S, P0/M, Z15.S, Z26.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
SPLICE Z4.S, P2, Z4.S, Z0.S	1	0	0	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
LD1W {Z0.S}, P3/Z, [X12, #15, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGT P3.S, P0/Z, Z17.S, Z15.S	1	0	0	0	0	0	0	1	0	0	0	2	1	vect (100.0%)
MOVPRFX Z18, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
EXT Z18.B, Z18.B, Z5.B, #16	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
UUNPKLO Z5.D, Z5.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
UUNPKLO Z18.D, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FCVT Z5.D, P1/M, Z5.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FMUL Z0.S, Z0.S, Z4.S	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
CPY Z4.S, P4/Z, #255	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (3.1%)
FCVT Z18.D, P1/M, Z18.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
AND Z0.D, Z4.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FNMSB Z2.D, P1/M, Z12.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z18, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FSQRT Z18.D, P1/M, Z3.D	1	0	0	0	0	0	0	1	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z3.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z27.S, P0/M, Z0.S, Z8.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z28.S, P0/M, Z0.S, Z9.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z19.S, P0/M, Z0.S, Z10.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FDIVR Z3.D, P1/M, Z3.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCVT Z2.S, P1/M, Z2.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
UZP1 Z2.S, Z2.S, Z2.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FNMSB Z3.D, P1/M, Z18.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCVT Z3.S, P1/M, Z3.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
UZP1 Z0.S, Z3.S, Z3.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
SPLICE Z0.S, P2, Z0.S, Z2.S	1	0	0	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
LD1W {Z2.S}, P3/Z, [X12, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGT P3.S, P0/Z, Z15.S, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	2	1	vect (100.0%)
ADD X12, X12, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z0.S, Z2.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
CPY Z2.S, P3/Z, #255	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (3.1%)
AND Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z29.S, P0/M, Z0.S, Z11.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z30.S, P0/M, Z0.S, Z6.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z31.S, P0/M, Z0.S, Z13.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
B.NE 41096c <Step10_orig+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code