OV - exec - Loop 6

	Loop Id: 6	Module: exec	Source: Step10_orig.c:19-35	Coverage: 0.02%

0x410c08 LDR	Q4, [X13], #16    [3]

0x410c0c LDR	Q0, [X14], #16    [4]

0x410c10 ORR	V29.16B, V16.16B, V16.16B

0x410c14 ORR	V30.16B, V25.16B, V25.16B

0x410c18 FSUB	V11.4S, V4.4S, V21.4S

0x410c1c FSUB	V0.4S, V0.4S, V20.4S

0x410c20 LDR	Q4, [X12], #16    [2]

0x410c24 FMUL	V9.4S, V0.4S, V0.4S

0x410c28 FMLA	V9.4S, V11.4S, V11.4S

0x410c2c FSUB	V10.4S, V4.4S, V22.4S

0x410c30 FMLA	V9.4S, V10.4S, V10.4S

0x410c34 FCMGT	V4.4S, V23.4S, V9.4S

0x410c38 FMLA	V29.4S, V7.4S, V9.4S

0x410c3c CMPNE	P2.S, P0/Z, Z4.S, #0

0x410c40 FADD	V4.4S, V9.4S, V24.4S

0x410c44 ADDS	X10, X10, #4

0x410c48 UUNPKLO	Z4.D, Z4.S

0x410c4c FMLA	V30.4S, V9.4S, V29.4S

0x410c50 ORR	V29.16B, V26.16B, V26.16B

0x410c54 FCVT	Z4.D, P1/M, Z4.S

0x410c58 LD1W	{Z31.S}, P2/Z, [X11, MUL VL]    [1]

0x410c5c ADD	X11, X11, #16

0x410c60 FMLA	V29.4S, V9.4S, V30.4S

0x410c64 ORR	V30.16B, V27.16B, V27.16B

0x410c68 MOVPRFX	Z5, Z4

0x410c6c FSQRT	Z5.D, P1/M, Z4.D

0x410c70 FMUL	Z4.D, Z4.D, Z4.D

0x410c74 FDIVR	Z4.D, P1/M, Z4.D, Z6.D

0x410c78 FMLA	V30.4S, V9.4S, V29.4S

0x410c7c ORR	V29.16B, V28.16B, V28.16B

0x410c80 FMLA	V29.4S, V9.4S, V30.4S

0x410c84 UUNPKLO	Z29.D, Z29.S

0x410c88 FCVT	Z29.D, P1/M, Z29.S

0x410c8c FMAD	Z4.D, P1/M, Z5.D, Z29.D

0x410c90 FCMGT	V5.4S, V9.4S, #0.0000000

0x410c94 FCVT	Z4.S, P1/M, Z4.D

0x410c98 UZP1	Z4.S, Z4.S, Z4.S

0x410c9c FMUL	V4.4S, V31.4S, V4.4S

0x410ca0 AND	V4.16B, V5.16B, V4.16B

0x410ca4 FMLA	V17.4S, V0.4S, V4.4S

0x410ca8 FMLA	V19.4S, V11.4S, V4.4S

0x410cac FMLA	V18.4S, V10.4S, V4.4S

0x410cb0 B.NE	410c08

/home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 35

--------------------------------------------------------------------------------

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

32:

33:         xi = xi + f * dxc;

34:         yi = yi + f * dyc;

35:         zi = zi + f * dzc;

Coverage (%)	Name	Source Location	Module
►95.24+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►4.76+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	main.c:155	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.55 - 3.13
Bottlenecks	P6, P8,
Function	Step10_orig
Source	Step10_orig.c:19-35
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	13.99 - 28.17
CQA cycles if no scalar integer	13.99 - 28.17
CQA cycles if FP arith vectorized	13.99 - 28.17
CQA cycles if fully vectorized	13.99 - 28.17
Front-end cycles	5.38
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	9.00
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	1.50
P11 cycles	1.17
P12 cycles	1.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	13.99 - 28.17
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	43.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.87 - 4.40
Nb FLOP add-sub	16.00
Nb FLOP mul	12.00
Nb FLOP fma	44.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.14 - 2.29
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	3.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	95.12
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	80.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	93.75
Vector-efficiency ratio all	65.24
Vector-efficiency ratio load	62.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	66.67
Vector-efficiency ratio add_sub	45.00
Vector-efficiency ratio fma	54.55
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	75.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.55 - 3.13
Bottlenecks	P6, P8,
Function	Step10_orig
Source	Step10_orig.c:19-35
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	13.99 - 28.17
CQA cycles if no scalar integer	13.99 - 28.17
CQA cycles if FP arith vectorized	13.99 - 28.17
CQA cycles if fully vectorized	13.99 - 28.17
Front-end cycles	5.38
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	9.00
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	1.50
P11 cycles	1.17
P12 cycles	1.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	13.99 - 28.17
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	43.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.87 - 4.40
Nb FLOP add-sub	16.00
Nb FLOP mul	12.00
Nb FLOP fma	44.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.14 - 2.29
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	3.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	95.12
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	80.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	93.75
Vector-efficiency ratio all	65.24
Vector-efficiency ratio load	62.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	66.67
Vector-efficiency ratio add_sub	45.00
Vector-efficiency ratio fma	54.55
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	75.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	Step10_orig
Source file and lines	Step10_orig.c:19-35
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is highly vectorized. Only 65% of vector register length is used (average across all VPU instructions).

Details

95% of VPU instructions are used in vector version (process two or more data elements in vector registers):

80% of VPU addition or subtraction instructions are used in vector version.
93% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.17 to 8.50 cycles (3.31x speedup).

FMA

Detected 44 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 124 FP arithmetical operations:

60: addition or subtraction (44 inside FMA instructions)
56: multiply (44 inside FMA instructions)
4: divide
4: square root

The binary loop is loading 32 bytes.

Arithmetic intensity

Arithmetic intensity is 3.87 FP operations per loaded or stored byte.

General properties

nb instructions	43
nb uops	43
loop length	172
used w registers	0
used x registers	5
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	2
used v registers	23
used z registers	5
nb stack references	0
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.38 cycles
front end	5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.50	1.50	1.50	1.50	9.00	9.00	9.00	9.00	1.50	1.17	1.33	0.00	0.00
cycles	0.50	0.50	1.50	1.50	1.50	1.50	9.00	9.00	9.00	9.00	1.50	1.17	1.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	13.99-28.17
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	5.38
Dispatch	9.00
DIV/SQRT	13.99-28.17
Data deps.	2.00
Overall L1	13.99-28.17

Vectorization ratios

INT

all	87%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	90%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	95%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	80%
fma	100%
div/sqrt	100%
other	93%

Vector efficiency ratios

INT

all	67%
load	62%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	72%

all	64%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	50%
fma	54%
div/sqrt	100%
other	80%

INT+FP

all	65%
load	62%
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	45%
fma	54%
div/sqrt	100%
other	75%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.17 cycles. At this rate:

1% of peak load performance is reached (1.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410c08

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR Q4, [X13], #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q0, [X14], #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ORR V29.16B, V16.16B, V16.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
ORR V30.16B, V25.16B, V25.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V11.4S, V4.4S, V21.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V0.4S, V0.4S, V20.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDR Q4, [X12], #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V9.4S, V0.4S, V0.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMLA V9.4S, V11.4S, V11.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FSUB V10.4S, V4.4S, V22.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMLA V9.4S, V10.4S, V10.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FCMGT V4.4S, V23.4S, V9.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMLA V29.4S, V7.4S, V9.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
CMPNE P2.S, P0/Z, Z4.S, #0	1	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
FADD V4.4S, V9.4S, V24.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
ADDS X10, X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
UUNPKLO Z4.D, Z4.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMLA V30.4S, V9.4S, V29.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
ORR V29.16B, V26.16B, V26.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FCVT Z4.D, P1/M, Z4.S	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
LD1W {Z31.S}, P2/Z, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD X11, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMLA V29.4S, V9.4S, V30.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
ORR V30.16B, V27.16B, V27.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOVPRFX Z5, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FSQRT Z5.D, P1/M, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z4.D, Z4.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z4.D, P1/M, Z4.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMLA V30.4S, V9.4S, V29.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
ORR V29.16B, V28.16B, V28.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMLA V29.4S, V9.4S, V30.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
UUNPKLO Z29.D, Z29.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FCVT Z29.D, P1/M, Z29.S	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
FMAD Z4.D, P1/M, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FCMGT V5.4S, V9.4S, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FCVT Z4.S, P1/M, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
UZP1 Z4.S, Z4.S, Z4.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL V4.4S, V31.4S, V4.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
AND V4.16B, V5.16B, V4.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMLA V17.4S, V0.4S, V4.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V19.4S, V11.4S, V4.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V18.4S, V10.4S, V4.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
B.NE 410c08 <Step10_orig+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	Step10_orig
Source file and lines	Step10_orig.c:19-35
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is highly vectorized. Only 65% of vector register length is used (average across all VPU instructions).

Details

95% of VPU instructions are used in vector version (process two or more data elements in vector registers):

80% of VPU addition or subtraction instructions are used in vector version.
93% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.17 to 8.50 cycles (3.31x speedup).

FMA

Detected 44 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 124 FP arithmetical operations:

60: addition or subtraction (44 inside FMA instructions)
56: multiply (44 inside FMA instructions)
4: divide
4: square root

The binary loop is loading 32 bytes.

Arithmetic intensity

Arithmetic intensity is 3.87 FP operations per loaded or stored byte.

General properties

nb instructions	43
nb uops	43
loop length	172
used w registers	0
used x registers	5
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	2
used v registers	23
used z registers	5
nb stack references	0
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.38 cycles
front end	5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.50	1.50	1.50	1.50	9.00	9.00	9.00	9.00	1.50	1.17	1.33	0.00	0.00
cycles	0.50	0.50	1.50	1.50	1.50	1.50	9.00	9.00	9.00	9.00	1.50	1.17	1.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	13.99-28.17
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	5.38
Dispatch	9.00
DIV/SQRT	13.99-28.17
Data deps.	2.00
Overall L1	13.99-28.17

Vectorization ratios

INT

all	87%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	90%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	95%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	80%
fma	100%
div/sqrt	100%
other	93%

Vector efficiency ratios

INT

all	67%
load	62%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	72%

all	64%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	50%
fma	54%
div/sqrt	100%
other	80%

INT+FP

all	65%
load	62%
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	45%
fma	54%
div/sqrt	100%
other	75%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.17 cycles. At this rate:

1% of peak load performance is reached (1.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410c08

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR Q4, [X13], #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q0, [X14], #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ORR V29.16B, V16.16B, V16.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
ORR V30.16B, V25.16B, V25.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V11.4S, V4.4S, V21.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V0.4S, V0.4S, V20.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDR Q4, [X12], #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V9.4S, V0.4S, V0.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMLA V9.4S, V11.4S, V11.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FSUB V10.4S, V4.4S, V22.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMLA V9.4S, V10.4S, V10.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FCMGT V4.4S, V23.4S, V9.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMLA V29.4S, V7.4S, V9.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
CMPNE P2.S, P0/Z, Z4.S, #0	1	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
FADD V4.4S, V9.4S, V24.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
ADDS X10, X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
UUNPKLO Z4.D, Z4.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMLA V30.4S, V9.4S, V29.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
ORR V29.16B, V26.16B, V26.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FCVT Z4.D, P1/M, Z4.S	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
LD1W {Z31.S}, P2/Z, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD X11, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMLA V29.4S, V9.4S, V30.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
ORR V30.16B, V27.16B, V27.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOVPRFX Z5, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FSQRT Z5.D, P1/M, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z4.D, Z4.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z4.D, P1/M, Z4.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMLA V30.4S, V9.4S, V29.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
ORR V29.16B, V28.16B, V28.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMLA V29.4S, V9.4S, V30.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
UUNPKLO Z29.D, Z29.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FCVT Z29.D, P1/M, Z29.S	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
FMAD Z4.D, P1/M, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FCMGT V5.4S, V9.4S, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FCVT Z4.S, P1/M, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
UZP1 Z4.S, Z4.S, Z4.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL V4.4S, V31.4S, V4.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
AND V4.16B, V5.16B, V4.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMLA V17.4S, V0.4S, V4.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V19.4S, V11.4S, V4.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V18.4S, V10.4S, V4.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
B.NE 410c08 <Step10_orig+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code