OV - exec - Function Step10

	Function: Step10_orig	Module: exec	Source: Step10_orig.c:10-41 [...]	Coverage (incl. loops): 97.71% \| (excl. loops): 0.03%

/home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 10 - 41

--------------------------------------------------------------------------------

10: {

[...]

17:     xi = 0.; yi = 0.; zi = 0.;

18:

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

32:

33:         xi = xi + f * dxc;

34:         yi = yi + f * dyc;

35:         zi = zi + f * dzc;

36:     }

37:

38:     *dxi = xi;

39:     *dyi = yi;

40:     *dzi = zi;

41: }

0x410a00 CMP	W0, #0

0x410a04 B.LE	410d98

0x410a08 STP	D9, D10, [SP, #960]!

0x410a0c SUB	W8, W0, #1

0x410a10 STP	D13, D14, [SP, #32]

0x410a14 STR	D15, [SP, #48]

0x410a18 CMP	W8, #6

0x410a1c B.LS	410dac

0x410a20 MOVZ	X8, #0

0x410a24 AND	X16, X0, #0x0

0x410a28 PTRUE	P7.B, VL32

0x410a2c ADRP	X15,

0x410a30 ADRP	X14,

0x410a34 DUP	Z25.S, #0

0x410a38 ADRP	X13,

0x410a3c ADRP	X12,

0x410a40 ORR	Z23.D, Z25.D, Z25.D

0x410a44 ADRP	X11,

0x410a48 ADRP	X10,

0x410a4c ORR	Z24.D, Z25.D, Z25.D

0x410a50 ADD	X17, X15, #4

0x410a54 ADD	X18, X14, #8

0x410a58 LD1RW	{Z13.S}, P7/Z, [X17]

0x410a5c ADD	X9, X13, #12

0x410a60 ADD	X15, X12, #16

0x410a64 LD1RW	{Z14.S}, P7/Z, [X18]

0x410a68 ADD	X14, X11, #20

0x410a6c ADD	X13, X10, #24

0x410a70 LD1RW	{Z15.S}, P7/Z, [X9]

0x410a74 LD1RW	{Z5.S}, P7/Z, [X15]

0x410a78 LD1RW	{Z6.S}, P7/Z, [X14]

0x410a7c LD1RW	{Z7.S}, P7/Z, [X13]

0x410a80 ORR	Z16.D, Z25.D, Z25.D

0x410a84 DUP	Z17.S, Z0.S[0]

0x410a88 DUP	Z18.S, Z1.S[0]

0x410a8c DUP	Z19.S, Z2.S[0]

0x410a90 DUP	Z20.S, Z3.S[0]

0x410a94 DUP	Z21.S, Z4.S[0]

0x410a98 FDUP	Z22.D, #112

0x410a9c STP	D11, D12, [SP, #16]

(4) 0x410aa0 LD1W	{Z26.S}, P7/Z, [X2, X8,LSL #2]

(4) 0x410aa4 LD1W	{Z27.S}, P7/Z, [X1, X8,LSL #2]

(4) 0x410aa8 FSUB	Z26.S, Z26.S, Z18.S

(4) 0x410aac FSUB	Z27.S, Z27.S, Z17.S

(4) 0x410ab0 LD1W	{Z28.S}, P7/Z, [X3, X8,LSL #2]

(4) 0x410ab4 FMUL	Z11.S, Z26.S, Z26.S

(4) 0x410ab8 FSUB	Z28.S, Z28.S, Z19.S

(4) 0x410abc FMLA	Z11.S, P7/M, Z27.S, Z27.S

(4) 0x410ac0 FMLA	Z11.S, P7/M, Z28.S, Z28.S

(4) 0x410ac4 FCMGT	P6.S, P7/Z, Z20.S, Z11.S

(4) 0x410ac8 FADD	Z10.S, Z11.S, Z21.S

(4) 0x410acc LD1W	{Z12.S}, P6/Z, [X4, X8,LSL #2]

(4) 0x410ad0 ZIP2	Z30.S, Z10.S, Z10.S

(4) 0x410ad4 ADD	X8, X8, #8

(4) 0x410ad8 FCVT	Z30.D, P7/M, Z30.S

(4) 0x410adc FCMGT	P0.S, P7/Z, Z11.S, #0.0000000

(4) 0x410ae0 MOVPRFX	Z29, Z14

(4) 0x410ae4 FMLA	Z29.S, P7/M, Z11.S, Z13.S

(4) 0x410ae8 MOVPRFX	Z31, Z30

(4) 0x410aec FSQRT	Z31.D, P7/M, Z30.D

(4) 0x410af0 FMAD	Z29.S, P7/M, Z11.S, Z15.S

(4) 0x410af4 FMUL	Z31.D, Z30.D, Z31.D

(4) 0x410af8 FMAD	Z29.S, P7/M, Z11.S, Z5.S

(4) 0x410afc ZIP1	Z10.S, Z10.S, Z10.S

(4) 0x410b00 FMAD	Z29.S, P7/M, Z11.S, Z6.S

(4) 0x410b04 FCVT	Z10.D, P7/M, Z10.S

(4) 0x410b08 FMAD	Z29.S, P7/M, Z11.S, Z7.S

(4) 0x410b0c SEL	Z12.S, P6, Z12.S, Z16.S

(4) 0x410b10 ZIP2	Z9.S, Z29.S, Z29.S

(4) 0x410b14 MOVPRFX	Z30, Z10

(4) 0x410b18 FSQRT	Z30.D, P7/M, Z10.D

(4) 0x410b1c ZIP1	Z29.S, Z29.S, Z29.S

(4) 0x410b20 FCVT	Z9.D, P7/M, Z9.S

(4) 0x410b24 FCVT	Z29.D, P7/M, Z29.S

(4) 0x410b28 FDIVR	Z31.D, P7/M, Z31.D, Z22.D

(4) 0x410b2c FMUL	Z10.D, Z10.D, Z30.D

(4) 0x410b30 FADD	Z9.D, Z31.D, Z9.D

(4) 0x410b34 FDIVR	Z10.D, P7/M, Z10.D, Z22.D

(4) 0x410b38 FCVT	Z9.S, P7/M, Z9.D

(4) 0x410b3c FADD	Z29.D, Z10.D, Z29.D

(4) 0x410b40 FCVT	Z29.S, P7/M, Z29.D

(4) 0x410b44 UZP1	Z11.S, Z9.S, Z29.S

(4) 0x410b48 FMUL	Z12.S, Z11.S, Z12.S

(4) 0x410b4c FMLA	Z23.S, P0/M, Z26.S, Z12.S

(4) 0x410b50 FMLA	Z24.S, P0/M, Z27.S, Z12.S

(4) 0x410b54 FMLA	Z25.S, P0/M, Z28.S, Z12.S

(4) 0x410b58 CMP	X16, X8

(4) 0x410b5c B.NE	410aa0

0x410b60 AND	W9, W0, #0xfffffff8

0x410b64 LDP	D11, D12, [SP, #16]

0x410b68 FADDV	S25, P7, Z25.S

0x410b6c FADDV	S23, P7, Z23.S

0x410b70 FADDV	S24, P7, Z24.S

0x410b74 CMP	W0, W9

0x410b78 B.EQ	410d74

0x410b7c SBFM	X16, X9, #0, #31

0x410b80 MOVZ	W18, #35234

0x410b84 FMOV	D13, #1.0000000

0x410b88 MOVZ	W15, #63002

0x410b8c MOVZ	W14, #18267

0x410b90 LDR	S14, [X2, X16,LSL #2]

0x410b94 MOVZ	W12, #6647

0x410b98 MOVZ	W11, #52448

0x410b9c MOVZ	W10, #58683

0x410ba0 ORN	W17, WZR, W9

0x410ba4 LDR	S15, [X1, X16,LSL #2]

0x410ba8 MOVK	W18, #13765

0x410bac MOVK	W15, #47229

0x410bb0 MOVK	W14, #14991

0x410bb4 MOVK	W12, #48188

0x410bb8 LDR	S7, [X3, X16,LSL #2]

0x410bbc MOVK	W11, #15769

0x410bc0 MOVK	W10, #48777

0x410bc4 ADD	W9, W0, W17

0x410bc8 FMOV	S5, W18

0x410bcc FSUB	S18, S14, S1

0x410bd0 AND	W13, W9, #0x1

0x410bd4 FMOV	S6, W15

0x410bd8 FSUB	S17, S15, S0

0x410bdc FMOV	S20, W14

0x410be0 FSUB	S19, S7, S2

0x410be4 FMOV	S26, W12

0x410be8 FMUL	S16, S18, S18

0x410bec FMOV	S22, W11

0x410bf0 FMOV	S21, W10

0x410bf4 FMADD	S27, S17, S17, S16

0x410bf8 FMADD	S28, S19, S19, S27

0x410bfc FCMPE	S3, S28

0x410c00 B.GT	410d90

0x410c04 MOVI	V10.2S, #0

0x410c08 FCMPE	S28, #0

0x410c0c B.LS	410c54

0x410c10 FADD	S31, S4, S28

0x410c14 FMADD	S30, S28, S5, S6

0x410c18 FMADD	S9, S28, S30, S20

0x410c1c FCVT	D29, S31

0x410c20 FMADD	S15, S28, S9, S26

0x410c24 FSQRT	D14, D29

0x410c28 FMADD	S7, S28, S15, S22

0x410c2c FMADD	S16, S28, S7, S21

0x410c30 FMUL	D27, D29, D14

0x410c34 FCVT	D28, S16

0x410c38 FDIV	D31, D13, D27

0x410c3c FADD	D30, D31, D28

0x410c40 FCVT	S9, D30

0x410c44 FMUL	S10, S9, S10

0x410c48 FMADD	S24, S17, S10, S24

0x410c4c FMADD	S23, S18, S10, S23

0x410c50 FMADD	S25, S19, S10, S25

0x410c54 ADD	X8, X16, #1

0x410c58 CMP	W0, W8

0x410c5c B.LE	410d74

0x410c60 CBNZ	W13, 410ce8

(3) 0x410c64 LDR	S29, [X2, X8,LSL #2]

(3) 0x410c68 MOVI	V10.2S, #0

(3) 0x410c6c LDR	S7, [X1, X8,LSL #2]

(3) 0x410c70 LDR	S27, [X3, X8,LSL #2]

(3) 0x410c74 FSUB	S18, S29, S1

(3) 0x410c78 FSUB	S19, S7, S0

(3) 0x410c7c FSUB	S17, S27, S2

(3) 0x410c80 FMUL	S30, S18, S18

(3) 0x410c84 FMADD	S15, S19, S19, S30

(3) 0x410c88 FMADD	S28, S17, S17, S15

(3) 0x410c8c FCMPE	S3, S28

(3) 0x410c90 B.LS	410c98

(3) 0x410c94 LDR	S10, [X4, X8,LSL #2]

(3) 0x410c98 FCMPE	S28, #0

(3) 0x410c9c B.LS	410ce4

(3) 0x410ca0 FADD	S14, S4, S28

(3) 0x410ca4 FMADD	S31, S28, S5, S6

(3) 0x410ca8 FMADD	S16, S28, S31, S20

(3) 0x410cac FCVT	D9, S14

(3) 0x410cb0 FMADD	S29, S28, S16, S26

(3) 0x410cb4 FSQRT	D7, D9

(3) 0x410cb8 FMADD	S27, S28, S29, S22

(3) 0x410cbc FMADD	S15, S28, S27, S21

(3) 0x410cc0 FMUL	D30, D9, D7

(3) 0x410cc4 FCVT	D28, S15

(3) 0x410cc8 FDIV	D14, D13, D30

(3) 0x410ccc FADD	D31, D14, D28

(3) 0x410cd0 FCVT	S16, D31

(3) 0x410cd4 FMUL	S10, S16, S10

(3) 0x410cd8 FMADD	S24, S19, S10, S24

(3) 0x410cdc FMADD	S23, S18, S10, S23

(3) 0x410ce0 FMADD	S25, S17, S10, S25

(3) 0x410ce4 ADD	X8, X8, #1

(3) 0x410ce8 LDR	S18, [X2, X8,LSL #2]

(3) 0x410cec MOVI	V9.2S, #0

(3) 0x410cf0 LDR	S17, [X1, X8,LSL #2]

(3) 0x410cf4 LDR	S19, [X3, X8,LSL #2]

(3) 0x410cf8 FSUB	S29, S18, S1

(3) 0x410cfc FSUB	S7, S17, S0

(3) 0x410d00 FSUB	S27, S19, S2

(3) 0x410d04 FMUL	S15, S29, S29

(3) 0x410d08 FMADD	S14, S7, S7, S15

(3) 0x410d0c FMADD	S28, S27, S27, S14

(3) 0x410d10 FCMPE	S3, S28

(3) 0x410d14 B.LS	410d1c

(3) 0x410d18 LDR	S9, [X4, X8,LSL #2]

(3) 0x410d1c FCMPE	S28, #0

(3) 0x410d20 B.LS	410d68

(3) 0x410d24 FADD	S31, S4, S28

(3) 0x410d28 FMADD	S16, S28, S5, S6

(3) 0x410d2c FMADD	S10, S28, S16, S20

(3) 0x410d30 FCVT	D30, S31

(3) 0x410d34 FMADD	S18, S28, S10, S26

(3) 0x410d38 FSQRT	D17, D30

(3) 0x410d3c FMADD	S19, S28, S18, S22

(3) 0x410d40 FMADD	S15, S28, S19, S21

(3) 0x410d44 FMUL	D14, D30, D17

(3) 0x410d48 FCVT	D28, S15

(3) 0x410d4c FDIV	D31, D13, D14

(3) 0x410d50 FADD	D16, D31, D28

(3) 0x410d54 FCVT	S10, D16

(3) 0x410d58 FMUL	S9, S10, S9

(3) 0x410d5c FMADD	S24, S7, S9, S24

(3) 0x410d60 FMADD	S23, S29, S9, S23

(3) 0x410d64 FMADD	S25, S27, S9, S25

(3) 0x410d68 ADD	X8, X8, #1

(3) 0x410d6c CMP	W0, W8

(3) 0x410d70 B.GT	410c64

0x410d74 LDR	D15, [SP, #48]

0x410d78 LDP	D13, D14, [SP, #32]

0x410d7c LDP	D9, D10, [SP], #64

0x410d80 STR	S24, [X5]

0x410d84 STR	S23, [X6]

0x410d88 STR	S25, [X7]

0x410d8c RET

0x410d90 LDR	S10, [X4, X16,LSL #2]

0x410d94 B	410c08

0x410d98 MOVI	V25.2S, #0

0x410d9c STR	S25, [X5]

0x410da0 STR	S25, [X6]

0x410da4 STR	S25, [X7]

0x410da8 RET

0x410dac MOVI	V25.2S, #0

0x410db0 MOVZ	W9, #0

0x410db4 FMOV	S23, S25

0x410db8 FMOV	S24, S25

0x410dbc B	410b7c

Coverage (%)	Name	Source Location	Module
►98.44+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.56+	GOMP_parallel		libgomp.so.1.0.0
○	main	main.c:155	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	main.c:69	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run gcc_2

Source file and lines	Step10_orig.c:10-41
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:10,17-41.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.75 to 11.50 cycles (1.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 15.75 to 9.68 cycles (1.63x speedup).

Details

19% of VPU instructions are used in vector version (process two or more data elements in vector registers):

21% of VPU loads are used in vector version.
30% of VPU stores are used in vector version.
27% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
21% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 10 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 54 FP arithmetical operations:

39: addition or subtraction (10 inside FMA instructions)
13: multiply (10 inside FMA instructions)
1: divide
1: square root

The binary function is loading 30 bytes. The binary function is storing 18 bytes.

Arithmetic intensity

Arithmetic intensity is 1.12 FP operations per loaded or stored byte.

General properties

nb instructions	124
nb uops	124
loop length	496
used w registers	12
used x registers	19
used b registers	0
used h registers	0
used s registers	28
used d registers	12
used q registers	0
used v registers	2
used z registers	21
nb stack references	8
ADD-SUB / MUL ratio	2.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.50 cycles
front end	15.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	10.25	10.25	10.25	10.25	15.75	15.75	15.75	15.75	8.00	8.00	8.00	0.00	0.00
cycles	5.50	5.50	10.25	10.25	10.25	10.25	15.75	15.75	15.75	15.75	8.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

3.50-7.24

Cycles summary

Front-end	15.50
Dispatch	15.75
DIV/SQRT	3.50-7.24
Overall L1	15.75

Vectorization ratios

INT

all	28%
load	21%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	36%

all	7%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	37%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	19%
load	21%
store	30%
mul	0%
add-sub	27%
fma	0%
div/sqrt	0%
other	21%

Vector efficiency ratios

INT

all	34%
load	21%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	47%

all	21%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	16%
add-sub	46%
fma	12%
div/sqrt	25%
other	13%

INT+FP

all	28%
load	21%
store	25%
mul	16%
add-sub	40%
fma	12%
div/sqrt	25%
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.75 cycles. At this rate:

1% of peak load performance is reached (1.90 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 410a00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 410d98 <Step10_orig+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D9, D10, [SP, #960]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
SUB W8, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP D13, D14, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR D15, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
CMP W8, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LS 410dac <Step10_orig+0x3ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
AND X16, X0, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P7.B, VL32	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADRP X15, <420a2c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X14, <420a30>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z25.S, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
ADRP X13, <420a38>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X12, <420a3c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR Z23.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADRP X11, <420a44>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X10, <420a48>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR Z24.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD X17, X15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1RW {Z13.S}, P7/Z, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	scal (12.5%)
ADD X9, X13, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1RW {Z14.S}, P7/Z, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	scal (12.5%)
ADD X14, X11, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X10, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1RW {Z15.S}, P7/Z, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	scal (12.5%)
LD1RW {Z5.S}, P7/Z, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	scal (12.5%)
LD1RW {Z6.S}, P7/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	scal (12.5%)
LD1RW {Z7.S}, P7/Z, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	scal (12.5%)
ORR Z16.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z17.S, Z0.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z18.S, Z1.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z19.S, Z2.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z20.S, Z3.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z21.S, Z4.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FDUP Z22.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
STP D11, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
AND W9, W0, #0xfffffff8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP D11, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FADDV S25, P7, Z25.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	11	2.50	vect (100.0%)
FADDV S23, P7, Z23.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	11	2.50	vect (100.0%)
FADDV S24, P7, Z24.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	11	2.50	vect (100.0%)
CMP W0, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 410d74 <Step10_orig+0x374>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X16, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W18, #35234	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D13, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOVZ W15, #63002	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W14, #18267	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR S14, [X2, X16,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
MOVZ W12, #6647	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W11, #52448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W10, #58683	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORN W17, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR S15, [X1, X16,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
MOVK W18, #13765	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W15, #47229	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W14, #14991	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W12, #48188	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR S7, [X3, X16,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
MOVK W11, #15769	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W10, #48777	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W0, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S5, W18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FSUB S18, S14, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
AND W13, W9, #0x1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S6, W15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FSUB S17, S15, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMOV S20, W14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FSUB S19, S7, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMOV S26, W12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMUL S16, S18, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
FMOV S22, W11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMOV S21, W10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMADD S27, S17, S17, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S28, S19, S19, S27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FCMPE S3, S28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
B.GT 410d90 <Step10_orig+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI V10.2S, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FCMPE S28, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
B.LS 410c54 <Step10_orig+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD S31, S4, S28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMADD S30, S28, S5, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S9, S28, S30, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FCVT D29, S31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FMADD S15, S28, S9, S26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FSQRT D14, D29	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1.75-3.75	scal (25.0%)
FMADD S7, S28, S15, S22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S16, S28, S7, S21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMUL D27, D29, D14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCVT D28, S16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FDIV D31, D13, D27	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FADD D30, D31, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCVT S9, D30	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (25.0%)
FMUL S10, S9, S10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
FMADD S24, S17, S10, S24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S23, S18, S10, S23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S25, S19, S10, S25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
ADD X8, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 410d74 <Step10_orig+0x374>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ W13, 410ce8 <Step10_orig+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDP D13, D14, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDP D9, D10, [SP], #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR S24, [X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (12.5%)
STR S23, [X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (12.5%)
STR S25, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (12.5%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR S10, [X4, X16,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
B 410c08 <Step10_orig+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI V25.2S, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
STR S25, [X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (12.5%)
STR S25, [X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (12.5%)
STR S25, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (12.5%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI V25.2S, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
MOVZ W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S23, S25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMOV S24, S25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
B 410b7c <Step10_orig+0x17c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run gcc_2

Source file and lines	Step10_orig.c:10-41
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:10,17-41.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

19% of VPU instructions are used in vector version (process two or more data elements in vector registers):

21% of VPU loads are used in vector version.
30% of VPU stores are used in vector version.
27% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
21% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 10 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 54 FP arithmetical operations:

39: addition or subtraction (10 inside FMA instructions)
13: multiply (10 inside FMA instructions)
1: divide
1: square root

The binary function is loading 30 bytes. The binary function is storing 18 bytes.

Arithmetic intensity

Arithmetic intensity is 1.12 FP operations per loaded or stored byte.

General properties

nb instructions	124
nb uops	124
loop length	496
used w registers	12
used x registers	19
used b registers	0
used h registers	0
used s registers	28
used d registers	12
used q registers	0
used v registers	2
used z registers	21
nb stack references	8
ADD-SUB / MUL ratio	2.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.50 cycles
front end	15.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	10.25	10.25	10.25	10.25	15.75	15.75	15.75	15.75	8.00	8.00	8.00	0.00	0.00
cycles	5.50	5.50	10.25	10.25	10.25	10.25	15.75	15.75	15.75	15.75	8.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

3.50-7.24

Cycles summary

Front-end	15.50
Dispatch	15.75
DIV/SQRT	3.50-7.24
Overall L1	15.75

Vectorization ratios

INT

all	28%
load	21%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	36%

all	7%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	37%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	19%
load	21%
store	30%
mul	0%
add-sub	27%
fma	0%
div/sqrt	0%
other	21%

Vector efficiency ratios

INT

all	34%
load	21%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	47%

all	21%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	16%
add-sub	46%
fma	12%
div/sqrt	25%
other	13%

INT+FP

all	28%
load	21%
store	25%
mul	16%
add-sub	40%
fma	12%
div/sqrt	25%
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.75 cycles. At this rate:

1% of peak load performance is reached (1.90 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 410a00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 410d98 <Step10_orig+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D9, D10, [SP, #960]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
SUB W8, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP D13, D14, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR D15, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
CMP W8, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LS 410dac <Step10_orig+0x3ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
AND X16, X0, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P7.B, VL32	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADRP X15, <420a2c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X14, <420a30>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z25.S, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
ADRP X13, <420a38>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X12, <420a3c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR Z23.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADRP X11, <420a44>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X10, <420a48>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR Z24.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD X17, X15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1RW {Z13.S}, P7/Z, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	scal (12.5%)
ADD X9, X13, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1RW {Z14.S}, P7/Z, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	scal (12.5%)
ADD X14, X11, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X10, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1RW {Z15.S}, P7/Z, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	scal (12.5%)
LD1RW {Z5.S}, P7/Z, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	scal (12.5%)
LD1RW {Z6.S}, P7/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	scal (12.5%)
LD1RW {Z7.S}, P7/Z, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	scal (12.5%)
ORR Z16.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z17.S, Z0.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z18.S, Z1.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z19.S, Z2.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z20.S, Z3.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z21.S, Z4.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FDUP Z22.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
STP D11, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
AND W9, W0, #0xfffffff8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP D11, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FADDV S25, P7, Z25.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	11	2.50	vect (100.0%)
FADDV S23, P7, Z23.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	11	2.50	vect (100.0%)
FADDV S24, P7, Z24.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	11	2.50	vect (100.0%)
CMP W0, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 410d74 <Step10_orig+0x374>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X16, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W18, #35234	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D13, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOVZ W15, #63002	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W14, #18267	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR S14, [X2, X16,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
MOVZ W12, #6647	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W11, #52448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W10, #58683	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORN W17, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR S15, [X1, X16,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
MOVK W18, #13765	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W15, #47229	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W14, #14991	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W12, #48188	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR S7, [X3, X16,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
MOVK W11, #15769	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W10, #48777	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W0, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S5, W18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FSUB S18, S14, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
AND W13, W9, #0x1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S6, W15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FSUB S17, S15, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMOV S20, W14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FSUB S19, S7, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMOV S26, W12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMUL S16, S18, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
FMOV S22, W11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMOV S21, W10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMADD S27, S17, S17, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S28, S19, S19, S27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FCMPE S3, S28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
B.GT 410d90 <Step10_orig+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI V10.2S, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FCMPE S28, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
B.LS 410c54 <Step10_orig+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD S31, S4, S28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMADD S30, S28, S5, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S9, S28, S30, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FCVT D29, S31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FMADD S15, S28, S9, S26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FSQRT D14, D29	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1.75-3.75	scal (25.0%)
FMADD S7, S28, S15, S22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S16, S28, S7, S21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMUL D27, D29, D14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCVT D28, S16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FDIV D31, D13, D27	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FADD D30, D31, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCVT S9, D30	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (25.0%)
FMUL S10, S9, S10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
FMADD S24, S17, S10, S24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S23, S18, S10, S23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S25, S19, S10, S25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
ADD X8, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 410d74 <Step10_orig+0x374>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ W13, 410ce8 <Step10_orig+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDP D13, D14, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDP D9, D10, [SP], #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR S24, [X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (12.5%)
STR S23, [X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (12.5%)
STR S25, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (12.5%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR S10, [X4, X16,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
B 410c08 <Step10_orig+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI V25.2S, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
STR S25, [X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (12.5%)
STR S25, [X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (12.5%)
STR S25, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (12.5%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI V25.2S, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
MOVZ W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S23, S25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMOV S24, S25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
B 410b7c <Step10_orig+0x17c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼Step10_orig–	97.71	27.94
○Loop 4 - Step10_orig.c:19-31 - exec	97.67	27.64
○Loop 3 - Step10_orig.c:19-35 - exec	0.01	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code