OV - exec - Loop 3

	Loop Id: 3	Module: exec	Source: Step10_orig.c:19-35	Coverage: 0.01%

0x410c64 LDR	S29, [X2, X8,LSL #2]    [3]

0x410c68 MOVI	V10.2S, #0

0x410c6c LDR	S7, [X1, X8,LSL #2]    [2]

0x410c70 LDR	S27, [X3, X8,LSL #2]    [4]

0x410c74 FSUB	S18, S29, S1

0x410c78 FSUB	S19, S7, S0

0x410c7c FSUB	S17, S27, S2

0x410c80 FMUL	S30, S18, S18

0x410c84 FMADD	S15, S19, S19, S30

0x410c88 FMADD	S28, S17, S17, S15

0x410c8c FCMPE	S3, S28

0x410c90 B.LS	410c98

0x410c94 LDR	S10, [X4, X8,LSL #2]    [1]

0x410c98 FCMPE	S28, #0

0x410c9c B.LS	410ce4

0x410ca0 FADD	S14, S4, S28

0x410ca4 FMADD	S31, S28, S5, S6

0x410ca8 FMADD	S16, S28, S31, S20

0x410cac FCVT	D9, S14

0x410cb0 FMADD	S29, S28, S16, S26

0x410cb4 FSQRT	D7, D9

0x410cb8 FMADD	S27, S28, S29, S22

0x410cbc FMADD	S15, S28, S27, S21

0x410cc0 FMUL	D30, D9, D7

0x410cc4 FCVT	D28, S15

0x410cc8 FDIV	D14, D13, D30

0x410ccc FADD	D31, D14, D28

0x410cd0 FCVT	S16, D31

0x410cd4 FMUL	S10, S16, S10

0x410cd8 FMADD	S24, S19, S10, S24

0x410cdc FMADD	S23, S18, S10, S23

0x410ce0 FMADD	S25, S17, S10, S25

0x410ce4 ADD	X8, X8, #1

0x410ce8 LDR	S18, [X2, X8,LSL #2]    [3]

0x410cec MOVI	V9.2S, #0

0x410cf0 LDR	S17, [X1, X8,LSL #2]    [2]

0x410cf4 LDR	S19, [X3, X8,LSL #2]    [4]

0x410cf8 FSUB	S29, S18, S1

0x410cfc FSUB	S7, S17, S0

0x410d00 FSUB	S27, S19, S2

0x410d04 FMUL	S15, S29, S29

0x410d08 FMADD	S14, S7, S7, S15

0x410d0c FMADD	S28, S27, S27, S14

0x410d10 FCMPE	S3, S28

0x410d14 B.LS	410d1c

0x410d18 LDR	S9, [X4, X8,LSL #2]    [1]

0x410d1c FCMPE	S28, #0

0x410d20 B.LS	410d68

0x410d24 FADD	S31, S4, S28

0x410d28 FMADD	S16, S28, S5, S6

0x410d2c FMADD	S10, S28, S16, S20

0x410d30 FCVT	D30, S31

0x410d34 FMADD	S18, S28, S10, S26

0x410d38 FSQRT	D17, D30

0x410d3c FMADD	S19, S28, S18, S22

0x410d40 FMADD	S15, S28, S19, S21

0x410d44 FMUL	D14, D30, D17

0x410d48 FCVT	D28, S15

0x410d4c FDIV	D31, D13, D14

0x410d50 FADD	D16, D31, D28

0x410d54 FCVT	S10, D16

0x410d58 FMUL	S9, S10, S9

0x410d5c FMADD	S24, S7, S9, S24

0x410d60 FMADD	S23, S29, S9, S23

0x410d64 FMADD	S25, S27, S9, S25

0x410d68 ADD	X8, X8, #1

0x410d6c CMP	W0, W8

0x410d70 B.GT	410c64

/home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 35

--------------------------------------------------------------------------------

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

32:

33:         xi = xi + f * dxc;

34:         yi = yi + f * dyc;

35:         zi = zi + f * dzc;

Coverage (%)	Name	Module
►100.00+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	4.87 - 5.43
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	3.71 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.53 - 1.11
Bottlenecks	P6, P8,
Function	Step10_orig
Source	Step10_orig.c:19-35
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.00 - 14.48
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	5.50 - 7.24
CQA cycles if fully vectorized	3.50 - 7.24
Front-end cycles	8.50
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.75
P6 cycles	13.00
P7 cycles	13.00
P8 cycles	13.00
P9 cycles	13.00
P10 cycles	2.67
P11 cycles	2.67
P12 cycles	2.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	7.01 - 14.48
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	68.00
Nb uops	68.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	4.62 - 4.14
Nb FLOP add-sub	10.00
Nb FLOP mul	6.00
Nb FLOP fma	20.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	2.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.66 - 1.85
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	14.58
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	16.67
Vector-efficiency ratio add_sub	15.00
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	14.58

Metric	Value
CQA speedup if no scalar integer	4.87 - 5.43
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	3.71 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.53 - 1.11
Bottlenecks	P6, P8,
Function	Step10_orig
Source	Step10_orig.c:19-35
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.00 - 14.48
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	5.50 - 7.24
CQA cycles if fully vectorized	3.50 - 7.24
Front-end cycles	8.50
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.75
P6 cycles	13.00
P7 cycles	13.00
P8 cycles	13.00
P9 cycles	13.00
P10 cycles	2.67
P11 cycles	2.67
P12 cycles	2.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	7.01 - 14.48
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	68.00
Nb uops	68.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	4.62 - 4.14
Nb FLOP add-sub	10.00
Nb FLOP mul	6.00
Nb FLOP fma	20.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	2.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.66 - 1.85
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	14.58
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	16.67
Vector-efficiency ratio add_sub	15.00
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	14.58

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	Step10_orig
Source file and lines	Step10_orig.c:19-35
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.48 to 2.67 cycles (5.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 14.48 to 7.24 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.48 to 12.00 cycles (1.21x speedup).

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 60 FP arithmetical operations:

30: addition or subtraction (20 inside FMA instructions)
26: multiply (20 inside FMA instructions)
2: divide
2: square root

The binary loop is loading 24 bytes.

Arithmetic intensity

Arithmetic intensity is 2.50 FP operations per loaded or stored byte.

General properties

nb instructions	68
nb uops	68
loop length	272
used w registers	2
used x registers	5
used b registers	0
used h registers	0
used s registers	28
used d registers	9
used q registers	0
used v registers	2
used z registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	0.75	0.75	0.75	0.75	13.00	13.00	13.00	13.00	2.67	2.67	2.67	0.00	0.00
cycles	2.50	2.50	0.75	0.75	0.75	0.75	13.00	13.00	13.00	13.00	2.67	2.67	2.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

7.01-14.48

Cycles summary

Front-end	8.50
Dispatch	13.00
DIV/SQRT	7.01-14.48
Overall L1	13.00-14.48

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	15%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	16%
add-sub	15%
fma	12%
div/sqrt	25%
other	15%

INT+FP

all	14%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	16%
add-sub	15%
fma	12%
div/sqrt	25%
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.48 cycles. At this rate:

1% of peak load performance is reached (1.66 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410ce8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR S29, [X2, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
MOVI V10.2S, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
LDR S7, [X1, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
LDR S27, [X3, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
FSUB S18, S29, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FSUB S19, S7, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FSUB S17, S27, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMUL S30, S18, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
FMADD S15, S19, S19, S30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S28, S17, S17, S15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FCMPE S3, S28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
B.LS 410c98 <Step10_orig+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR S10, [X4, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
FCMPE S28, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
B.LS 410ce4 <Step10_orig+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD S14, S4, S28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMADD S31, S28, S5, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S16, S28, S31, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FCVT D9, S14	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FMADD S29, S28, S16, S26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FSQRT D7, D9	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1.75-3.75	scal (25.0%)
FMADD S27, S28, S29, S22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S15, S28, S27, S21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMUL D30, D9, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCVT D28, S15	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FDIV D14, D13, D30	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FADD D31, D14, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCVT S16, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (25.0%)
FMUL S10, S16, S10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
FMADD S24, S19, S10, S24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S23, S18, S10, S23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S25, S17, S10, S25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR S18, [X2, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
MOVI V9.2S, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
LDR S17, [X1, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
LDR S19, [X3, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
FSUB S29, S18, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FSUB S7, S17, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FSUB S27, S19, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMUL S15, S29, S29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
FMADD S14, S7, S7, S15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S28, S27, S27, S14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FCMPE S3, S28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
B.LS 410d1c <Step10_orig+0x31c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR S9, [X4, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
FCMPE S28, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
B.LS 410d68 <Step10_orig+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD S31, S4, S28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMADD S16, S28, S5, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S10, S28, S16, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FCVT D30, S31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FMADD S18, S28, S10, S26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FSQRT D17, D30	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1.75-3.75	scal (25.0%)
FMADD S19, S28, S18, S22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S15, S28, S19, S21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMUL D14, D30, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCVT D28, S15	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FDIV D31, D13, D14	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FADD D16, D31, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCVT S10, D16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (25.0%)
FMUL S9, S10, S9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
FMADD S24, S7, S9, S24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S23, S29, S9, S23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S25, S27, S9, S25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 410c64 <Step10_orig+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	Step10_orig
Source file and lines	Step10_orig.c:19-35
Module	exec

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.48 to 2.67 cycles (5.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.48 to 12.00 cycles (1.21x speedup).

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 60 FP arithmetical operations:

30: addition or subtraction (20 inside FMA instructions)
26: multiply (20 inside FMA instructions)
2: divide
2: square root

The binary loop is loading 24 bytes.

Arithmetic intensity

Arithmetic intensity is 2.50 FP operations per loaded or stored byte.

General properties

nb instructions	68
nb uops	68
loop length	272
used w registers	2
used x registers	5
used b registers	0
used h registers	0
used s registers	28
used d registers	9
used q registers	0
used v registers	2
used z registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	0.75	0.75	0.75	0.75	13.00	13.00	13.00	13.00	2.67	2.67	2.67	0.00	0.00
cycles	2.50	2.50	0.75	0.75	0.75	0.75	13.00	13.00	13.00	13.00	2.67	2.67	2.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

7.01-14.48

Cycles summary

Front-end	8.50
Dispatch	13.00
DIV/SQRT	7.01-14.48
Overall L1	13.00-14.48

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	15%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	16%
add-sub	15%
fma	12%
div/sqrt	25%
other	15%

INT+FP

all	14%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	16%
add-sub	15%
fma	12%
div/sqrt	25%
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.48 cycles. At this rate:

1% of peak load performance is reached (1.66 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410ce8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR S29, [X2, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
MOVI V10.2S, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
LDR S7, [X1, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
LDR S27, [X3, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
FSUB S18, S29, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FSUB S19, S7, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FSUB S17, S27, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMUL S30, S18, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
FMADD S15, S19, S19, S30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S28, S17, S17, S15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FCMPE S3, S28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
B.LS 410c98 <Step10_orig+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR S10, [X4, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
FCMPE S28, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
B.LS 410ce4 <Step10_orig+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD S14, S4, S28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMADD S31, S28, S5, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S16, S28, S31, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FCVT D9, S14	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FMADD S29, S28, S16, S26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FSQRT D7, D9	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1.75-3.75	scal (25.0%)
FMADD S27, S28, S29, S22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S15, S28, S27, S21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMUL D30, D9, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCVT D28, S15	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FDIV D14, D13, D30	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FADD D31, D14, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCVT S16, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (25.0%)
FMUL S10, S16, S10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
FMADD S24, S19, S10, S24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S23, S18, S10, S23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S25, S17, S10, S25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR S18, [X2, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
MOVI V9.2S, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
LDR S17, [X1, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
LDR S19, [X3, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
FSUB S29, S18, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FSUB S7, S17, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FSUB S27, S19, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMUL S15, S29, S29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
FMADD S14, S7, S7, S15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S28, S27, S27, S14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FCMPE S3, S28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
B.LS 410d1c <Step10_orig+0x31c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR S9, [X4, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
FCMPE S28, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
B.LS 410d68 <Step10_orig+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD S31, S4, S28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (12.5%)
FMADD S16, S28, S5, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S10, S28, S16, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FCVT D30, S31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FMADD S18, S28, S10, S26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FSQRT D17, D30	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1.75-3.75	scal (25.0%)
FMADD S19, S28, S18, S22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S15, S28, S19, S21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMUL D14, D30, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCVT D28, S15	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FDIV D31, D13, D14	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FADD D16, D31, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCVT S10, D16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (25.0%)
FMUL S9, S10, S9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
FMADD S24, S7, S9, S24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S23, S29, S9, S23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
FMADD S25, S27, S9, S25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (12.5%)
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 410c64 <Step10_orig+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code