OV - exec - Loop 4

	Loop Id: 4	Module: exec	Source: Step10_orig.c:19-31	Coverage: 97.67%

0x410aa0 LD1W	{Z26.S}, P7/Z, [X2, X8,LSL #2]    [3]

0x410aa4 LD1W	{Z27.S}, P7/Z, [X1, X8,LSL #2]    [2]

0x410aa8 FSUB	Z26.S, Z26.S, Z18.S

0x410aac FSUB	Z27.S, Z27.S, Z17.S

0x410ab0 LD1W	{Z28.S}, P7/Z, [X3, X8,LSL #2]    [4]

0x410ab4 FMUL	Z11.S, Z26.S, Z26.S

0x410ab8 FSUB	Z28.S, Z28.S, Z19.S

0x410abc FMLA	Z11.S, P7/M, Z27.S, Z27.S

0x410ac0 FMLA	Z11.S, P7/M, Z28.S, Z28.S

0x410ac4 FCMGT	P6.S, P7/Z, Z20.S, Z11.S

0x410ac8 FADD	Z10.S, Z11.S, Z21.S

0x410acc LD1W	{Z12.S}, P6/Z, [X4, X8,LSL #2]    [1]

0x410ad0 ZIP2	Z30.S, Z10.S, Z10.S

0x410ad4 ADD	X8, X8, #8

0x410ad8 FCVT	Z30.D, P7/M, Z30.S

0x410adc FCMGT	P0.S, P7/Z, Z11.S, #0.0000000

0x410ae0 MOVPRFX	Z29, Z14

0x410ae4 FMLA	Z29.S, P7/M, Z11.S, Z13.S

0x410ae8 MOVPRFX	Z31, Z30

0x410aec FSQRT	Z31.D, P7/M, Z30.D

0x410af0 FMAD	Z29.S, P7/M, Z11.S, Z15.S

0x410af4 FMUL	Z31.D, Z30.D, Z31.D

0x410af8 FMAD	Z29.S, P7/M, Z11.S, Z5.S

0x410afc ZIP1	Z10.S, Z10.S, Z10.S

0x410b00 FMAD	Z29.S, P7/M, Z11.S, Z6.S

0x410b04 FCVT	Z10.D, P7/M, Z10.S

0x410b08 FMAD	Z29.S, P7/M, Z11.S, Z7.S

0x410b0c SEL	Z12.S, P6, Z12.S, Z16.S

0x410b10 ZIP2	Z9.S, Z29.S, Z29.S

0x410b14 MOVPRFX	Z30, Z10

0x410b18 FSQRT	Z30.D, P7/M, Z10.D

0x410b1c ZIP1	Z29.S, Z29.S, Z29.S

0x410b20 FCVT	Z9.D, P7/M, Z9.S

0x410b24 FCVT	Z29.D, P7/M, Z29.S

0x410b28 FDIVR	Z31.D, P7/M, Z31.D, Z22.D

0x410b2c FMUL	Z10.D, Z10.D, Z30.D

0x410b30 FADD	Z9.D, Z31.D, Z9.D

0x410b34 FDIVR	Z10.D, P7/M, Z10.D, Z22.D

0x410b38 FCVT	Z9.S, P7/M, Z9.D

0x410b3c FADD	Z29.D, Z10.D, Z29.D

0x410b40 FCVT	Z29.S, P7/M, Z29.D

0x410b44 UZP1	Z11.S, Z9.S, Z29.S

0x410b48 FMUL	Z12.S, Z11.S, Z12.S

0x410b4c FMLA	Z23.S, P0/M, Z26.S, Z12.S

0x410b50 FMLA	Z24.S, P0/M, Z27.S, Z12.S

0x410b54 FMLA	Z25.S, P0/M, Z28.S, Z12.S

0x410b58 CMP	X16, X8

0x410b5c B.NE	410aa0

/home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 31

--------------------------------------------------------------------------------

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

Coverage (%)	Name	Source Location	Module
►98.44+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.56+	GOMP_parallel		libgomp.so.1.0.0
○	main	main.c:155	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	main.c:69	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.36 - 2.75
Bottlenecks	P6, P8,
Function	Step10_orig
Source	Step10_orig.c:19-31
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.97 - 56.34
CQA cycles if no scalar integer	27.97 - 56.34
CQA cycles if FP arith vectorized	27.97 - 56.34
CQA cycles if fully vectorized	27.97 - 56.34
Front-end cycles	6.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	20.50
P7 cycles	20.50
P8 cycles	10.00
P9 cycles	10.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	27.97 - 56.34
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	48.00
Nb uops	48.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.58 - 4.26
Nb FLOP add-sub	40.00
Nb FLOP mul	24.00
Nb FLOP fma	80.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.27 - 4.58
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	93.33
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	82.35
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.36 - 2.75
Bottlenecks	P6, P8,
Function	Step10_orig
Source	Step10_orig.c:19-31
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.97 - 56.34
CQA cycles if no scalar integer	27.97 - 56.34
CQA cycles if FP arith vectorized	27.97 - 56.34
CQA cycles if fully vectorized	27.97 - 56.34
Front-end cycles	6.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	20.50
P7 cycles	20.50
P8 cycles	10.00
P9 cycles	10.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	27.97 - 56.34
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	48.00
Nb uops	48.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.58 - 4.26
Nb FLOP add-sub	40.00
Nb FLOP mul	24.00
Nb FLOP fma	80.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.27 - 4.58
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	93.33
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	82.35
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	Step10_orig
Source file and lines	Step10_orig.c:19-31
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-31.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

93% of VPU instructions are used in vector version (process two or more data elements in vector registers):

82% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 56.34 to 18.50 cycles (3.05x speedup).

FMA

Detected 80 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 240 FP arithmetical operations:

120: addition or subtraction (80 inside FMA instructions)
104: multiply (80 inside FMA instructions)
8: divide
8: square root

The binary loop is loading 128 bytes.

Arithmetic intensity

Arithmetic intensity is 1.87 FP operations per loaded or stored byte.

General properties

nb instructions	48
nb uops	48
loop length	192
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	26
nb stack references	0
ADD-SUB / MUL ratio	1.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	20.50	20.50	0.00	0.00	2.00	2.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	20.50	20.50	10.00	10.00	2.00	2.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	27.97-56.34
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	6.00
Dispatch	20.50
DIV/SQRT	27.97-56.34
Data deps.	2.00
Overall L1	27.97-56.34

Vectorization ratios

INT

all	76%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	93%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	82%

Vector efficiency ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 56.34 cycles. At this rate:

2% of peak load performance is reached (2.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410aa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
LD1W {Z26.S}, P7/Z, [X2, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1W {Z27.S}, P7/Z, [X1, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z26.S, Z26.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FSUB Z27.S, Z27.S, Z17.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1W {Z28.S}, P7/Z, [X3, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z11.S, Z26.S, Z26.S	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FSUB Z28.S, Z28.S, Z19.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z11.S, P7/M, Z27.S, Z27.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z11.S, P7/M, Z28.S, Z28.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCMGT P6.S, P7/Z, Z20.S, Z11.S	1	0	0	0	0	0	0	1	0	0	0	2	1	vect (100.0%)
FADD Z10.S, Z11.S, Z21.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1W {Z12.S}, P6/Z, [X4, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ZIP2 Z30.S, Z10.S, Z10.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FCVT Z30.D, P7/M, Z30.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FCMGT P0.S, P7/Z, Z11.S, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	2	1	vect (100.0%)
MOVPRFX Z29, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z29.S, P7/M, Z11.S, Z13.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z31, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FSQRT Z31.D, P7/M, Z30.D	1	0	0	0	0	0	0	1	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMAD Z29.S, P7/M, Z11.S, Z15.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMUL Z31.D, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMAD Z29.S, P7/M, Z11.S, Z5.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
ZIP1 Z10.S, Z10.S, Z10.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMAD Z29.S, P7/M, Z11.S, Z6.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCVT Z10.D, P7/M, Z10.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FMAD Z29.S, P7/M, Z11.S, Z7.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
SEL Z12.S, P6, Z12.S, Z16.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
ZIP2 Z9.S, Z29.S, Z29.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOVPRFX Z30, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FSQRT Z30.D, P7/M, Z10.D	1	0	0	0	0	0	0	1	0	0	0	7-16	6.99-14.08	vect (100.0%)
ZIP1 Z29.S, Z29.S, Z29.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FCVT Z9.D, P7/M, Z9.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FCVT Z29.D, P7/M, Z29.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FDIVR Z31.D, P7/M, Z31.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z10.D, Z10.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z9.D, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FDIVR Z10.D, P7/M, Z10.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCVT Z9.S, P7/M, Z9.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FADD Z29.D, Z10.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FCVT Z29.S, P7/M, Z29.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
UZP1 Z11.S, Z9.S, Z29.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMUL Z12.S, Z11.S, Z12.S	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z23.S, P0/M, Z26.S, Z12.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z24.S, P0/M, Z27.S, Z12.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z25.S, P0/M, Z28.S, Z12.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
CMP X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
B.NE 410aa0 <Step10_orig+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	Step10_orig
Source file and lines	Step10_orig.c:19-31
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-31.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

93% of VPU instructions are used in vector version (process two or more data elements in vector registers):

82% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 56.34 to 18.50 cycles (3.05x speedup).

FMA

Detected 80 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 240 FP arithmetical operations:

120: addition or subtraction (80 inside FMA instructions)
104: multiply (80 inside FMA instructions)
8: divide
8: square root

The binary loop is loading 128 bytes.

Arithmetic intensity

Arithmetic intensity is 1.87 FP operations per loaded or stored byte.

General properties

nb instructions	48
nb uops	48
loop length	192
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	26
nb stack references	0
ADD-SUB / MUL ratio	1.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	20.50	20.50	0.00	0.00	2.00	2.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	20.50	20.50	10.00	10.00	2.00	2.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	27.97-56.34
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	6.00
Dispatch	20.50
DIV/SQRT	27.97-56.34
Data deps.	2.00
Overall L1	27.97-56.34

Vectorization ratios

INT

all	76%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	93%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	82%

Vector efficiency ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 56.34 cycles. At this rate:

2% of peak load performance is reached (2.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410aa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
LD1W {Z26.S}, P7/Z, [X2, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1W {Z27.S}, P7/Z, [X1, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z26.S, Z26.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FSUB Z27.S, Z27.S, Z17.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1W {Z28.S}, P7/Z, [X3, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z11.S, Z26.S, Z26.S	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FSUB Z28.S, Z28.S, Z19.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z11.S, P7/M, Z27.S, Z27.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z11.S, P7/M, Z28.S, Z28.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCMGT P6.S, P7/Z, Z20.S, Z11.S	1	0	0	0	0	0	0	1	0	0	0	2	1	vect (100.0%)
FADD Z10.S, Z11.S, Z21.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1W {Z12.S}, P6/Z, [X4, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ZIP2 Z30.S, Z10.S, Z10.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FCVT Z30.D, P7/M, Z30.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FCMGT P0.S, P7/Z, Z11.S, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	2	1	vect (100.0%)
MOVPRFX Z29, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z29.S, P7/M, Z11.S, Z13.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z31, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FSQRT Z31.D, P7/M, Z30.D	1	0	0	0	0	0	0	1	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMAD Z29.S, P7/M, Z11.S, Z15.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMUL Z31.D, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMAD Z29.S, P7/M, Z11.S, Z5.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
ZIP1 Z10.S, Z10.S, Z10.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMAD Z29.S, P7/M, Z11.S, Z6.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCVT Z10.D, P7/M, Z10.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FMAD Z29.S, P7/M, Z11.S, Z7.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
SEL Z12.S, P6, Z12.S, Z16.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
ZIP2 Z9.S, Z29.S, Z29.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOVPRFX Z30, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FSQRT Z30.D, P7/M, Z10.D	1	0	0	0	0	0	0	1	0	0	0	7-16	6.99-14.08	vect (100.0%)
ZIP1 Z29.S, Z29.S, Z29.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FCVT Z9.D, P7/M, Z9.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FCVT Z29.D, P7/M, Z29.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FDIVR Z31.D, P7/M, Z31.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z10.D, Z10.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z9.D, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FDIVR Z10.D, P7/M, Z10.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCVT Z9.S, P7/M, Z9.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FADD Z29.D, Z10.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FCVT Z29.S, P7/M, Z29.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
UZP1 Z11.S, Z9.S, Z29.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMUL Z12.S, Z11.S, Z12.S	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z23.S, P0/M, Z26.S, Z12.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z24.S, P0/M, Z27.S, Z12.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z25.S, P0/M, Z28.S, Z12.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
CMP X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
B.NE 410aa0 <Step10_orig+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code