OV - exec - Loop 17

0x411278 SBFM	X4, X14, #0, #31

0x41127c SBFM	X21, X14, #61, #31

0x411280 ORR	X3, XZR, XZR

0x411284 ORR	X24, XZR, X18

0x411288 ADD	X5, X17, X4

0x41128c ADD	X6, X10, X4

0x411290 ADD	X7, X16, X4

0x411294 UBFM	X20, X5, #61, #60

0x411298 UBFM	X23, X6, #61, #60

0x41129c ADD	X5, X13, X7,LSL #3

0x4112a0 ADD	X4, X0, X21

0x4112a4 ADD	X21, X2, X21

0x4112a8 ADD	X6, X12, X20

0x4112ac ADD	X7, X13, X20

0x4112b0 ADD	X20, X1, X23

0x4112b4 ADD	X23, X15, X23

  (16) 0x4112b8 ADD	X25, X20, X3

  (16) 0x4112bc LDR	D5, [X6, X3]

  (16) 0x4112c0 LDR	D6, [X4, X3]

  (16) 0x4112c4 LDP	D3, D2, [X25, #1016]

  (16) 0x4112c8 ADD	X25, X21, X3

  (16) 0x4112cc LDUR	D7, [X25, #504]

  (16) 0x4112d0 FADD	D16, D5, D6

  (16) 0x4112d4 LDR	D17, [X5, X3]

  (16) 0x4112d8 SUBS	X24, X24, #1

  (16) 0x4112dc FADD	D4, D2, D3

  (16) 0x4112e0 FMUL	D3, D3, D7

  (16) 0x4112e4 LDR	D7, [X25, #8]

  (16) 0x4112e8 FADD	D4, D4, D1

  (16) 0x4112ec FMADD	D2, D2, D7, D3

  (16) 0x4112f0 FMUL	D3, D6, D17

  (16) 0x4112f4 LDR	D6, [X25]

  (16) 0x4112f8 LDR	D7, [X7, X3]

  (16) 0x4112fc FADD	D4, D4, D16

  (16) 0x411300 FMADD	D3, D5, D7, D3

  (16) 0x411304 FNMSUB	D2, D4, D6, D2

  (16) 0x411308 FSUB	D2, D2, S3

  (16) 0x41130c STR	D2, [X23, X3]

  (16) 0x411310 ADD	X3, X3, #8

  (16) 0x411314 LDR	D3, [X25]

  (16) 0x411318 FMADD	D0, D2, D3, D0

  (16) 0x41131c STR	D0, [SP, #16]

  (16) 0x411320 B.NE	4112b8

0x411324 CMP	W9, W8

0x411328 ADD	W9, W9, #1

0x41132c ADD	W14, W14, W11

0x411330 B.NE	411278

/home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 85 - 90

--------------------------------------------------------------------------------

85:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

86:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

87:       const int index = kk + jj * x;

88:       const double smvp = tealeaf_SMVP(p);

89:       w[index] = smvp;

90:       pw_temp += w[index] * p[index];

Coverage (%)	Name	Source Location	Module
►98.40+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.60+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	run_cg_calc_w(Chunk*, Settings[...]	cg.cpp:94	exec
○	cg_main_step_driver(Chunk*, Se[...]	cg_driver.cpp:57	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:18	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:45	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:169	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.81
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.90
Bottlenecks	P2, P3, P4, P5,
Function	cg_calc_w(int, int, int, double, double const, double, double const, double const*) [clone .omp_outlined]
Source	cg.cpp:85-85
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.75
CQA cycles if no scalar integer	4.75
CQA cycles if FP arith vectorized	4.75
CQA cycles if fully vectorized	1.69
Front-end cycles	2.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	4.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	7.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	31.94
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.86
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	44.64

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.81
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.90
Bottlenecks	P2, P3, P4, P5,
Function	cg_calc_w(int, int, int, double, double const, double, double const, double const*) [clone .omp_outlined]
Source	cg.cpp:85-85
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.75
CQA cycles if no scalar integer	4.75
CQA cycles if FP arith vectorized	4.75
CQA cycles if fully vectorized	1.69
Front-end cycles	2.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	4.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	7.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	31.94
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.86
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	44.64

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	cg_calc_w(int, int, int, double, double const, double, double const, double const*) [clone .omp_outlined]
Source file and lines	cg.cpp:85-90
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:85-90.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:85.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 31% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.75 to 1.69 cycles (2.81x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	20
nb uops	20
loop length	80
used w registers	4
used x registers	21
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	0.50	0.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	2.50
Dispatch	4.75
Data deps.	2.00
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	31%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	44%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.75 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 411278

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput	Vectorization
SBFM X4, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (100.0%)
SBFM X21, X14, #61, #31	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (100.0%)
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ORR X24, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X5, X17, X4	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X6, X10, X4	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X7, X16, X4	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
UBFM X20, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
UBFM X23, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X5, X13, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X4, X0, X21	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X21, X2, X21	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X6, X12, X20	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X7, X13, X20	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X20, X1, X23	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X23, X15, X23	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
CMP W9, W8	1	0	0	0.25	0.25	0.25	0.25	1	0.33	scal (12.5%)
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
ADD W14, W14, W11	1	0	0	0.25	0.25	0.25	0.25	1	0.25	N/A
B.NE 411278 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x104>	1	0.50	0.50	0	0	0	0	1	0.50	N/A

Function	cg_calc_w(int, int, int, double, double const, double, double const, double const*) [clone .omp_outlined]
Source file and lines	cg.cpp:85-90
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:85-90.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:85.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 31% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.75 to 1.69 cycles (2.81x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	20
nb uops	20
loop length	80
used w registers	4
used x registers	21
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	0.50	0.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	2.50
Dispatch	4.75
Data deps.	2.00
Overall L1	4.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	31%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	44%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.75 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 411278

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput	Vectorization
SBFM X4, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (100.0%)
SBFM X21, X14, #61, #31	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (100.0%)
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ORR X24, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X5, X17, X4	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X6, X10, X4	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X7, X16, X4	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
UBFM X20, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
UBFM X23, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X5, X13, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X4, X0, X21	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X21, X2, X21	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X6, X12, X20	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X7, X13, X20	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X20, X1, X23	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X23, X15, X23	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
CMP W9, W8	1	0	0	0.25	0.25	0.25	0.25	1	0.33	scal (12.5%)
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
ADD W14, W14, W11	1	0	0	0.25	0.25	0.25	0.25	1	0.25	N/A
B.NE 411278 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x104>	1	0.50	0.50	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code