OV - exec - Loop 22

	Loop Id: 22	Module: exec	Source: cg.cpp:127-131	Coverage: 0.02%

0x41182c CMP	W9, W8

0x411830 ADD	W9, W9, #1

0x411834 ADD	W12, W12, #1

0x411838 ADD	W5, W5, W11

0x41183c B.EQ	411920

0x411840 SBFM	X5, X5, #0, #31

0x411844 CMP	X16, #4

0x411848 ORR	X21, XZR, X10

0x41184c B.CS	411884

0x411850 ADD	X6, X21, X5

0x411854 ADD	X21, X4, X21

0x411858 UBFM	X7, X6, #61, #60

0x41185c ADD	X6, X13, X7

0x411860 ADD	X7, X14, X7

  (21) 0x411864 LDR	D0, [X19]

  (21) 0x411868 LDR	D1, [X6]

  (21) 0x41186c ADDS	X21, X21, #1

  (21) 0x411870 LDR	D2, [X7], #8

  (21) 0x411874 FMADD	D0, D0, D1, D2

  (21) 0x411878 STR	D0, [X6], #8

  (21) 0x41187c B.CC	411864

0x411880 B	41182c

0x411884 ADD	W6, W15, W12

0x411888 MUL	W6, W11, W6

0x41188c SBFM	X6, X6, #0, #31

0x411890 ADD	X7, X11, X6

0x411894 ADD	X6, X10, X6

0x411898 UBFM	X7, X7, #61, #60

0x41189c UBFM	X6, X6, #61, #60

0x4118a0 ADD	X21, X0, X7

0x4118a4 ADD	X22, X13, X6

0x4118a8 ADD	X6, X14, X6

0x4118ac ADD	X7, X17, X7

0x4118b0 CMP	X22, X21

0x4118b4 ORR	X21, XZR, X10

0x4118b8 CCMP	X6, X7, #2, #3

0x4118bc CSINC	W6, WZR, WZR, #2

0x4118c0 CMP	X19, X7

0x4118c4 CCMP	X22, X18, #2, #3

0x4118c8 B.CC	411850

0x4118cc ORR	X21, XZR, X10

0x4118d0 TBNZ	W6, #0, 411850

0x4118d4 ADD	X6, X10, X5

0x4118d8 LDR	D0, [X19]

0x4118dc AND	X21, X16, #0x0

0x4118e0 UBFM	X7, X6, #61, #60

0x4118e4 ADD	X6, X2, X7

0x4118e8 ADD	X7, X3, X7

  (23) 0x4118ec LDP	Q1, Q4, [X7, #2032]

  (23) 0x4118f0 SUBS	X21, X21, #4

  (23) 0x4118f4 LDP	Q2, Q3, [X6, #2032]

  (23) 0x4118f8 ADD	X7, X7, #32

  (23) 0x4118fc FMLA	V1.2D, V2.2D, V0.D[0]

  (23) 0x411900 FMLA	V4.2D, V3.2D, V0.D[0]

  (23) 0x411904 STP	Q1, Q4, [X6, #2032]

  (23) 0x411908 ADD	X6, X6, #32

  (23) 0x41190c B.NE	4118ec

0x411910 CMP	X16, X1

0x411914 ADD	X21, X1, X10

0x411918 B.EQ	41182c

0x41191c B	411850

/home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 127 - 131

--------------------------------------------------------------------------------

127:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

128:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

129:       const int index = kk + jj * x;

130:

131:       p[index] = beta * p[index] + r[index];

Coverage (%)	Name	Source Location	Module
►98.68+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.32+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	run_cg_calc_p(Chunk*, Settings[...]	cg.cpp:160	exec
○	cg_main_step_driver(Chunk*, Se[...]	cg_driver.cpp:83	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:18	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:45	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:169	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	5.29
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.45
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.64
Bottlenecks	P2, P3, P4, P5,
Function	cg_calc_p(int, int, int, double, double, double const) [clone .omp_outlined]
Source	cg.cpp:127-128,cg.cpp:131-131
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.25
CQA cycles if no scalar integer	1.75
CQA cycles if FP arith vectorized	9.25
CQA cycles if fully vectorized	3.78
Front-end cycles	5.63
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	9.25
P3 cycles	9.25
P4 cycles	9.25
P5 cycles	9.25
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.33
P11 cycles	0.33
P12 cycles	0.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	45.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	27.02
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	21.67
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	33.93

Metric	Value
CQA speedup if no scalar integer	5.29
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.45
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.64
Bottlenecks	P2, P3, P4, P5,
Function	cg_calc_p(int, int, int, double, double, double const) [clone .omp_outlined]
Source	cg.cpp:127-128,cg.cpp:131-131
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.25
CQA cycles if no scalar integer	1.75
CQA cycles if FP arith vectorized	9.25
CQA cycles if fully vectorized	3.78
Front-end cycles	5.63
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	9.25
P3 cycles	9.25
P4 cycles	9.25
P5 cycles	9.25
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.33
P11 cycles	0.33
P12 cycles	0.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	45.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	27.02
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	21.67
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	33.93

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	cg_calc_p(int, int, int, double, double, double const) [clone .omp_outlined]
Source file and lines	cg.cpp:127-131
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:127-131.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:127-128,131.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.25 to 1.75 cycles (5.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.25 to 3.78 cycles (2.45x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	45
nb uops	45
loop length	180
used w registers	8
used x registers	19
used b registers	0
used h registers	0
used s registers	0
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.63 cycles
front end	5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00
cycles	3.50	3.50	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.63
Dispatch	9.25
Overall L1	9.25

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	27%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.25 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 411840

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
CMP W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (12.5%)
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ADD W5, W5, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
B.EQ 411920 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X5, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (100.0%)
CMP X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
ORR X21, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
B.CS 411884 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X21, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X21, X4, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
UBFM X7, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X6, X13, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X7, X14, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
B 41182c <_Z9cg_calc_piiidPdPKd.omp_outlined+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ADD W6, W15, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
MUL W6, W11, W6	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
SBFM X6, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (100.0%)
ADD X7, X11, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X6, X10, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
UBFM X7, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
UBFM X6, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X21, X0, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X22, X13, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X6, X14, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X7, X17, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMP X22, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
ORR X21, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
CCMP X6, X7, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CSINC W6, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
CMP X19, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
CCMP X22, X18, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
B.CC 411850 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
TBNZ W6, #0, 411850 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X10, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
LDR D0, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
AND X21, X16, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
UBFM X7, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X6, X2, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X7, X3, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMP X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
ADD X21, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
B.EQ 41182c <_Z9cg_calc_piiidPdPKd.omp_outlined+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
B 411850 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Function	cg_calc_p(int, int, int, double, double, double const) [clone .omp_outlined]
Source file and lines	cg.cpp:127-131
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.25 to 1.75 cycles (5.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	45
nb uops	45
loop length	180
used w registers	8
used x registers	19
used b registers	0
used h registers	0
used s registers	0
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.63 cycles
front end	5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00
cycles	3.50	3.50	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.63
Dispatch	9.25
Overall L1	9.25

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	27%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.25 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 411840

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
CMP W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (12.5%)
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ADD W5, W5, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
B.EQ 411920 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X5, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (100.0%)
CMP X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
ORR X21, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
B.CS 411884 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X21, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X21, X4, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
UBFM X7, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X6, X13, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X7, X14, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
B 41182c <_Z9cg_calc_piiidPdPKd.omp_outlined+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ADD W6, W15, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
MUL W6, W11, W6	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
SBFM X6, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (100.0%)
ADD X7, X11, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X6, X10, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
UBFM X7, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
UBFM X6, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X21, X0, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X22, X13, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X6, X14, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X7, X17, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMP X22, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
ORR X21, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
CCMP X6, X7, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CSINC W6, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
CMP X19, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
CCMP X22, X18, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
B.CC 411850 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
TBNZ W6, #0, 411850 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X10, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
LDR D0, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
AND X21, X16, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
UBFM X7, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X6, X2, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X7, X3, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMP X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
ADD X21, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
B.EQ 41182c <_Z9cg_calc_piiidPdPKd.omp_outlined+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
B 411850 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code