OV - exec - Function cg_init(int, int, int, int, double, double, double*, double const*, double const*, double*, double*, double*, double*, double*, double*) [clone ._omp

	Function: cg_init(int, int, int, int, double, double, double, double const, double const, double ...	Module: exec	Source: cg.cpp:59-68	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 59 - 68

--------------------------------------------------------------------------------

59:   #pragma omp parallel for reduction(+ : rro_temp)

60: #endif

61:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

62:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

63:       const int index = kk + jj * x;

64:       const double smvp = tealeaf_SMVP(u);

65:       w[index] = smvp;

66:       r[index] = u[index] - w[index];

67:       p[index] = r[index];

68:       rro_temp += r[index] * p[index];

0x411100 STP	X29, X30, [SP, #976]!

0x411104 ADD	X29, SP, #0

0x411108 STP	X19, X20, [SP, #16]

0x41110c ORR	X19, XZR, X0

0x411110 LDR	W20, [X0, #64]

0x411114 STR	X21, [SP, #32]

0x411118 BL	410320

0x41111c ORR	W21, WZR, W0

0x411120 BL	4102b0

0x411124 LDR	W1, [X19, #60]

0x411128 ORR	W15, WZR, W0

0x41112c SUB	W0, W1, W20,LSL #1

0x411130 SDIV	W1, W0, W21

0x411134 MSUB	W0, W1, W21, W0

0x411138 CMP	W15, W0

0x41113c B.LT	411274

0x411140 MADD	W15, W1, W15, W0

0x411144 MOVI	D26, #0

0x411148 ADD	W1, W1, W15

0x41114c CMP	W15, W1

0x411150 B.GE	411240

0x411154 LDR	W17, [X19, #56]

0x411158 ADD	W15, W20, W15

0x41115c FMOV	D20, #1.0000000

0x411160 LDP	X2, X13, [X19]

0x411164 SBFM	X30, X20, #0, #31

0x411168 ADD	W0, W20, W1

0x41116c LDP	X6, X5, [X19, #32]

0x411170 SUB	W18, W17, W20,LSL #1

0x411174 SBFM	X4, X17, #61, #31

0x411178 SUB	W21, W17, W20

0x41117c MUL	W16, W15, W17

0x411180 ADD	X14, X2, X4

0x411184 SUB	X12, X2, X4

0x411188 LDP	X8, X7, [X19, #16]

0x41118c ADD	X18, X18, X30

0x411190 ADD	X11, X2, #8

0x411194 SUB	X10, X2, #8

0x411198 ADD	X9, X6, #8

0x41119c ADD	X4, X5, X4

(16) 0x4111a0 CMP	W20, W21

(16) 0x4111a4 B.GE	411230

(16) 0x4111a8 SBFM	X3, X16, #0, #31

(16) 0x4111ac ADD	X1, X3, X30

(16) 0x4111b0 ADD	X3, X18, X3

(16) 0x4111b4 UBFM	X1, X1, #61, #60

(16) 0x4111b8 UBFM	X3, X3, #61, #60

(16) 0x4111bc HINT	#0

  (17) 0x4111c0 LDR	D27, [X9, X1]

  (17) 0x4111c4 LDR	D31, [X6, X1]

  (17) 0x4111c8 LDR	D28, [X4, X1]

  (17) 0x4111cc LDR	D30, [X5, X1]

  (17) 0x4111d0 FADD	D29, D27, D31

  (17) 0x4111d4 LDR	D25, [X10, X1]

  (17) 0x4111d8 LDR	D22, [X11, X1]

  (17) 0x4111dc FADD	D23, D28, D30

  (17) 0x4111e0 LDR	D21, [X12, X1]

  (17) 0x4111e4 FADD	D29, D29, D20

  (17) 0x4111e8 FMUL	D31, D31, D25

  (17) 0x4111ec LDR	D24, [X14, X1]

  (17) 0x4111f0 LDR	D25, [X2, X1]

  (17) 0x4111f4 FMUL	D30, D30, D21

  (17) 0x4111f8 FMADD	D31, D27, D22, D31

  (17) 0x4111fc FADD	D29, D29, D23

  (17) 0x411200 FMADD	D30, D28, D24, D30

  (17) 0x411204 FNMSUB	D31, D29, D25, D31

  (17) 0x411208 FSUB	D31, D31, S30

  (17) 0x41120c STR	D31, [X7, X1]

  (17) 0x411210 LDR	D30, [X2, X1]

  (17) 0x411214 FSUB	D31, D30, S31

  (17) 0x411218 STR	D31, [X8, X1]

  (17) 0x41121c FMADD	D26, D31, D31, D26

  (17) 0x411220 STR	D31, [X13, X1]

  (17) 0x411224 ADD	X1, X1, #8

  (17) 0x411228 CMP	X3, X1

  (17) 0x41122c B.NE	4111c0

(16) 0x411230 ADD	W15, W15, #1

(16) 0x411234 ADD	W16, W16, W17

(16) 0x411238 CMP	W0, W15

(16) 0x41123c B.GT	4111a0

0x411240 ADD	X19, X19, #48

0x411244 LDR	X0, [X19]

(15) 0x411248 FMOV	D31, X0

(15) 0x41124c ORR	X1, XZR, X0

(15) 0x411250 FADD	D31, D26, D31

(15) 0x411254 FMOV	X2, D31

(15) 0x411258 CAS	X1, X2, [X19]

(15) 0x41125c CMP	X0, X1

(15) 0x411260 B.NE	411280

0x411264 LDR	X21, [SP, #32]

0x411268 LDP	X19, X20, [SP, #16]

0x41126c LDP	X29, X30, [SP], #48

0x411270 RET

0x411274 ADD	W1, W1, #1

0x411278 MOVZ	W0, #0

0x41127c B	411140

(15) 0x411280 ORR	X0, XZR, X1

(15) 0x411284 B	411248

Coverage (%)	Name	Source Location	Module
►97.92+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.85+	GOMP_parallel		libgomp.so.1.0.0
○	run_cg_init(Chunk*, Settings&,[...]	cg.cpp:73	exec
○	cg_init_driver(Chunk*, Setting[...]	cg_driver.cpp:30	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:15	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:51	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:179	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	cg.cpp:59-68
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:59-68.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 30% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 7.50 cycles (1.67x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:59
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:59

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 9 bytes.

General properties

nb instructions	49
nb uops	49
loop length	196
used w registers	9
used x registers	21
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.13 cycles
front end	6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	7.75	7.75	7.75	7.75	0.50	0.50	0.50	0.50	4.50	4.17	4.33	1.50	1.50
cycles	3.00	3.00	7.75	7.75	7.75	7.75	0.50	0.50	0.50	0.50	4.50	4.17	4.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	6.13
Dispatch	7.75
DIV/SQRT	5.00-12.50
Overall L1	7.75-12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	30%
load	35%
store	41%
mul	12%
add-sub	21%
fma	12%
other	39%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	30%
load	35%
store	41%
mul	12%
add-sub	21%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.72 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 411100

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W20, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410320 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4102b0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X19, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W15, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W0, W1, W20,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W1, W0, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W0, W1, W21, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W15, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 411274 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_._omp_fn.3+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W15, W1, W15, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOVI D26, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD W1, W1, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W15, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 411240 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_._omp_fn.3+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W17, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W15, W20, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
FMOV D20, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDP X2, X13, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
SBFM X30, X20, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W0, W20, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X6, X5, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
SUB W18, W17, W20,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X4, X17, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SUB W21, W17, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W16, W15, W17	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
ADD X14, X2, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X12, X2, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X8, X7, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X18, X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X10, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X5, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X19, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 411140 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_._omp_fn.3+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	cg.cpp:59-68
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:59-68.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 30% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 7.50 cycles (1.67x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:59
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:59

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 9 bytes.

General properties

nb instructions	49
nb uops	49
loop length	196
used w registers	9
used x registers	21
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.13 cycles
front end	6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	7.75	7.75	7.75	7.75	0.50	0.50	0.50	0.50	4.50	4.17	4.33	1.50	1.50
cycles	3.00	3.00	7.75	7.75	7.75	7.75	0.50	0.50	0.50	0.50	4.50	4.17	4.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	6.13
Dispatch	7.75
DIV/SQRT	5.00-12.50
Overall L1	7.75-12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	30%
load	35%
store	41%
mul	12%
add-sub	21%
fma	12%
other	39%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	30%
load	35%
store	41%
mul	12%
add-sub	21%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.72 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 411100

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W20, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410320 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4102b0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X19, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W15, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W0, W1, W20,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W1, W0, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W0, W1, W21, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W15, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 411274 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_._omp_fn.3+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W15, W1, W15, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOVI D26, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD W1, W1, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W15, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 411240 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_._omp_fn.3+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W17, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W15, W20, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
FMOV D20, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDP X2, X13, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
SBFM X30, X20, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W0, W20, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X6, X5, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
SUB W18, W17, W20,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X4, X17, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SUB W21, W17, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W16, W15, W17	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
ADD X14, X2, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X12, X2, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X8, X7, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X18, X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X10, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X5, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X19, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 411140 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_._omp_fn.3+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼cg_init(int, int, int, int, double, double, double, double const, double const, double, double, double, double, double, double*) [clone ._omp_fn.3]–	0.01	0.03
○Loop 15 - cg.cpp:59-59 - exec	0.00	0.00
▼Loop 16 - cg.cpp:62-68 - exec–	0.00	0.00
○Loop 17 - cg.cpp:62-68 - exec	0.01	0.04

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code