OV - exec - Loop 22

	Loop Id: 22	Module: exec	Source: cg.cpp:83-90	Coverage: 0.11%

0x411380 SBFM	X1, X30, #0, #31

0x411384 ADD	X3, X1, X27

0x411388 UBFM	X2, X3, #61, #60

0x41138c ADD	X9, X18, X3,LSL #3

0x411390 SUB	X4, X3, X22

0x411394 ADD	X12, X2, #24

0x411398 ADD	X4, X4, #1

0x41139c ADD	X12, X6, X12

0x4113a0 SUB	X21, X2, #8

0x4113a4 ADD	X24, X6, X4,LSL #3

0x4113a8 ADD	X23, X2, #16

0x4113ac CMP	X12, X9

0x4113b0 ADD	X23, X18, X23

0x4113b4 ADD	X12, X2, #8

0x4113b8 ADD	X21, X6, X21

0x4113bc ADD	X3, X22, X3

0x4113c0 ADD	X3, X3, #1

0x4113c4 CCMP	X21, X23, #2, #8

0x4113c8 ADD	X23, X17, X12

0x4113cc ADD	X26, X6, X3,LSL #3

0x4113d0 CCMP	X24, X9, #4, #2

0x4113d4 SUB	X24, X9, X23

0x4113d8 ADD	X25, X15, X3,LSL #3

0x4113dc UBFM	X4, X4, #61, #60

0x4113e0 CCMP	X24, #8, #0, #1

0x4113e4 UBFM	X3, X3, #61, #60

0x4113e8 CSINC	W24, WZR, WZR, #9

0x4113ec CMP	X26, X9

0x4113f0 ADD	X26, X15, X12

0x4113f4 CCMP	X25, X9, #4, #1

0x4113f8 CCMP	X26, X9, #4, #1

0x4113fc CSINC	W25, WZR, WZR, #0

0x411400 ANDS	WZR, W24, W25

0x411404 B.EQ	411578

0x411408 SUB	X3, X3, #8

0x41140c SUB	X4, X4, #8

0x411410 ADD	X26, X15, X3

0x411414 ADD	X25, X17, X2

0x411418 ADD	X24, X15, X2

0x41141c MOVZ	X1, #0

0x411420 ADD	X4, X6, X4

0x411424 ADD	X12, X6, X12

0x411428 ADD	X3, X6, X3

0x41142c ADD	X2, X6, X2

  (21) 0x411430 LDR	Q25, [X23, X1]

  (21) 0x411434 LDR	Q29, [X25, X1]

  (21) 0x411438 LDR	Q31, [X21, X1]

  (21) 0x41143c LDR	Q23, [X12, X1]

  (21) 0x411440 LDR	Q27, [X26, X1]

  (21) 0x411444 FADD	V28.2D, V25.2D, V29.2D

  (21) 0x411448 LDR	Q26, [X24, X1]

  (21) 0x41144c FMUL	V31.2D, V31.2D, V29.2D

  (21) 0x411450 LDR	Q29, [X4, X1]

  (21) 0x411454 FADD	V28.2D, V28.2D, V22.2D

  (21) 0x411458 LDR	Q24, [X2, X1]

  (21) 0x41145c FMLA	V31.2D, V25.2D, V23.2D

  (21) 0x411460 LDR	Q25, [X3, X1]

  (21) 0x411464 FADD	V23.2D, V27.2D, V26.2D

  (21) 0x411468 FMUL	V29.2D, V29.2D, V26.2D

  (21) 0x41146c FADD	V28.2D, V28.2D, V23.2D

  (21) 0x411470 FNEG	V31.2D, V31.2D

  (21) 0x411474 FMLA	V29.2D, V27.2D, V25.2D

  (21) 0x411478 FMLA	V31.2D, V28.2D, V24.2D

  (21) 0x41147c FSUB	V31.2D, V31.2D, V29.2D

  (21) 0x411480 STR	Q31, [X9, X1]

  (21) 0x411484 LDR	Q29, [X2, X1]

  (21) 0x411488 ADD	X1, X1, #16

  (21) 0x41148c FMUL	V31.2D, V29.2D, V31.2D

  (21) 0x411490 FADD	D30, D30, D31

  (21) 0x411494 MOV	D29, V31.D[1]

  (21) 0x411498 FADD	D30, D29, D30

  (21) 0x41149c CMP	X1, X14

  (21) 0x4114a0 B.NE	411430

0x4114a4 CBZ	W28, 411528

0x4114a8 LDR	W1, [SP, #96]

0x4114ac ADD	W2, W1, W30

0x4114b0 SBFM	X1, X2, #0, #31

0x4114b4 ADD	W4, W0, W2

0x4114b8 ADD	X1, X1, #1

0x4114bc SUB	W3, W2, W0

0x4114c0 UBFM	X1, X1, #61, #60

0x4114c4 SBFM	X4, X4, #61, #31

0x4114c8 SUB	X2, X1, #8

0x4114cc ADD	X9, X6, X1

0x4114d0 LDR	D19, [X6, W3,SXTW #3]

0x4114d4 LDR	D31, [X17, X2]

0x4114d8 LDR	D26, [X17, X1]

0x4114dc LDR	D27, [X15, X4]

0x4114e0 LDR	D29, [X15, X2]

0x4114e4 FADD	D28, D26, D31

0x4114e8 LDUR	D25, [X9, #496]

0x4114ec LDR	D20, [X6, X1]

0x4114f0 FADD	D23, D27, D29

0x4114f4 LDR	D24, [X6, X4]

0x4114f8 FMUL	D29, D29, D19

0x4114fc FADD	D28, D28, D22

0x411500 FMUL	D31, D31, D25

0x411504 LDR	D25, [X6, X2]

0x411508 FMADD	D29, D27, D24, D29

0x41150c FMADD	D31, D26, D20, D31

0x411510 FADD	D28, D28, D23

0x411514 FNMSUB	D31, D28, D25, D31

0x411518 FSUB	D31, D31, S29

0x41151c STR	D31, [X18, X2]

0x411520 LDR	D29, [X6, X2]

0x411524 FMADD	D30, D31, D29, D30

0x411528 ADD	W16, W16, #1

0x41152c ADD	W30, W30, W0

0x411530 CMP	W20, W16

0x411534 B.GT	411380

/home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 83 - 90

--------------------------------------------------------------------------------

83:   #pragma omp parallel for reduction(+ : pw_temp)

84: #endif

85:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

86:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

87:       const int index = kk + jj * x;

88:       const double smvp = tealeaf_SMVP(p);

89:       w[index] = smvp;

90:       pw_temp += w[index] * p[index];

Coverage (%)	Name	Source Location	Module
►98.22+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.78+	GOMP_parallel		libgomp.so.1.0.0
○	run_cg_calc_w(Chunk*, Settings[...]	cg.cpp:83	exec
○	cg_main_step_driver(Chunk*, Se[...]	cg_driver.cpp:57	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:18	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:51	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:179	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.29
CQA speedup if FP arith vectorized	1.25
CQA speedup if fully vectorized	4.23
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.55
Bottlenecks
Function	cg_calc_w(int, int, int, double, double const, double, double const, double const*) [clone ._omp_fn.0]
Source	cg.cpp:83-83,cg.cpp:86-90
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.63
CQA cycles if no scalar integer	9.75
CQA cycles if FP arith vectorized	10.09
CQA cycles if fully vectorized	2.98
Front-end cycles	8.13
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	12.63
P3 cycles	12.63
P4 cycles	12.63
P5 cycles	12.63
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	2.08
P11 cycles	1.92
P12 cycles	2.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	65.00
Nb uops	65.00
Nb loads	NA
Nb stores	0.50
Nb stack references	0.50
FLOP/cycle	0.59
Nb FLOP add-sub	2.50
Nb FLOP mul	1.00
Nb FLOP fma	2.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.11
Bytes prefetched	0.00
Bytes loaded	1.50
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	10.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.78
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	24.51
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	24.38

Metric	Value
CQA speedup if no scalar integer	1.72
CQA speedup if FP arith vectorized	1.58
CQA speedup if fully vectorized	5.57
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.36
Bottlenecks	P2, P3, P4, P5,
Function	cg_calc_w(int, int, int, double, double const, double, double const, double const*) [clone ._omp_fn.0]
Source	cg.cpp:83-83,cg.cpp:86-90
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.75
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.69
CQA cycles if fully vectorized	2.47
Front-end cycles	10.13
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	13.75
P3 cycles	13.75
P4 cycles	13.75
P5 cycles	13.75
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	4.17
P11 cycles	3.83
P12 cycles	4.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	81.00
Nb uops	81.00
Nb loads	NA
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	1.09
Nb FLOP add-sub	5.00
Nb FLOP mul	2.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.22
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	10.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	24.46
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.29
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.88
Bottlenecks	P2, P3, P4, P5,
Function	cg_calc_w(int, int, int, double, double const, double, double const, double const*) [clone ._omp_fn.0]
Source	cg.cpp:83-83,cg.cpp:86-90
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.50
CQA cycles if no scalar integer	11.50
CQA cycles if FP arith vectorized	11.50
CQA cycles if fully vectorized	3.50
Front-end cycles	6.13
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	11.50
P3 cycles	11.50
P4 cycles	11.50
P5 cycles	11.50
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	49.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	10.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.57
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.57
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	27.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	cg_calc_w(int, int, int, double, double const, double, double const, double const*) [clone ._omp_fn.0]
Source file and lines	cg.cpp:83-90
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83-90.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83,86-90.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.63 to 2.98 cycles (4.23x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 10 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 7.5 FP arithmetical operations:

4.50: addition or subtraction (2 inside FMA instructions)
3: multiply (2 inside FMA instructions)

The binary loop is loading 1 bytes.

Arithmetic intensity

Arithmetic intensity is 5.00 FP operations per loaded or stored byte.

General properties

nb instructions	65
nb uops	65
loop length	260
used w registers	10
used x registers	18
used b registers	0
used h registers	0
used s registers	1
used d registers	6
used q registers	0
used v registers	0
used z registers	0
nb stack references	0.50
ADD-SUB / MUL ratio	2.50

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	8.13 cycles
front end	8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	12.63	12.63	12.63	12.63	1.50	1.50	1.50	1.50	2.08	1.92	2.00	0.00	0.00
cycles	1.50	1.50	12.63	12.63	12.63	12.63	1.50	1.50	1.50	1.50	2.08	1.92	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	8.13
Dispatch	12.63
Data deps.	8.00
Overall L1	12.63

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	24%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	24%
fma	NA (no fma vectorizable/vectorized instructions)
other	24%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	24%
load	25%
store	25%
mul	25%
add-sub	24%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.63 cycles. At this rate:

0% of peak load performance is reached (0.11 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	cg_calc_w(int, int, int, double, double const, double, double const, double const*) [clone ._omp_fn.0]
Source file and lines	cg.cpp:83-90
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.75 to 8.00 cycles (1.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 10 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 15 FP arithmetical operations:

9: addition or subtraction (4 inside FMA instructions)
6: multiply (4 inside FMA instructions)

The binary loop is loading 3 bytes.

Arithmetic intensity

Arithmetic intensity is 5.00 FP operations per loaded or stored byte.

General properties

nb instructions	81
nb uops	81
loop length	324
used w registers	12
used x registers	18
used b registers	0
used h registers	0
used s registers	2
used d registers	12
used q registers	0
used v registers	0
used z registers	0
nb stack references	1
ADD-SUB / MUL ratio	2.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.13 cycles
front end	10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	13.75	13.75	13.75	13.75	3.00	3.00	3.00	3.00	4.17	3.83	4.00	0.00	0.00
cycles	1.50	1.50	13.75	13.75	13.75	13.75	3.00	3.00	3.00	3.00	4.17	3.83	4.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	10.13
Dispatch	13.75
Data deps.	8.00
Overall L1	13.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	23%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	24%
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	24%
load	25%
store	25%
mul	25%
add-sub	24%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.75 cycles. At this rate:

0% of peak load performance is reached (0.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 411380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SBFM X1, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X1, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X2, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X18, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X3, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X2, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X6, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X21, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X24, X6, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X23, X2, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X23, X18, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X21, X6, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X22, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CCMP X21, X23, #2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X23, X17, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X26, X6, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP X24, X9, #4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X24, X9, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X25, X15, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X4, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CCMP X24, #8, #0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X3, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CSINC W24, WZR, WZR, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X26, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X26, X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP X25, X9, #4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP X26, X9, #4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W25, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ANDS WZR, W24, W25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
B.EQ 411578 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X26, X15, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X25, X17, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X24, X15, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X6, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X6, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X6, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CBZ W28, 411528 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD W2, W1, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X1, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W4, W0, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB W3, W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X1, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X4, X4, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X2, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X6, W3,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D31, [X17, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D26, [X17, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D27, [X15, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D29, [X15, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D28, D26, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDUR D25, [X9, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D20, [X6, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D23, D27, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D24, [X6, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D29, D29, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FADD D28, D28, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D31, D31, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
LDR D25, [X6, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D29, D27, D24, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMADD D31, D26, D20, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FADD D28, D28, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FNMSUB D31, D28, D25, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FSUB D31, D31, S29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D31, [X18, X2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D29, [X6, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D30, D31, D29, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
ADD W16, W16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W30, W30, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W20, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 411380 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	cg_calc_w(int, int, int, double, double const, double, double const, double const*) [clone ._omp_fn.0]
Source file and lines	cg.cpp:83-90
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.50 to 3.50 cycles (3.29x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 10 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	49
nb uops	49
loop length	196
used w registers	8
used x registers	18
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.13 cycles
front end	6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	11.50	11.50	11.50	11.50	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.50	1.50	11.50	11.50	11.50	11.50	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	6.13
Dispatch	11.50
Data deps.	8.00
Overall L1	11.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	24%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 411380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput	Vectorization
SBFM X1, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (100.0%)
ADD X3, X1, X27	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
UBFM X2, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X9, X18, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
SUB X4, X3, X22	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X12, X2, #24	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X12, X6, X12	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
SUB X21, X2, #8	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X24, X6, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X23, X2, #16	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
CMP X12, X9	1	0	0	0.25	0.25	0.25	0.25	1	0.33	scal (25.0%)
ADD X23, X18, X23	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X12, X2, #8	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X21, X6, X21	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X3, X22, X3	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
CCMP X21, X23, #2, #8	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X23, X17, X12	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X26, X6, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
CCMP X24, X9, #4, #2	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
SUB X24, X9, X23	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X25, X15, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
UBFM X4, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
CCMP X24, #8, #0, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
UBFM X3, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
CSINC W24, WZR, WZR, #9	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
CMP X26, X9	1	0	0	0.25	0.25	0.25	0.25	1	0.33	scal (25.0%)
ADD X26, X15, X12	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
CCMP X25, X9, #4, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
CCMP X26, X9, #4, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
CSINC W25, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
ANDS WZR, W24, W25	1	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
B.EQ 411578 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	1	0.50	N/A
SUB X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
SUB X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X26, X15, X3	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X25, X17, X2	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X24, X15, X2	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X4, X6, X4	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X12, X6, X12	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X3, X6, X3	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
ADD X2, X6, X2	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (25.0%)
CBZ W28, 411528 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x2a0>	1	0.50	0.50	0	0	0	0	1	0.50	N/A
ADD W16, W16, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25	N/A
ADD W30, W30, W0	1	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
CMP W20, W16	1	0	0	0.25	0.25	0.25	0.25	1	0.33	N/A
B.GT 411380 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0xf8>	1	0.50	0.50	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code