OV - exec - Function cg_calc_w(int, int, int, double*, double const*, double*, double const*, double const*) [clone .omp

	Function: cg_calc_w(int, int, int, double, double const, double, double const, double const*) [c ...	Module: exec	Source: cg.cpp:83-90	Coverage (incl. loops): 33.00% \| (excl. loops): 0.01%

/home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 83 - 90

--------------------------------------------------------------------------------

83:   #pragma omp parallel for reduction(+ : pw_temp)

84: #endif

85:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

86:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

87:       const int index = kk + jj * x;

88:       const double smvp = tealeaf_SMVP(p);

89:       w[index] = smvp;

90:       pw_temp += w[index] * p[index];

0x411a30 SUB	SP, SP, #384

0x411a34 STP	X29, X30, [SP, #288]

0x411a38 STP	X28, X27, [SP, #304]

0x411a3c STP	X26, X25, [SP, #320]

0x411a40 STP	X24, X23, [SP, #336]

0x411a44 STP	X22, X21, [SP, #352]

0x411a48 STP	X20, X19, [SP, #368]

0x411a4c ADD	X29, SP, #288

0x411a50 LDR	W23, [X3]

0x411a54 LDR	W8, [X2]

0x411a58 SUB	W8, W8, W23

0x411a5c CMP	W23, W8

0x411a60 B.GE	412104

0x411a64 LDR	X9, [X29, #104]

0x411a68 LDR	W1, [X0]

0x411a6c ORR	X20, XZR, X4

0x411a70 ORR	X21, XZR, X3

0x411a74 ORR	X24, XZR, X5

0x411a78 ORR	X22, XZR, X6

0x411a7c ORR	X19, XZR, X7

0x411a80 ADRP	X0,

0x411a84 ADD	X0, X0, #1048

0x411a88 SUB	X3, X29, #24

0x411a8c SUB	X4, X29, #12

0x411a90 SUB	X5, X29, #16

0x411a94 SUB	X6, X29, #20

0x411a98 MOVZ	W2, #34

0x411a9c MOVZ	W7, #1

0x411aa0 STUR	XZR, [X29, #480]

0x411aa4 STR	X9, [SP, #16]

0x411aa8 ORN	W9, WZR, W23

0x411aac STR	W1, [SP, #12]

0x411ab0 ADD	W25, W8, W9

0x411ab4 MOVZ	W8, #1

0x411ab8 STP	W25, WZR, [X29, #496]

0x411abc STP	WZR, W8, [X29, #488]

0x411ac0 STR	W8, [SP]

0x411ac4 BL	4100a0

0x411ac8 LDP	W8, W10, [X29, #496]

0x411acc CMP	W8, W25

0x411ad0 CSEL	W15, W8, W25, #3

0x411ad4 ADD	W8, W15, #1

0x411ad8 STUR	W15, [X29, #496]

0x411adc CMP	W10, W8

0x411ae0 B.CS	412050

0x411ae4 LDRSW	X4, [X21]

0x411ae8 LDRSW	X5, [X20]

0x411aec SUB	W8, W5, W4

0x411af0 CMP	W4, W8

0x411af4 B.GE	412050

0x411af8 LDR	X8, [X29, #96]

0x411afc LDR	X11, [X24]

0x411b00 LDR	X18, [X22]

0x411b04 SUB	X16, X29, #32

0x411b08 MOVZ	W13, #8

0x411b0c SUB	X0, XZR, X5

0x411b10 ADD	W9, W10, W23

0x411b14 ADD	X14, X4, X5

0x411b18 LDR	X2, [X19]

0x411b1c STUR	X0, [X29, #432]

0x411b20 SUB	X0, X13, X4,LSL #3

0x411b24 STUR	X14, [X29, #408]

0x411b28 UBFM	X14, X5, #60, #59

0x411b2c CNTW	X1, ALL

0x411b30 STP	W15, W9, [X29, #400]

0x411b34 SUB	X14, X14, X4,LSL #3

0x411b38 RDVL	X17, #1

0x411b3c CMP	X1, #8

0x411b40 CSEL	X22, X1, X13, #8

0x411b44 MOVI	D2, #0

0x411b48 FMOV	D0, #1.0000000

0x411b4c SUB	X13, XZR, X1

0x411b50 ADD	X1, X17, X4,LSL #3

0x411b54 SUB	X21, X5, X4,LSL #1

0x411b58 MOVI	V1.2D, #0

0x411b5c PTRUE	P0.D, VL1

0x411b60 ORR	W12, WZR, WZR

0x411b64 LDR	X3, [X8]

0x411b68 ADD	X8, X16, #8

0x411b6c PTRUE	P1.D, ALL

0x411b70 SUB	X16, X4, X5

0x411b74 AND	X7, X21, X13

0x411b78 STP	X8, X21, [X29, #896]

0x411b7c MOVZ	X28, #1

0x411b80 MUL	W8, W5, W9

0x411b84 ADD	X9, X11, X0

0x411b88 MOVN	X26, #0

0x411b8c STUR	X16, [X29, #376]

0x411b90 STP	X9, X22, [SP, #136]

0x411b94 SUB	X9, X18, X4,LSL #3

0x411b98 STR	X9, [SP, #128]

0x411b9c ADD	X9, X18, X14

0x411ba0 STR	X9, [SP, #120]

0x411ba4 SUB	X9, X2, X4,LSL #3

0x411ba8 STUR	X3, [X29, #464]

0x411bac STR	X9, [SP, #112]

0x411bb0 ADD	X9, X2, X14

0x411bb4 STR	X9, [SP, #104]

0x411bb8 SUB	X9, X2, #8

0x411bbc STR	X9, [SP, #96]

0x411bc0 ADD	X9, X2, X0

0x411bc4 STR	X9, [SP, #88]

0x411bc8 ADD	X9, X2, X4,LSL #3

0x411bcc STR	X9, [SP, #72]

0x411bd0 ADD	X9, X2, X1

0x411bd4 STR	X9, [SP, #64]

0x411bd8 ADD	X9, X11, X17

0x411bdc STR	X9, [SP, #56]

0x411be0 ADD	X9, X2, X17

0x411be4 STR	X9, [SP, #48]

0x411be8 ADD	X9, X18, X17

0x411bec STR	X9, [SP, #40]

0x411bf0 ADD	X9, X18, X4,LSL #3

0x411bf4 STR	X9, [SP, #32]

0x411bf8 SUB	X9, X3, X4,LSL #3

0x411bfc STR	X9, [SP, #80]

0x411c00 ADD	X9, X3, X17

0x411c04 ORR	X17, XZR, X2

0x411c08 STR	X9, [SP, #24]

0x411c0c ADD	X9, X11, #8

0x411c10 STP	X11, X9, [X29, #928]

0x411c14 B	411c34

0x411c18 HINT	#0

0x411c1c HINT	#0

(24) 0x411c20 CMP	W10, W15

(24) 0x411c24 ADD	W10, W10, #1

(24) 0x411c28 ADD	W12, W12, #1

(24) 0x411c2c ADD	W8, W23, W5

(24) 0x411c30 B.EQ	412050

(24) 0x411c34 SBFM	X23, X8, #0, #31

(24) 0x411c38 SBFM	X19, X8, #61, #31

(24) 0x411c3c CMP	X21, X22

(24) 0x411c40 B.CS	411c4c

(24) 0x411c44 ORR	X3, XZR, X4

(24) 0x411c48 B	411f54

(24) 0x411c4c LDUR	W8, [X29, #404]

(24) 0x411c50 STUR	W10, [X29, #452]

(24) 0x411c54 LDP	X10, X9, [SP, #88]

(24) 0x411c58 ORR	X2, XZR, X5

(24) 0x411c5c ADD	W8, W8, W12

(24) 0x411c60 MUL	W8, W5, W8

(24) 0x411c64 STUR	X23, [X29, #456]

(24) 0x411c68 STUR	X19, [X29, #440]

(24) 0x411c6c ORR	X19, XZR, X4

(24) 0x411c70 SBFM	X13, X8, #0, #31

(24) 0x411c74 SBFM	X8, X8, #61, #31

(24) 0x411c78 ADD	X0, X4, X13

(24) 0x411c7c ADD	X14, X5, X13

(24) 0x411c80 ADD	X25, X9, X0,LSL #3

(24) 0x411c84 LDR	X9, [SP, #104]

(24) 0x411c88 ADD	X24, X10, X14,LSL #3

(24) 0x411c8c ADD	X4, X18, X0,LSL #3

(24) 0x411c90 ADD	X23, X9, X8

(24) 0x411c94 LDUR	X9, [X29, #408]

(24) 0x411c98 ADD	X1, X9, X13

(24) 0x411c9c LDP	X10, X9, [SP, #112]

(24) 0x411ca0 ADD	X13, X16, X13

(24) 0x411ca4 ORR	X16, XZR, X17

(24) 0x411ca8 ADD	X30, X17, X13,LSL #3

(24) 0x411cac ADD	X15, X18, X1,LSL #3

(24) 0x411cb0 ADD	X27, X17, X1,LSL #3

(24) 0x411cb4 ORR	X17, XZR, X18

(24) 0x411cb8 SUB	X18, X29, #32

(24) 0x411cbc ADD	X22, X10, X8

(24) 0x411cc0 ADD	X21, X9, X8

(24) 0x411cc4 LDP	X9, X8, [SP, #128]

(24) 0x411cc8 LDUR	X10, [X29, #384]

(24) 0x411ccc ADD	X6, X8, X14,LSL #3

(24) 0x411cd0 LDUR	X8, [X29, #416]

(24) 0x411cd4 ADD	X20, X9, X14,LSL #3

(24) 0x411cd8 ADD	X5, X8, X0,LSL #3

(24) 0x411cdc LDR	X8, [SP, #80]

(24) 0x411ce0 ADD	X9, X8, X14,LSL #3

(24) 0x411ce4 LDUR	X8, [X29, #464]

(24) 0x411ce8 ADD	X11, X8, X0,LSL #3

(24) 0x411cec CMP	X11, X6

(24) 0x411cf0 CCMP	X5, X9, #2, #3

(24) 0x411cf4 CSINC	W8, WZR, WZR, #2

(24) 0x411cf8 CMP	X11, X20

(24) 0x411cfc CCMP	X4, X9, #2, #3

(24) 0x411d00 CSINC	W13, WZR, WZR, #2

(24) 0x411d04 CMP	X11, X21

(24) 0x411d08 CCMP	X15, X9, #2, #3

(24) 0x411d0c CSINC	W14, WZR, WZR, #2

(24) 0x411d10 CMP	X11, X22

(24) 0x411d14 CCMP	X30, X9, #2, #3

(24) 0x411d18 CSINC	W0, WZR, WZR, #2

(24) 0x411d1c CMP	X11, X23

(24) 0x411d20 CCMP	X27, X9, #2, #3

(24) 0x411d24 CSINC	W1, WZR, WZR, #2

(24) 0x411d28 CMP	X11, X24

(24) 0x411d2c CCMP	X25, X9, #2, #3

(24) 0x411d30 CSINC	W3, WZR, WZR, #2

(24) 0x411d34 CMP	X18, X6

(24) 0x411d38 CCMP	X5, X10, #2, #3

(24) 0x411d3c CSINC	W6, WZR, WZR, #2

(24) 0x411d40 CMP	X18, X20

(24) 0x411d44 CCMP	X4, X10, #2, #3

(24) 0x411d48 CSINC	W20, WZR, WZR, #2

(24) 0x411d4c CMP	X18, X21

(24) 0x411d50 CCMP	X15, X10, #2, #3

(24) 0x411d54 CSINC	W21, WZR, WZR, #2

(24) 0x411d58 CMP	X18, X22

(24) 0x411d5c CCMP	X30, X10, #2, #3

(24) 0x411d60 CSINC	W22, WZR, WZR, #2

(24) 0x411d64 CMP	X18, X23

(24) 0x411d68 CCMP	X27, X10, #2, #3

(24) 0x411d6c CSINC	W23, WZR, WZR, #2

(24) 0x411d70 CMP	X18, X24

(24) 0x411d74 CCMP	X25, X10, #2, #3

(24) 0x411d78 CSINC	W24, WZR, WZR, #2

(24) 0x411d7c CMP	X18, X9

(24) 0x411d80 CCMP	X11, X10, #2, #3

(24) 0x411d84 B.CC	412010

(24) 0x411d88 LDUR	W15, [X29, #400]

(24) 0x411d8c ORR	X5, XZR, X2

(24) 0x411d90 ORR	X18, XZR, X17

(24) 0x411d94 TBNZ	W8, #0, 412028

(24) 0x411d98 ORR	X4, XZR, X19

(24) 0x411d9c ORR	X17, XZR, X16

(24) 0x411da0 TBNZ	W13, #0, 412008

(24) 0x411da4 LDUR	X16, [X29, #376]

(24) 0x411da8 LDUR	X19, [X29, #440]

(24) 0x411dac TBNZ	W14, #0, 411f40

(24) 0x411db0 LDUR	W10, [X29, #452]

(24) 0x411db4 TBNZ	W0, #0, 411f44

(24) 0x411db8 TBNZ	W1, #0, 411f44

(24) 0x411dbc TBNZ	W3, #0, 411f44

(24) 0x411dc0 TBNZ	W6, #0, 411f44

(24) 0x411dc4 TBNZ	W20, #0, 411f44

(24) 0x411dc8 TBNZ	W21, #0, 411f44

(24) 0x411dcc TBNZ	W22, #0, 411f44

(24) 0x411dd0 TBNZ	W23, #0, 411f44

(24) 0x411dd4 TBNZ	W24, #0, 411f44

(24) 0x411dd8 LDP	X8, X9, [SP, #64]

(24) 0x411ddc LDUR	X2, [X29, #456]

(24) 0x411de0 SEL	Z2.D, P0, Z2.D, Z1.D

(24) 0x411de4 MOVI	V3.2D, #0

(24) 0x411de8 ORR	X3, XZR, XZR

(24) 0x411dec ADD	X30, X9, X19

(24) 0x411df0 ADD	X13, X8, X19

(24) 0x411df4 LDP	X9, X11, [X29, #920]

(24) 0x411df8 ADD	X8, X4, X2

(24) 0x411dfc ADD	X20, X11, X8,LSL #3

(24) 0x411e00 LDR	X11, [SP, #56]

(24) 0x411e04 ADD	X9, X9, X2

(24) 0x411e08 ADD	X25, X17, X9,LSL #3

(24) 0x411e0c ADD	X21, X18, X9,LSL #3

(24) 0x411e10 ADD	X23, X11, X8,LSL #3

(24) 0x411e14 LDP	X14, X11, [SP, #40]

(24) 0x411e18 ADD	X27, X11, X9,LSL #3

(24) 0x411e1c ADD	X24, X14, X9,LSL #3

(24) 0x411e20 LDR	X9, [SP, #32]

(24) 0x411e24 ADD	X0, X14, X8,LSL #3

(24) 0x411e28 ADD	X1, X9, X19

(24) 0x411e2c ADD	X9, X16, X2

(24) 0x411e30 CNTW	X2, ALL

(24) 0x411e34 ADD	X14, X17, X9,LSL #3

(24) 0x411e38 ADD	X6, X11, X9,LSL #3

(24) 0x411e3c LDUR	X9, [X29, #464]

(24) 0x411e40 ADD	X22, X9, X8,LSL #3

(24) 0x411e44 LDR	X9, [SP, #24]

(24) 0x411e48 ADD	X8, X9, X8,LSL #3

  (25) 0x411e4c ADD	X9, X20, X3,LSL #3

  (25) 0x411e50 ADD	X11, X23, X3,LSL #3

  (25) 0x411e54 LD1D	{Z6.D}, P1/Z, [X20, X3,LSL #3]

  (25) 0x411e58 LD1D	{Z16.D}, P1/Z, [X21, X3,LSL #3]

  (25) 0x411e5c FADD	Z22.D, Z6.D, Z16.D

  (25) 0x411e60 LD1D	{Z4.D}, P1/Z, [X9, X28,LSL #3]

  (25) 0x411e64 LD1D	{Z5.D}, P1/Z, [X11, X28,LSL #3]

  (25) 0x411e68 ADD	X9, X30, X3,LSL #3

  (25) 0x411e6c ADD	X11, X13, X3,LSL #3

  (25) 0x411e70 LD1D	{Z24.D}, P1/Z, [X9, X28,LSL #3]

  (25) 0x411e74 LD1D	{Z25.D}, P1/Z, [X11, X28,LSL #3]

  (25) 0x411e78 LD1D	{Z7.D}, P1/Z, [X23, X3,LSL #3]

  (25) 0x411e7c LD1D	{Z17.D}, P1/Z, [X24, X3,LSL #3]

  (25) 0x411e80 LD1D	{Z26.D}, P1/Z, [X9, X26,LSL #3]

  (25) 0x411e84 LD1D	{Z27.D}, P1/Z, [X11, X26,LSL #3]

  (25) 0x411e88 LD1D	{Z28.D}, P1/Z, [X25, X3,LSL #3]

  (25) 0x411e8c LD1D	{Z29.D}, P1/Z, [X27, X3,LSL #3]

  (25) 0x411e90 LD1D	{Z18.D}, P1/Z, [X1, X3,LSL #3]

  (25) 0x411e94 LD1D	{Z19.D}, P1/Z, [X0, X3,LSL #3]

  (25) 0x411e98 MOVPRFX	Z20, Z4

  (25) 0x411e9c FADD	Z20.D, P1/M, Z20.D, #0.0000000

  (25) 0x411ea0 MOVPRFX	Z21, Z5

  (25) 0x411ea4 FADD	Z21.D, P1/M, Z21.D, #0.0000000

  (25) 0x411ea8 LD1D	{Z30.D}, P1/Z, [X14, X3,LSL #3]

  (25) 0x411eac LD1D	{Z31.D}, P1/Z, [X6, X3,LSL #3]

  (25) 0x411eb0 FMUL	Z4.D, Z24.D, Z4.D

  (25) 0x411eb4 FMUL	Z5.D, Z25.D, Z5.D

  (25) 0x411eb8 LD1D	{Z23.D}, P1/Z, [X13, X3,LSL #3]

  (25) 0x411ebc FADD	Z20.D, Z20.D, Z22.D

  (25) 0x411ec0 FADD	Z22.D, Z7.D, Z17.D

  (25) 0x411ec4 FADD	Z21.D, Z21.D, Z22.D

  (25) 0x411ec8 LD1D	{Z22.D}, P1/Z, [X30, X3,LSL #3]

  (25) 0x411ecc FMLA	Z4.D, P1/M, Z26.D, Z6.D

  (25) 0x411ed0 FMLA	Z5.D, P1/M, Z27.D, Z7.D

  (25) 0x411ed4 FADD	Z20.D, Z20.D, Z18.D

  (25) 0x411ed8 LD1D	{Z6.D}, P1/Z, [X30, X3,LSL #3]

  (25) 0x411edc LD1D	{Z7.D}, P1/Z, [X13, X3,LSL #3]

  (25) 0x411ee0 FMLA	Z4.D, P1/M, Z28.D, Z16.D

  (25) 0x411ee4 FMLA	Z5.D, P1/M, Z29.D, Z17.D

  (25) 0x411ee8 FADD	Z21.D, Z21.D, Z19.D

  (25) 0x411eec FMLA	Z4.D, P1/M, Z30.D, Z18.D

  (25) 0x411ef0 FMLA	Z5.D, P1/M, Z31.D, Z19.D

  (25) 0x411ef4 FNMLS	Z4.D, P1/M, Z22.D, Z20.D

  (25) 0x411ef8 FNMLS	Z5.D, P1/M, Z23.D, Z21.D

  (25) 0x411efc FMLA	Z2.D, P1/M, Z6.D, Z4.D

  (25) 0x411f00 FMLA	Z3.D, P1/M, Z7.D, Z5.D

  (25) 0x411f04 ST1D	{Z4.D}, P1, [X22, X3,LSL #3]

  (25) 0x411f08 ST1D	{Z5.D}, P1, [X8, X3,LSL #3]

  (25) 0x411f0c ADD	X3, X3, X2

  (25) 0x411f10 CMP	X7, X3

  (25) 0x411f14 B.NE	411e4c

(24) 0x411f18 FADD	Z2.D, Z3.D, Z2.D

(24) 0x411f1c LDUR	X21, [X29, #392]

(24) 0x411f20 LDR	X22, [SP, #144]

(24) 0x411f24 LDUR	X23, [X29, #456]

(24) 0x411f28 ADD	X3, X7, X4

(24) 0x411f2c CMP	X21, X7

(24) 0x411f30 FADDV	D2, P1, Z2.D

(24) 0x411f34 STUR	D2, [X29, #480]

(24) 0x411f38 B.EQ	411c20

(24) 0x411f3c B	411f54

(24) 0x411f40 LDUR	W10, [X29, #452]

(24) 0x411f44 ORR	X3, XZR, X4

(24) 0x411f48 LDUR	X21, [X29, #392]

(24) 0x411f4c LDR	X22, [SP, #144]

(24) 0x411f50 LDUR	X23, [X29, #456]

(24) 0x411f54 ADD	X9, X3, X23

(24) 0x411f58 LDP	X2, X8, [X29, #936]

(24) 0x411f5c ADD	X1, X16, X3

(24) 0x411f60 ORR	X13, XZR, XZR

(24) 0x411f64 ADD	X11, X9, X5

(24) 0x411f68 ADD	X14, X18, X11,LSL #3

(24) 0x411f6c ADD	X0, X17, X11,LSL #3

(24) 0x411f70 ADD	X11, X19, X3,LSL #3

(24) 0x411f74 ADD	X3, X18, X11

(24) 0x411f78 ADD	X19, X17, X11

(24) 0x411f7c LDUR	X11, [X29, #464]

(24) 0x411f80 ADD	X8, X9, X8

(24) 0x411f84 ADD	X6, X2, X9,LSL #3

(24) 0x411f88 ADD	X8, X17, X8,LSL #3

(24) 0x411f8c ADD	X20, X11, X9,LSL #3

(24) 0x411f90 HINT	#0

(24) 0x411f94 HINT	#0

(24) 0x411f98 HINT	#0

(24) 0x411f9c HINT	#0

  (23) 0x411fa0 ADD	X9, X6, X13

  (23) 0x411fa4 LDR	D5, [X14, X13]

  (23) 0x411fa8 LDR	D19, [X0, X13]

  (23) 0x411fac LDR	D6, [X3, X13]

  (23) 0x411fb0 ADDS	X1, X1, #1

  (23) 0x411fb4 LDR	D20, [X8, X13]

  (23) 0x411fb8 LDP	D4, D3, [X9, #1016]

  (23) 0x411fbc ADD	X9, X19, X13

  (23) 0x411fc0 FADD	D7, D3, D0

  (23) 0x411fc4 LDUR	D18, [X9, #504]

  (23) 0x411fc8 FADD	D16, D4, D5

  (23) 0x411fcc FADD	D7, D7, D16

  (23) 0x411fd0 LDP	D17, D16, [X9]

  (23) 0x411fd4 FMUL	D3, D16, D3

  (23) 0x411fd8 FMADD	D3, D18, D4, D3

  (23) 0x411fdc FADD	D7, D7, D6

  (23) 0x411fe0 FMADD	D3, D19, D5, D3

  (23) 0x411fe4 FMADD	D3, D20, D6, D3

  (23) 0x411fe8 FNMSUB	D3, D17, D7, D3

  (23) 0x411fec STR	D3, [X20, X13]

  (23) 0x411ff0 ADD	X13, X13, #8

  (23) 0x411ff4 LDR	D4, [X9]

  (23) 0x411ff8 FMADD	D2, D4, D3, D2

  (23) 0x411ffc STUR	D2, [X29, #480]

  (23) 0x412000 B.CC	411fa0

(24) 0x412004 B	411c20

(24) 0x412008 ORR	X3, XZR, X4

(24) 0x41200c B	412034

(24) 0x412010 LDUR	W15, [X29, #400]

(24) 0x412014 ORR	X4, XZR, X19

(24) 0x412018 ORR	X3, XZR, X19

(24) 0x41201c ORR	X5, XZR, X2

(24) 0x412020 ORR	X18, XZR, X17

(24) 0x412024 B	412030

(24) 0x412028 ORR	X4, XZR, X19

(24) 0x41202c ORR	X3, XZR, X19

(24) 0x412030 ORR	X17, XZR, X16

(24) 0x412034 LDUR	X16, [X29, #376]

(24) 0x412038 LDUR	W10, [X29, #452]

(24) 0x41203c LDUR	X21, [X29, #392]

(24) 0x412040 LDR	X22, [SP, #144]

(24) 0x412044 LDUR	X23, [X29, #456]

(24) 0x412048 LDUR	X19, [X29, #440]

(24) 0x41204c B	411f54

0x412050 LDR	W19, [SP, #12]

0x412054 ADRP	X0,

0x412058 ADD	X0, X0, #1072

0x41205c ORR	W1, WZR, W19

0x412060 BL	4102d0

0x412064 SUB	X8, X29, #32

0x412068 ADRP	X6,

0x41206c ADRP	X0,

0x412070 ADD	X0, X0, #1096

0x412074 ORR	W1, WZR, W19

0x412078 STUR	X8, [X29, #472]

0x41207c ADRP	X5, 41207c

0x412080 ADD	X5, X5, #304

0x412084 SUB	X4, X29, #40

0x412088 MOVZ	W2, #1

0x41208c LDR	X6, [X6, #4016]

0x412090 MOVZ	W3, #8

0x412094 BL	4102a0

0x412098 CMP	W0, #2

0x41209c B.EQ	4120d8

0x4120a0 LDR	X8, [SP, #16]

0x4120a4 CMP	W0, #1

0x4120a8 B.NE	412104

0x4120ac LDR	D0, [X8]

0x4120b0 LDUR	D1, [X29, #480]

0x4120b4 ADRP	X2,

0x4120b8 ADRP	X0,

0x4120bc ADD	X0, X0, #1096

0x4120c0 ORR	W1, WZR, W19

0x4120c4 FADD	D0, D1, D0

0x4120c8 STR	D0, [X8]

0x4120cc LDR	X2, [X2, #4016]

0x4120d0 BL	410160

0x4120d4 B	412104

0x4120d8 LDR	X11, [SP, #16]

0x4120dc LDUR	D0, [X29, #480]

0x4120e0 LDR	D1, [X11]

(22) 0x4120e4 FADD	D2, D1, D0

(22) 0x4120e8 FMOV	X9, D1

(22) 0x4120ec ORR	X10, XZR, X9

(22) 0x4120f0 FMOV	X8, D2

(22) 0x4120f4 CAS	X10, X8, [X11]

(22) 0x4120f8 FMOV	D1, X10

(22) 0x4120fc CMP	X10, X9

(22) 0x412100 B.NE	4120e4

0x412104 LDP	X20, X19, [SP, #368]

0x412108 LDP	X22, X21, [SP, #352]

0x41210c LDP	X24, X23, [SP, #336]

0x412110 LDP	X26, X25, [SP, #320]

0x412114 LDP	X28, X27, [SP, #304]

0x412118 LDP	X29, X30, [SP, #288]

0x41211c ADD	SP, SP, #384

0x412120 RET

0x412124 HINT	#0

0x412128 HINT	#0

0x41212c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.41+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.59+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	run_cg_calc_w(Chunk*, Settings[...]	cg.cpp:94	exec
○	cg_main_step_driver(Chunk*, Se[...]	cg_driver.cpp:57	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:18	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:45	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:169	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run armclang_1

Source file and lines	cg.cpp:83-90
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83-90.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.75 to 2.00 cycles (11.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 26% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 22.75 to 13.50 cycles (1.69x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 18 bytes. The binary function is storing 9 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	172
nb uops	167
loop length	688
used w registers	17
used x registers	29
used b registers	0
used h registers	0
used s registers	1
used d registers	3
used q registers	0
used v registers	1
used z registers	0
nb stack references	33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.88 cycles
front end	20.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	22.75	22.75	22.75	22.75	1.25	1.25	1.25	1.25	21.50	21.17	21.33	18.00	18.00
cycles	6.00	6.00	22.75	22.75	22.75	22.75	1.25	1.25	1.25	1.25	21.50	21.17	21.33	18.00	18.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.88
Dispatch	22.75
Overall L1	22.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	26%
load	25%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	24%
fma	NA (no fma vectorizable/vectorized instructions)
other	24%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	26%
load	25%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	24%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.75 cycles. At this rate:

0% of peak load performance is reached (0.79 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 411a30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W23, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W23, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 412104 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X20, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <44fa80>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1048	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X3, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR XZR, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORN W9, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W1, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W25, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W25, WZR, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP WZR, W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W10, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W15, W8, W25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W8, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W15, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W10, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 412050 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X4, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDRSW X5, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W8, W5, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W4, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 412050 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X16, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X0, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W9, W10, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X14, X4, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X2, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X0, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X0, X13, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X14, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UBFM X14, X5, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTW X1, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STP W15, W9, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X14, X14, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
RDVL X17, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X22, X1, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB X13, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X17, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X21, X5, X4,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI V1.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
PTRUE P0.D, VL1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ORR W12, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X3, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUB X16, X4, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X7, X21, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X8, X21, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL W8, W5, W9	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X9, X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVN X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X16, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X9, X22, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X9, X18, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X18, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X9, X2, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X3, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X2, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X9, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X2, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X11, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X2, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X18, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X9, X3, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X3, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X17, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X11, X9, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 411c34 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W19, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <44f054>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1072	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4102d0 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X6, <44f068>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <44f06c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADRP X5, 41207c <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x64c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X5, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X6, #4016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4120d8 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x6a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 412104 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDUR D1, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADRP X2, <44f0b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <44f0b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X2, [X2, #4016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 410160 <@plt_start@+0x140>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 412104 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR D0, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run armclang_1

Source file and lines	cg.cpp:83-90
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83-90.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 18 bytes. The binary function is storing 9 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	172
nb uops	167
loop length	688
used w registers	17
used x registers	29
used b registers	0
used h registers	0
used s registers	1
used d registers	3
used q registers	0
used v registers	1
used z registers	0
nb stack references	33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.88 cycles
front end	20.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	22.75	22.75	22.75	22.75	1.25	1.25	1.25	1.25	21.50	21.17	21.33	18.00	18.00
cycles	6.00	6.00	22.75	22.75	22.75	22.75	1.25	1.25	1.25	1.25	21.50	21.17	21.33	18.00	18.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.88
Dispatch	22.75
Overall L1	22.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	26%
load	25%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	24%
fma	NA (no fma vectorizable/vectorized instructions)
other	24%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	26%
load	25%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	24%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.75 cycles. At this rate:

0% of peak load performance is reached (0.79 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 411a30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W23, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W23, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 412104 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X20, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <44fa80>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1048	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X3, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR XZR, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORN W9, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W1, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W25, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W25, WZR, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP WZR, W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W10, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W15, W8, W25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W8, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W15, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W10, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 412050 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X4, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDRSW X5, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W8, W5, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W4, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 412050 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X16, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X0, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W9, W10, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X14, X4, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X2, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X0, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X0, X13, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X14, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UBFM X14, X5, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTW X1, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STP W15, W9, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X14, X14, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
RDVL X17, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X22, X1, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB X13, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X17, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X21, X5, X4,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI V1.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
PTRUE P0.D, VL1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ORR W12, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X3, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUB X16, X4, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X7, X21, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X8, X21, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL W8, W5, W9	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X9, X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVN X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X16, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X9, X22, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X9, X18, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X18, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X9, X2, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X3, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X2, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X9, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X2, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X11, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X2, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X18, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X9, X3, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X3, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X17, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X11, X9, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 411c34 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W19, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <44f054>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1072	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4102d0 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X6, <44f068>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <44f06c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADRP X5, 41207c <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x64c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X5, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X6, #4016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4120d8 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x6a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 412104 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDUR D1, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADRP X2, <44f0b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <44f0b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X2, [X2, #4016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 410160 <@plt_start@+0x140>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 412104 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR D0, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼cg_calc_w(int, int, int, double, double const, double, double const, double const*) [clone .omp_outlined]–	33.00	88.07
▼Loop 24 - cg.cpp:85-90 - exec–	0.31	0.82
○Loop 25 - cg.cpp:86-90 - exec	32.68	87.22
○Loop 23 - cg.cpp:86-90 - exec	0.00	0.00
○Loop 22 - cg.cpp:83-83 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

Arithmetic intensity

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Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code