OV - exec - Function cg_calc_ur(int, int, int, double, double*, double*, double const*, double*, double const*) [clone .omp

	Function: cg_calc_ur(int, int, int, double, double, double, double const, double, double const*) ...	Module: exec	Source: cg.cpp:105-113	Coverage (incl. loops): 43.33% \| (excl. loops): 0.01%

/home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 105 - 113

--------------------------------------------------------------------------------

105:   #pragma omp parallel for reduction(+ : rrn_temp)

106: #endif

107:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

108:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

109:       const int index = kk + jj * x;

110:

111:       u[index] += alpha * p[index];

112:       r[index] -= alpha * w[index];

113:       rrn_temp += r[index] * r[index];

0x4121e0 SUB	SP, SP, #176

0x4121e4 STP	X29, X30, [SP, #80]

0x4121e8 STP	X28, X27, [SP, #96]

0x4121ec STP	X26, X25, [SP, #112]

0x4121f0 STP	X24, X23, [SP, #128]

0x4121f4 STP	X22, X21, [SP, #144]

0x4121f8 STP	X20, X19, [SP, #160]

0x4121fc ADD	X29, SP, #80

0x412200 LDR	W25, [X3]

0x412204 LDR	W8, [X2]

0x412208 SUB	W8, W8, W25

0x41220c CMP	W25, W8

0x412210 B.GE	412600

0x412214 LDR	W1, [X0]

0x412218 LDR	X23, [X29, #112]

0x41221c ORN	W9, WZR, W25

0x412220 ORR	X20, XZR, X6

0x412224 ORR	X21, XZR, X4

0x412228 ORR	X22, XZR, X3

0x41222c ORR	X26, XZR, X7

0x412230 ORR	X24, XZR, X5

0x412234 ADD	W19, W8, W9

0x412238 MOVZ	W8, #1

0x41223c ADRP	X0,

0x412240 ADD	X0, X0, #1144

0x412244 SUB	X3, X29, #16

0x412248 SUB	X4, X29, #4

0x41224c SUB	X5, X29, #8

0x412250 SUB	X6, X29, #12

0x412254 MOVZ	W2, #34

0x412258 MOVZ	W7, #1

0x41225c STP	W19, WZR, [X29, #504]

0x412260 STP	WZR, W8, [X29, #496]

0x412264 STUR	XZR, [X29, #488]

0x412268 STR	W8, [SP]

0x41226c STR	W1, [SP, #12]

0x412270 BL	4100a0

0x412274 LDP	W8, W10, [X29, #504]

0x412278 CMP	W8, W19

0x41227c CSEL	W8, W8, W19, #3

0x412280 ADD	W9, W8, #1

0x412284 STUR	W8, [X29, #504]

0x412288 CMP	W10, W9

0x41228c B.CS	412550

0x412290 LDRSW	X9, [X22]

0x412294 LDRSW	X11, [X21]

0x412298 SUB	W12, W11, W9

0x41229c CMP	W9, W12

0x4122a0 B.GE	412550

0x4122a4 LDP	X2, X1, [X29, #96]

0x4122a8 LDR	X15, [X26]

0x4122ac CNTW	X0, ALL

0x4122b0 RDVL	X7, #1

0x4122b4 LDR	X18, [X24]

0x4122b8 SUB	X14, X29, #24

0x4122bc ADD	X16, X20, #8

0x4122c0 MOVZ	W4, #12

0x4122c4 ADD	W13, W10, W25

0x4122c8 ADD	X3, X14, #8

0x4122cc SUB	X17, X11, X9,LSL #1

0x4122d0 MUL	W6, W11, W13

0x4122d4 MOVI	D1, #0

0x4122d8 MOVI	V0.2D, #0

0x4122dc ORR	W12, WZR, WZR

0x4122e0 CMP	X0, #12

0x4122e4 CSEL	X4, X0, X4, #8

0x4122e8 CMP	X14, X16

0x4122ec LDR	X1, [X1]

0x4122f0 LDR	X2, [X2]

0x4122f4 ADD	X19, X15, X7

0x4122f8 SUB	X5, XZR, X0

0x4122fc CCMP	X20, X3, #2, #3

0x412300 PTRUE	P0.D, VL1

0x412304 PTRUE	P1.D, ALL

0x412308 AND	X5, X17, X5

0x41230c CSINC	W21, WZR, WZR, #2

0x412310 STR	X19, [SP, #40]

0x412314 ADD	X19, X18, X7

0x412318 ADD	X16, X2, X7

0x41231c STR	X19, [SP, #32]

0x412320 ADD	X19, X1, X7

0x412324 STP	X16, X19, [SP, #16]

0x412328 B	412340

(28) 0x41232c CMP	W10, W8

(28) 0x412330 ADD	W10, W10, #1

(28) 0x412334 ADD	W12, W12, #1

(28) 0x412338 ADD	W6, W6, W11

(28) 0x41233c B.EQ	412550

(28) 0x412340 SBFM	X6, X6, #0, #31

(28) 0x412344 CMP	X17, X4

(28) 0x412348 B.CS	4123a8

(28) 0x41234c ORR	X19, XZR, X9

(28) 0x412350 ADD	X25, X19, X6

(28) 0x412354 SUB	X16, X9, X11

(28) 0x412358 ADD	X7, X15, X25,LSL #3

(28) 0x41235c ADD	X22, X18, X25,LSL #3

(28) 0x412360 ADD	X24, X1, X25,LSL #3

(28) 0x412364 ADD	X25, X2, X25,LSL #3

(28) 0x412368 ADD	X26, X16, X19

  (27) 0x41236c LDR	D2, [X20]

  (27) 0x412370 LDR	D3, [X7], #8

  (27) 0x412374 LDR	D4, [X22]

  (27) 0x412378 ADDS	X26, X26, #1

  (27) 0x41237c FMADD	D2, D3, D2, D4

  (27) 0x412380 STR	D2, [X22], #8

  (27) 0x412384 LDR	D2, [X20]

  (27) 0x412388 LDR	D3, [X24], #8

  (27) 0x41238c LDR	D4, [X25]

  (27) 0x412390 FMSUB	D2, D3, D2, D4

  (27) 0x412394 FMADD	D1, D2, D2, D1

  (27) 0x412398 STR	D2, [X25], #8

  (27) 0x41239c STUR	D1, [X29, #488]

  (27) 0x4123a0 B.CC	41236c

(28) 0x4123a4 B	41232c

(28) 0x4123a8 ADD	W7, W13, W12

(28) 0x4123ac SUB	X27, X2, X9,LSL #3

(28) 0x4123b0 SUB	X22, X1, X9,LSL #3

(28) 0x4123b4 SUB	X25, X15, X9,LSL #3

(28) 0x4123b8 SUB	X30, X18, X9,LSL #3

(28) 0x4123bc ADD	X16, X20, #8

(28) 0x4123c0 MUL	W7, W11, W7

(28) 0x4123c4 SBFM	X7, X7, #0, #31

(28) 0x4123c8 ADD	X19, X11, X7

(28) 0x4123cc ADD	X7, X9, X7

(28) 0x4123d0 ADD	X24, X1, X7,LSL #3

(28) 0x4123d4 ADD	X26, X15, X7,LSL #3

(28) 0x4123d8 ADD	X27, X27, X19,LSL #3

(28) 0x4123dc ADD	X28, X2, X7,LSL #3

(28) 0x4123e0 ADD	X7, X18, X7,LSL #3

(28) 0x4123e4 ADD	X22, X22, X19,LSL #3

(28) 0x4123e8 ADD	X25, X25, X19,LSL #3

(28) 0x4123ec ADD	X19, X30, X19,LSL #3

(28) 0x4123f0 CMP	X7, X27

(28) 0x4123f4 CCMP	X28, X19, #2, #3

(28) 0x4123f8 CSINC	W30, WZR, WZR, #2

(28) 0x4123fc CMP	X7, X3

(28) 0x412400 CCMP	X14, X19, #2, #3

(28) 0x412404 CSINC	W30, W30, WZR, #2

(28) 0x412408 CMP	X7, X16

(28) 0x41240c CCMP	X20, X19, #2, #3

(28) 0x412410 CSINC	W30, W30, WZR, #2

(28) 0x412414 CMP	X7, X25

(28) 0x412418 CCMP	X26, X19, #2, #3

(28) 0x41241c CSINC	W30, W30, WZR, #2

(28) 0x412420 CMP	X7, X22

(28) 0x412424 CCMP	X24, X19, #2, #3

(28) 0x412428 CSINC	W7, W30, WZR, #2

(28) 0x41242c CMP	X28, X3

(28) 0x412430 CCMP	X14, X27, #2, #3

(28) 0x412434 CSINC	W7, W7, WZR, #2

(28) 0x412438 CMP	X28, X16

(28) 0x41243c CCMP	X20, X27, #2, #3

(28) 0x412440 CSINC	W7, W7, WZR, #2

(28) 0x412444 CMP	X28, X25

(28) 0x412448 CCMP	X26, X27, #2, #3

(28) 0x41244c CSINC	W19, WZR, WZR, #2

(28) 0x412450 CMP	X28, X22

(28) 0x412454 CCMP	X24, X27, #2, #3

(28) 0x412458 CSINC	W27, WZR, WZR, #2

(28) 0x41245c CMP	X14, X25

(28) 0x412460 ORR	W19, W19, W27

(28) 0x412464 CCMP	X26, X3, #2, #3

(28) 0x412468 ORR	W19, W19, W21

(28) 0x41246c ORR	W27, W7, W19

(28) 0x412470 CSINC	W7, WZR, WZR, #2

(28) 0x412474 CMP	X14, X22

(28) 0x412478 CCMP	X24, X3, #2, #3

(28) 0x41247c CSINC	W19, WZR, WZR, #2

(28) 0x412480 TBNZ	W27, #0, 41234c

(28) 0x412484 TBNZ	W7, #0, 41234c

(28) 0x412488 TBNZ	W19, #0, 41234c

(28) 0x41248c LDR	X19, [SP, #40]

(28) 0x412490 ADD	X30, X9, X6

(28) 0x412494 LDR	D2, [X20]

(28) 0x412498 SEL	Z1.D, P0, Z1.D, Z0.D

(28) 0x41249c MOVI	V3.2D, #0

(28) 0x4124a0 ORR	X7, XZR, XZR

(28) 0x4124a4 ADD	X24, X15, X30,LSL #3

(28) 0x4124a8 ADD	X22, X18, X30,LSL #3

(28) 0x4124ac ADD	X27, X1, X30,LSL #3

(28) 0x4124b0 ADD	X25, X19, X30,LSL #3

(28) 0x4124b4 LDR	X19, [SP, #32]

(28) 0x4124b8 DUP	Z2.D, Z2.D[0]

(28) 0x4124bc ADD	X26, X19, X30,LSL #3

(28) 0x4124c0 LDP	X16, X19, [SP, #16]

(28) 0x4124c4 ADD	X28, X19, X30,LSL #3

(28) 0x4124c8 ADD	X19, X2, X30,LSL #3

(28) 0x4124cc ADD	X30, X16, X30,LSL #3

(28) 0x4124d0 HINT	#0

(28) 0x4124d4 HINT	#0

(28) 0x4124d8 HINT	#0

(28) 0x4124dc HINT	#0

  (29) 0x4124e0 LD1D	{Z4.D}, P1/Z, [X24, X7,LSL #3]

  (29) 0x4124e4 LD1D	{Z5.D}, P1/Z, [X25, X7,LSL #3]

  (29) 0x4124e8 LD1D	{Z6.D}, P1/Z, [X22, X7,LSL #3]

  (29) 0x4124ec FMAD	Z4.D, P1/M, Z2.D, Z6.D

  (29) 0x4124f0 LD1D	{Z7.D}, P1/Z, [X26, X7,LSL #3]

  (29) 0x4124f4 FMAD	Z5.D, P1/M, Z2.D, Z7.D

  (29) 0x4124f8 LD1D	{Z6.D}, P1/Z, [X19, X7,LSL #3]

  (29) 0x4124fc LD1D	{Z7.D}, P1/Z, [X30, X7,LSL #3]

  (29) 0x412500 ST1D	{Z4.D}, P1, [X22, X7,LSL #3]

  (29) 0x412504 ST1D	{Z5.D}, P1, [X26, X7,LSL #3]

  (29) 0x412508 LD1D	{Z4.D}, P1/Z, [X27, X7,LSL #3]

  (29) 0x41250c LD1D	{Z5.D}, P1/Z, [X28, X7,LSL #3]

  (29) 0x412510 FMSB	Z4.D, P1/M, Z2.D, Z6.D

  (29) 0x412514 FMSB	Z5.D, P1/M, Z2.D, Z7.D

  (29) 0x412518 FMLA	Z1.D, P1/M, Z4.D, Z4.D

  (29) 0x41251c FMLA	Z3.D, P1/M, Z5.D, Z5.D

  (29) 0x412520 ST1D	{Z4.D}, P1, [X19, X7,LSL #3]

  (29) 0x412524 ST1D	{Z5.D}, P1, [X30, X7,LSL #3]

  (29) 0x412528 ADD	X7, X7, X0

  (29) 0x41252c CMP	X5, X7

  (29) 0x412530 B.NE	4124e0

(28) 0x412534 FADD	Z1.D, Z3.D, Z1.D

(28) 0x412538 CMP	X17, X5

(28) 0x41253c ADD	X19, X5, X9

(28) 0x412540 FADDV	D1, P1, Z1.D

(28) 0x412544 STUR	D1, [X29, #488]

(28) 0x412548 B.EQ	41232c

(28) 0x41254c B	412350

0x412550 LDR	W19, [SP, #12]

0x412554 ADRP	X0,

0x412558 ADD	X0, X0, #1168

0x41255c ORR	W1, WZR, W19

0x412560 BL	4102d0

0x412564 SUB	X8, X29, #24

0x412568 ADRP	X6,

0x41256c ADRP	X0,

0x412570 ADD	X0, X0, #1192

0x412574 ORR	W1, WZR, W19

0x412578 STUR	X8, [X29, #480]

0x41257c ADRP	X5, 41257c

0x412580 ADD	X5, X5, #1568

0x412584 SUB	X4, X29, #32

0x412588 MOVZ	W2, #1

0x41258c LDR	X6, [X6, #4016]

0x412590 MOVZ	W3, #8

0x412594 BL	4102a0

0x412598 CMP	W0, #2

0x41259c B.EQ	4125d4

0x4125a0 CMP	W0, #1

0x4125a4 B.NE	412600

0x4125a8 LDR	D0, [X23]

0x4125ac LDUR	D1, [X29, #488]

0x4125b0 ADRP	X2,

0x4125b4 ADRP	X0,

0x4125b8 ADD	X0, X0, #1192

0x4125bc ORR	W1, WZR, W19

0x4125c0 FADD	D0, D1, D0

0x4125c4 STR	D0, [X23]

0x4125c8 LDR	X2, [X2, #4016]

0x4125cc BL	410160

0x4125d0 B	412600

0x4125d4 LDUR	D0, [X29, #488]

0x4125d8 LDR	D1, [X23]

0x4125dc HINT	#0

(26) 0x4125e0 FADD	D2, D1, D0

(26) 0x4125e4 FMOV	X9, D1

(26) 0x4125e8 ORR	X10, XZR, X9

(26) 0x4125ec FMOV	X8, D2

(26) 0x4125f0 CAS	X10, X8, [X23]

(26) 0x4125f4 FMOV	D1, X10

(26) 0x4125f8 CMP	X10, X9

(26) 0x4125fc B.NE	4125e0

0x412600 LDP	X20, X19, [SP, #160]

0x412604 LDP	X22, X21, [SP, #144]

0x412608 LDP	X24, X23, [SP, #128]

0x41260c LDP	X26, X25, [SP, #112]

0x412610 LDP	X28, X27, [SP, #96]

0x412614 LDP	X29, X30, [SP, #80]

0x412618 ADD	SP, SP, #176

0x41261c RET

Coverage (%)	Name	Source Location	Module
►98.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	run_cg_calc_ur(Chunk*, Setting[...]	cg.cpp:117	exec
○	cg_main_step_driver(Chunk*, Se[...]	cg_driver.cpp:69	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:18	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:45	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:169	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run armclang_1

Source file and lines	cg.cpp:105-113
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:105-113.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.25 to 2.00 cycles (9.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 18.25 to 11.25 cycles (1.62x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:105
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:105
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:105
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:105

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 18 bytes. The binary function is storing 9 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	127
nb uops	126
loop length	508
used w registers	17
used x registers	29
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	1
used z registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.75 cycles
front end	15.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	18.25	18.25	18.25	18.25	1.00	1.00	1.00	1.00	14.17	13.83	14.00	8.00	8.00
cycles	6.00	6.00	18.25	18.25	18.25	18.25	1.00	1.00	1.00	1.00	14.17	13.83	14.00	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.75
Dispatch	18.25
Overall L1	18.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	24%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	25%
load	24%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.25 cycles. At this rate:

1% of peak load performance is reached (0.99 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.49 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4121e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W25, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W8, W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W25, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 412600 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN W9, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X20, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W19, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <44f23c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP W19, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR XZR, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W1, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W10, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W8, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W8, W8, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR W8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 412550 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDRSW X11, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W12, W11, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W9, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 412550 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X2, X1, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X15, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTW X0, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
RDVL X7, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X18, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X14, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W13, W10, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X3, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X17, X11, X9,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL W6, W11, W13	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V0.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR W12, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X0, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X4, X0, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X19, X15, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP X20, X3, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P0.D, VL1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
AND X5, X17, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W21, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X19, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X19, X18, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X2, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X19, X1, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X16, X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 412340 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <44f554>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4102d0 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X6, <44f568>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <44f56c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADRP X5, 41257c <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x39c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X5, #1568	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X6, #4016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4125d4 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x3f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 412600 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDUR D1, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADRP X2, <44f5b0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <44f5b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X23]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X2, [X2, #4016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 410160 <@plt_start@+0x140>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 412600 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR D0, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
HINT #0																			N/A
LDP X20, X19, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run armclang_1

Source file and lines	cg.cpp:105-113
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:105-113.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.25 to 2.00 cycles (9.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:105
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:105
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:105
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:105

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 18 bytes. The binary function is storing 9 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	127
nb uops	126
loop length	508
used w registers	17
used x registers	29
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	1
used z registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.75 cycles
front end	15.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	18.25	18.25	18.25	18.25	1.00	1.00	1.00	1.00	14.17	13.83	14.00	8.00	8.00
cycles	6.00	6.00	18.25	18.25	18.25	18.25	1.00	1.00	1.00	1.00	14.17	13.83	14.00	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.75
Dispatch	18.25
Overall L1	18.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	24%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	25%
load	24%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.25 cycles. At this rate:

1% of peak load performance is reached (0.99 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.49 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4121e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W25, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W8, W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W25, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 412600 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN W9, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X20, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W19, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <44f23c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP W19, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR XZR, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W1, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W10, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W8, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W8, W8, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR W8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 412550 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDRSW X11, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W12, W11, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W9, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 412550 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X2, X1, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X15, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTW X0, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
RDVL X7, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X18, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X14, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W13, W10, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X3, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X17, X11, X9,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL W6, W11, W13	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V0.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR W12, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X0, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X4, X0, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X19, X15, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP X20, X3, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P0.D, VL1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
AND X5, X17, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W21, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X19, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X19, X18, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X2, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X19, X1, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X16, X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 412340 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <44f554>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4102d0 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X6, <44f568>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <44f56c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADRP X5, 41257c <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x39c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X5, #1568	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X6, #4016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4125d4 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x3f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 412600 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDUR D1, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADRP X2, <44f5b0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <44f5b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X23]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X2, [X2, #4016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 410160 <@plt_start@+0x140>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 412600 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR D0, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
HINT #0																			N/A
LDP X20, X19, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼cg_calc_ur(int, int, int, double, double, double, double const, double, double const*) [clone .omp_outlined]–	43.33	115.64
▼Loop 28 - cg.cpp:105-113 - exec–	0.16	0.42
○Loop 29 - cg.cpp:108-113 - exec	43.16	115.18
○Loop 27 - cg.cpp:108-113 - exec	0.00	0.00
○Loop 26 - cg.cpp:105-105 - exec	0.00	0.00

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