OV - exec - Function cg_calc_w(int, int, int, double*, double const*, double*, double const*, double const*) [clone ._omp

	Function: cg_calc_w(int, int, int, double, double const, double, double const, double const*) [c ...	Module: exec	Source: cg.cpp:83-90	Coverage (incl. loops): 32.74% \| (excl. loops): 0.02%

/home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 83 - 90

--------------------------------------------------------------------------------

83:   #pragma omp parallel for reduction(+ : pw_temp)

84: #endif

85:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

86:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

87:       const int index = kk + jj * x;

88:       const double smvp = tealeaf_SMVP(p);

89:       w[index] = smvp;

90:       pw_temp += w[index] * p[index];

0x411640 STP	X29, X30, [SP, #976]!

0x411644 ADD	X29, SP, #0

0x411648 STP	X19, X20, [SP, #16]

0x41164c ORR	X19, XZR, X0

0x411650 LDR	W20, [X0, #48]

0x411654 STR	X21, [SP, #32]

0x411658 BL	410100

0x41165c ORR	W21, WZR, W0

0x411660 BL	410110

0x411664 LDR	W1, [X19, #44]

0x411668 ORR	W14, WZR, W0

0x41166c SUB	W0, W1, W20,LSL #1

0x411670 SDIV	W2, W0, W21

0x411674 MSUB	W3, W2, W21, W0

0x411678 CMP	W14, W3

0x41167c B.LT	41186c

0x411680 MADD	W4, W2, W14, W3

0x411684 MOVI	D27, #0

0x411688 ADD	W5, W2, W4

0x41168c CMP	W4, W5

0x411690 B.GE	411838

0x411694 LDR	W16, [X19, #40]

0x411698 ADD	W21, W20, W5

0x41169c ADD	W14, W20, W4

0x4116a0 LDP	X3, X11, [X19]

0x4116a4 FMOV	D24, #1.0000000

0x4116a8 SBFM	X30, X20, #0, #31

0x4116ac LDP	X6, X5, [X19, #16]

0x4116b0 SUB	W17, W16, W20,LSL #1

0x4116b4 SBFM	X13, X16, #61, #31

0x4116b8 SUB	W18, W16, W20

0x4116bc MUL	W15, W14, W16

0x4116c0 ADD	X12, X3, X13

0x4116c4 SUB	X10, X3, X13

0x4116c8 ADD	X0, X17, X30

0x4116cc ADD	X9, X3, #8

0x4116d0 SUB	X8, X3, #8

0x4116d4 ADD	X7, X6, #8

0x4116d8 ADD	X4, X5, X13

0x4116dc HINT	#0

(15) 0x4116e0 CMP	W20, W18

(15) 0x4116e4 B.GE	411828

(15) 0x4116e8 SBFM	X1, X15, #0, #31

(15) 0x4116ec ADD	X17, X0, X1

(15) 0x4116f0 ADD	X2, X1, X30

(15) 0x4116f4 UBFM	X13, X17, #61, #60

(15) 0x4116f8 UBFM	X1, X2, #61, #60

(15) 0x4116fc SUB	X17, X13, X2,LSL #3

(15) 0x411700 TBZ	W17, #3, 411768

(15) 0x411704 LDR	D26, [X7, X1]

(15) 0x411708 LDR	D31, [X6, X1]

(15) 0x41170c LDR	D28, [X4, X1]

(15) 0x411710 LDR	D30, [X5, X1]

(15) 0x411714 FADD	D29, D26, D31

(15) 0x411718 LDR	D25, [X8, X1]

(15) 0x41171c LDR	D21, [X9, X1]

(15) 0x411720 FADD	D22, D28, D30

(15) 0x411724 LDR	D20, [X10, X1]

(15) 0x411728 FADD	D0, D29, D24

(15) 0x41172c FMUL	D1, D31, D25

(15) 0x411730 LDR	D2, [X3, X1]

(15) 0x411734 LDR	D23, [X12, X1]

(15) 0x411738 FMUL	D3, D30, D20

(15) 0x41173c FMADD	D4, D26, D21, D1

(15) 0x411740 FADD	D5, D0, D22

(15) 0x411744 FMADD	D6, D28, D23, D3

(15) 0x411748 FNMSUB	D7, D5, D2, D4

(15) 0x41174c FSUB	D16, D7, S6

(15) 0x411750 STR	D16, [X11, X1]

(15) 0x411754 LDR	D17, [X3, X1]

(15) 0x411758 ADD	X1, X1, #8

(15) 0x41175c FMADD	D27, D16, D17, D27

(15) 0x411760 CMP	X13, X1

(15) 0x411764 B.EQ	411828

  (16) 0x411768 LDR	D18, [X7, X1]

  (16) 0x41176c ADD	X2, X1, #8

  (16) 0x411770 LDR	D30, [X6, X1]

  (16) 0x411774 LDR	D26, [X4, X1]

  (16) 0x411778 LDR	D29, [X5, X1]

  (16) 0x41177c FADD	D28, D18, D30

  (16) 0x411780 LDR	D31, [X8, X1]

  (16) 0x411784 LDR	D25, [X9, X1]

  (16) 0x411788 FADD	D21, D26, D29

  (16) 0x41178c LDR	D19, [X10, X1]

  (16) 0x411790 FADD	D20, D28, D24

  (16) 0x411794 FMUL	D0, D30, D31

  (16) 0x411798 LDR	D1, [X3, X1]

  (16) 0x41179c LDR	D22, [X12, X1]

  (16) 0x4117a0 FMUL	D2, D29, D19

  (16) 0x4117a4 FMADD	D23, D18, D25, D0

  (16) 0x4117a8 FADD	D3, D20, D21

  (16) 0x4117ac FMADD	D4, D26, D22, D2

  (16) 0x4117b0 FNMSUB	D5, D3, D1, D23

  (16) 0x4117b4 FSUB	D6, D5, S4

  (16) 0x4117b8 STR	D6, [X11, X1]

  (16) 0x4117bc LDR	D7, [X7, X2]

  (16) 0x4117c0 LDR	D16, [X6, X2]

  (16) 0x4117c4 LDR	D17, [X4, X2]

  (16) 0x4117c8 LDR	D18, [X5, X2]

  (16) 0x4117cc FADD	D30, D7, D16

  (16) 0x4117d0 LDR	D26, [X8, X2]

  (16) 0x4117d4 LDR	D31, [X9, X2]

  (16) 0x4117d8 FADD	D25, D17, D18

  (16) 0x4117dc LDR	D29, [X10, X2]

  (16) 0x4117e0 FADD	D28, D30, D24

  (16) 0x4117e4 FMUL	D19, D16, D26

  (16) 0x4117e8 LDR	D1, [X3, X1]

  (16) 0x4117ec ADD	X1, X1, #16

  (16) 0x4117f0 LDR	D20, [X3, X2]

  (16) 0x4117f4 LDR	D21, [X12, X2]

  (16) 0x4117f8 FMUL	D0, D18, D29

  (16) 0x4117fc FMADD	D22, D7, D31, D19

  (16) 0x411800 FADD	D2, D28, D25

  (16) 0x411804 FMADD	D3, D6, D1, D27

  (16) 0x411808 FMADD	D23, D17, D21, D0

  (16) 0x41180c FNMSUB	D27, D2, D20, D22

  (16) 0x411810 FSUB	D4, D27, S23

  (16) 0x411814 STR	D4, [X11, X2]

  (16) 0x411818 LDR	D5, [X3, X2]

  (16) 0x41181c FMADD	D27, D4, D5, D3

  (16) 0x411820 CMP	X13, X1

  (16) 0x411824 B.NE	411768

(15) 0x411828 ADD	W14, W14, #1

(15) 0x41182c ADD	W15, W15, W16

(15) 0x411830 CMP	W21, W14

(15) 0x411834 B.GT	4116e0

0x411838 ADD	X19, X19, #32

0x41183c LDR	X1, [X19]

(14) 0x411840 FMOV	D24, X1

(14) 0x411844 ORR	X20, XZR, X1

(14) 0x411848 FADD	D6, D27, D24

(14) 0x41184c FMOV	X30, D6

(14) 0x411850 CAS	X20, X30, [X19]

(14) 0x411854 CMP	X1, X20

(14) 0x411858 B.NE	411878

0x41185c LDR	X21, [SP, #32]

0x411860 LDP	X19, X20, [SP, #16]

0x411864 LDP	X29, X30, [SP], #48

0x411868 RET

0x41186c ADD	W2, W2, #1

0x411870 MOVZ	W3, #0

0x411874 B	411680

(14) 0x411878 ORR	X1, XZR, X20

(14) 0x41187c B	411840

Coverage (%)	Name	Source Location	Module
►98.43+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.56+	GOMP_parallel		libgomp.so.1.0.0
○	run_cg_calc_w(Chunk*, Settings[...]	cg.cpp:83	exec
○	cg_main_step_driver(Chunk*, Se[...]	cg_driver.cpp:57	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:18	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:51	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:179	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	basic_string.h:809	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run gcc_5

Source file and lines	cg.cpp:83-90
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83-90.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 7.50 cycles (1.67x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 9 bytes.

General properties

nb instructions	49
nb uops	48
loop length	196
used w registers	14
used x registers	21
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	7.75	7.75	7.75	7.75	0.50	0.50	0.50	0.50	4.17	3.83	4.00	1.50	1.50
cycles	3.00	3.00	7.75	7.75	7.75	7.75	0.50	0.50	0.50	0.50	4.17	3.83	4.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	6.00
Dispatch	7.75
DIV/SQRT	5.00-12.50
Overall L1	7.75-12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	27%
load	29%
store	41%
mul	12%
add-sub	19%
fma	12%
other	35%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	27%
load	29%
store	41%
mul	12%
add-sub	19%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	34%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.72 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 411640

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W20, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410100 <@plt_start@+0xe0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410110 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X19, #44]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR W14, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W0, W1, W20,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W2, W0, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W3, W2, W21, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W14, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 41186c <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W4, W2, W14, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOVI D27, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD W5, W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 411838 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W16, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W21, W20, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W14, W20, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X3, X11, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
FMOV D24, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SBFM X30, X20, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
LDP X6, X5, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
SUB W17, W16, W20,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X13, X16, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SUB W18, W16, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W15, W14, W16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
ADD X12, X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X10, X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X17, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X7, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X5, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
ADD X19, X19, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 411680 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run gcc_5

Source file and lines	cg.cpp:83-90
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83-90.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 7.50 cycles (1.67x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 9 bytes.

General properties

nb instructions	49
nb uops	48
loop length	196
used w registers	14
used x registers	21
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	7.75	7.75	7.75	7.75	0.50	0.50	0.50	0.50	4.17	3.83	4.00	1.50	1.50
cycles	3.00	3.00	7.75	7.75	7.75	7.75	0.50	0.50	0.50	0.50	4.17	3.83	4.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	6.00
Dispatch	7.75
DIV/SQRT	5.00-12.50
Overall L1	7.75-12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	27%
load	29%
store	41%
mul	12%
add-sub	19%
fma	12%
other	35%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	27%
load	29%
store	41%
mul	12%
add-sub	19%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	34%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.72 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 411640

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W20, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410100 <@plt_start@+0xe0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410110 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X19, #44]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR W14, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W0, W1, W20,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W2, W0, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W3, W2, W21, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W14, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 41186c <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W4, W2, W14, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOVI D27, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD W5, W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 411838 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W16, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W21, W20, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W14, W20, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X3, X11, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
FMOV D24, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SBFM X30, X20, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
LDP X6, X5, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
SUB W17, W16, W20,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X13, X16, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SUB W18, W16, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W15, W14, W16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
ADD X12, X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X10, X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X17, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X7, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X5, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
ADD X19, X19, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 411680 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼cg_calc_w(int, int, int, double, double const, double, double const, double const*) [clone ._omp_fn.0]–	32.74	87.23
▼Loop 15 - cg.cpp:86-90 - exec–	0.08	0.22
○Loop 16 - cg.cpp:86-90 - exec	32.63	86.91
○Loop 14 - cg.cpp:83-83 - exec	0.01	0.04

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code