OV - exec - Function update_left(int, int, int, int, double*, bool) [clone ._omp

	Function: update_left(int, int, int, int, double*, bool) [clone ._omp_fn.0]	Module: exec	Source: local_halos.cpp:10-15	Coverage (incl. loops): 0.04% \| (excl. loops): 0.01%

/home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp: 10 - 15

--------------------------------------------------------------------------------

10:   #pragma omp parallel for

11: #endif

12:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

13:     for (int kk = 0; kk < depth; ++kk) {

14:       int base = jj * x;

15:       buffer[base + (halo_depth - kk - 1)] = buffer[base + (halo_depth + kk)];

0x4164c0 STP	X29, X30, [SP, #976]!

0x4164c4 ADD	X29, SP, #0

0x4164c8 STP	X19, X20, [SP, #16]

0x4164cc ORR	X20, XZR, X0

0x4164d0 STR	X21, [SP, #32]

0x4164d4 LDR	W21, [X0, #16]

0x4164d8 BL	410100

0x4164dc ORR	W19, WZR, W0

0x4164e0 BL	410110

0x4164e4 LDR	W1, [X20, #12]

0x4164e8 ORR	W5, WZR, W0

0x4164ec SUB	W0, W1, W21,LSL #1

0x4164f0 SDIV	W2, W0, W19

0x4164f4 MSUB	W3, W2, W19, W0

0x4164f8 CMP	W5, W3

0x4164fc B.LT	4166d4

0x416500 MADD	W4, W2, W5, W3

0x416504 ADD	W6, W2, W4

0x416508 CMP	W4, W6

0x41650c B.GE	4166c4

0x416510 LDR	W7, [X20, #20]

0x416514 ADD	W5, W21, W4

0x416518 ADD	W14, W21, W6

0x41651c LDR	X8, [X20]

0x416520 LDR	W15, [X20, #8]

0x416524 CMP	W7, #0

0x416528 B.LE	4166c4

0x41652c MUL	W9, W15, W5

0x416530 SBFM	X10, X21, #0, #31

0x416534 SBFM	X11, X7, #0, #31

0x416538 ADD	X12, X10, X11

0x41653c SUB	X13, XZR, X11,LSL #3

0x416540 UBFM	X18, X8, #63, #62

0x416544 SBFM	X16, X15, #60, #31

0x416548 SBFM	X30, X15, #61, #31

0x41654c SBFM	X17, X9, #0, #31

0x416550 ADD	X20, X12, X17

0x416554 ADD	X21, X10, X17

0x416558 ADD	X4, X8, X20,LSL #3

0x41655c UBFM	X6, X21, #60, #59

(57) 0x416560 SUB	X19, XZR, X13

(57) 0x416564 ADD	X0, X4, X13

(57) 0x416568 SUB	X1, X19, #8

(57) 0x41656c SUB	X2, X6, #8

(57) 0x416570 UBFM	X3, X1, #3, #63

(57) 0x416574 ADD	X15, X3, #1

(57) 0x416578 ANDS	X7, X15, #0x7

(57) 0x41657c B.EQ	416628

(57) 0x416580 CMP	X7, #1

(57) 0x416584 B.EQ	416610

(57) 0x416588 CMP	X7, #2

(57) 0x41658c B.EQ	416600

(57) 0x416590 CMP	X7, #3

(57) 0x416594 B.EQ	4165f0

(57) 0x416598 CMP	X7, #4

(57) 0x41659c B.EQ	4165e0

(57) 0x4165a0 CMP	X7, #5

(57) 0x4165a4 B.EQ	4165d0

(57) 0x4165a8 CMP	X7, #6

(57) 0x4165ac B.EQ	4165c0

(57) 0x4165b0 LDR	D31, [X4, X13]

(57) 0x4165b4 SUB	X8, X2, X0

(57) 0x4165b8 ADD	X0, X0, #8

(57) 0x4165bc STR	D31, [X8, X18]

(57) 0x4165c0 LDR	D0, [X0]

(57) 0x4165c4 SUB	X9, X2, X0

(57) 0x4165c8 ADD	X0, X0, #8

(57) 0x4165cc STR	D0, [X9, X18]

(57) 0x4165d0 LDR	D1, [X0]

(57) 0x4165d4 SUB	X10, X2, X0

(57) 0x4165d8 ADD	X0, X0, #8

(57) 0x4165dc STR	D1, [X10, X18]

(57) 0x4165e0 LDR	D2, [X0]

(57) 0x4165e4 SUB	X11, X2, X0

(57) 0x4165e8 ADD	X0, X0, #8

(57) 0x4165ec STR	D2, [X11, X18]

(57) 0x4165f0 LDR	D3, [X0]

(57) 0x4165f4 SUB	X12, X2, X0

(57) 0x4165f8 ADD	X0, X0, #8

(57) 0x4165fc STR	D3, [X12, X18]

(57) 0x416600 LDR	D4, [X0]

(57) 0x416604 SUB	X17, X2, X0

(57) 0x416608 ADD	X0, X0, #8

(57) 0x41660c STR	D4, [X17, X18]

(57) 0x416610 LDR	D5, [X0]

(57) 0x416614 SUB	X20, X2, X0

(57) 0x416618 ADD	X0, X0, #8

(57) 0x41661c STR	D5, [X20, X18]

(57) 0x416620 CMP	X4, X0

(57) 0x416624 B.EQ	4166b0

  (56) 0x416628 LDR	D6, [X0]

  (56) 0x41662c SUB	X21, X2, X0

  (56) 0x416630 ADD	X19, X0, #8

  (56) 0x416634 SUB	X3, X2, X19

  (56) 0x416638 ADD	X1, X0, #16

  (56) 0x41663c SUB	X15, X2, X1

  (56) 0x416640 ADD	X7, X0, #24

  (56) 0x416644 SUB	X10, X2, X7

  (56) 0x416648 ADD	X8, X0, #32

  (56) 0x41664c SUB	X9, X2, X8

  (56) 0x416650 ADD	X11, X0, #40

  (56) 0x416654 SUB	X12, X2, X11

  (56) 0x416658 ADD	X17, X0, #48

  (56) 0x41665c STR	D6, [X21, X18]

  (56) 0x416660 SUB	X20, X2, X17

  (56) 0x416664 ADD	X21, X0, #56

  (56) 0x416668 LDR	D7, [X0, #8]

  (56) 0x41666c SUB	X19, X2, X21

  (56) 0x416670 ADD	X0, X0, #64

  (56) 0x416674 STR	D7, [X3, X18]

  (56) 0x416678 LDUR	D16, [X0, #464]

  (56) 0x41667c STR	D16, [X15, X18]

  (56) 0x416680 LDUR	D17, [X0, #472]

  (56) 0x416684 STR	D17, [X10, X18]

  (56) 0x416688 LDUR	D18, [X0, #480]

  (56) 0x41668c STR	D18, [X9, X18]

  (56) 0x416690 LDUR	D19, [X0, #488]

  (56) 0x416694 STR	D19, [X12, X18]

  (56) 0x416698 LDUR	D20, [X0, #496]

  (56) 0x41669c STR	D20, [X20, X18]

  (56) 0x4166a0 LDUR	D21, [X0, #504]

  (56) 0x4166a4 STR	D21, [X19, X18]

  (56) 0x4166a8 CMP	X4, X0

  (56) 0x4166ac B.NE	416628

(57) 0x4166b0 ADD	W5, W5, #1

(57) 0x4166b4 ADD	X6, X6, X16

(57) 0x4166b8 ADD	X4, X4, X30

(57) 0x4166bc CMP	W14, W5

(57) 0x4166c0 B.GT	416560

0x4166c4 LDR	X21, [SP, #32]

0x4166c8 LDP	X19, X20, [SP, #16]

0x4166cc LDP	X29, X30, [SP], #48

0x4166d0 RET

0x4166d4 ADD	W2, W2, #1

0x4166d8 MOVZ	W3, #0

0x4166dc B	416500

Coverage (%)	Name	Module
►96.75+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6
►2.17+	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_5

Source file and lines	local_halos.cpp:10-15
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:10-15.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 32% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 7.75 cycles (1.61x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:10
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:10

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes.

General properties

nb instructions	47
nb uops	47
loop length	188
used w registers	14
used x registers	20
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.88 cycles
front end	5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50
cycles	3.50	3.50	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	5.88
Dispatch	8.00
DIV/SQRT	5.00-12.50
Overall L1	8.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	32%
load	21%
store	41%
mul	12%
add-sub	20%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	48%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (0.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4164c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
BL 410100 <@plt_start@+0xe0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410110 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X20, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR W5, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W0, W1, W21,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SDIV W2, W0, W19	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W3, W2, W19, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W5, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 4166d4 <_Z11update_leftiiiiPdb._omp_fn.0+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W4, W2, W5, W3	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W6, W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 4166c4 <_Z11update_leftiiiiPdb._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W7, [X20, #20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W5, W21, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W14, W21, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W15, [X20, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 4166c4 <_Z11update_leftiiiiPdb._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W9, W15, W5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
SBFM X10, X21, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
SBFM X11, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
ADD X12, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X13, XZR, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X18, X8, #63, #62	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SBFM X16, X15, #60, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
SBFM X30, X15, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
SBFM X17, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
ADD X20, X12, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X21, X10, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X8, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X6, X21, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
B 416500 <_Z11update_leftiiiiPdb._omp_fn.0+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_5

Source file and lines	local_halos.cpp:10-15
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:10-15.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 32% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 7.75 cycles (1.61x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:10
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:10

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes.

General properties

nb instructions	47
nb uops	47
loop length	188
used w registers	14
used x registers	20
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.88 cycles
front end	5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50
cycles	3.50	3.50	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	5.88
Dispatch	8.00
DIV/SQRT	5.00-12.50
Overall L1	8.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	32%
load	21%
store	41%
mul	12%
add-sub	20%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	48%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (0.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4164c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
BL 410100 <@plt_start@+0xe0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410110 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X20, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR W5, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W0, W1, W21,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SDIV W2, W0, W19	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W3, W2, W19, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W5, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 4166d4 <_Z11update_leftiiiiPdb._omp_fn.0+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W4, W2, W5, W3	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W6, W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 4166c4 <_Z11update_leftiiiiPdb._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W7, [X20, #20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W5, W21, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W14, W21, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W15, [X20, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 4166c4 <_Z11update_leftiiiiPdb._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W9, W15, W5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
SBFM X10, X21, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
SBFM X11, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
ADD X12, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X13, XZR, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X18, X8, #63, #62	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SBFM X16, X15, #60, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
SBFM X30, X15, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
SBFM X17, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
ADD X20, X12, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X21, X10, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X8, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X6, X21, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
B 416500 <_Z11update_leftiiiiPdb._omp_fn.0+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼update_left(int, int, int, int, double*, bool) [clone ._omp_fn.0]–	0.04	0.12
▼Loop 57 - local_halos.cpp:13-15 - exec–	0.04	0.10
○Loop 56 - local_halos.cpp:13-15 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code