OV - exec - Loop 18

	Loop Id: 18	Module: exec	Source: cg.cpp:108-113	Coverage: 0.03%

0x411900 CMP	W20, W14

0x411904 B.GE	411a6c

0x411908 SBFM	X6, X11, #0, #31

0x41190c ADD	X9, X17, X6

0x411910 ADD	X21, X6, X15

0x411914 UBFM	X0, X9, #61, #60

0x411918 UBFM	X1, X21, #61, #60

0x41191c SUB	X2, X0, X21,LSL #3

0x411920 SUB	X3, X2, #8

0x411924 UBFM	X4, X3, #3, #63

0x411928 ADD	X5, X4, #1

0x41192c ANDS	X13, X5, #0x3

0x411930 B.EQ	4119c4

0x411934 CMP	X13, #1

0x411938 B.EQ	411994

0x41193c CMP	X13, #2

0x411940 B.EQ	41196c

0x411944 LDR	D28, [X8, X1]

0x411948 LDR	D29, [X18, X1]

0x41194c FMADD	D0, D30, D28, D29

0x411950 STR	D0, [X18, X1]

0x411954 LDR	D1, [X7, X1]

0x411958 LDR	D2, [X30, X1]

0x41195c FMSUB	D3, D30, D1, D2

0x411960 FMADD	D31, D3, D3, D31

0x411964 STR	D3, [X30, X1]

0x411968 ADD	X1, X1, #8

0x41196c LDR	D4, [X8, X1]

0x411970 LDR	D5, [X18, X1]

0x411974 FMADD	D6, D30, D4, D5

0x411978 STR	D6, [X18, X1]

0x41197c LDR	D7, [X7, X1]

0x411980 LDR	D16, [X30, X1]

0x411984 FMSUB	D17, D30, D7, D16

0x411988 FMADD	D31, D17, D17, D31

0x41198c STR	D17, [X30, X1]

0x411990 ADD	X1, X1, #8

0x411994 LDR	D18, [X8, X1]

0x411998 LDR	D19, [X18, X1]

0x41199c FMADD	D20, D30, D18, D19

0x4119a0 STR	D20, [X18, X1]

0x4119a4 LDR	D21, [X7, X1]

0x4119a8 LDR	D22, [X30, X1]

0x4119ac FMSUB	D23, D30, D21, D22

0x4119b0 FMADD	D31, D23, D23, D31

0x4119b4 STR	D23, [X30, X1]

0x4119b8 ADD	X1, X1, #8

0x4119bc CMP	X0, X1

0x4119c0 B.EQ	411a6c

  (19) 0x4119c4 LDR	D24, [X8, X1]

  (19) 0x4119c8 ADD	X9, X1, #8

  (19) 0x4119cc ADD	X6, X1, #16

  (19) 0x4119d0 ADD	X21, X1, #24

  (19) 0x4119d4 LDR	D25, [X18, X1]

  (19) 0x4119d8 FMADD	D26, D30, D24, D25

  (19) 0x4119dc STR	D26, [X18, X1]

  (19) 0x4119e0 LDR	D27, [X7, X1]

  (19) 0x4119e4 LDR	D28, [X30, X1]

  (19) 0x4119e8 FMSUB	D29, D30, D27, D28

  (19) 0x4119ec FMADD	D0, D29, D29, D31

  (19) 0x4119f0 STR	D29, [X30, X1]

  (19) 0x4119f4 ADD	X1, X1, #32

  (19) 0x4119f8 LDR	D1, [X8, X9]

  (19) 0x4119fc LDR	D2, [X18, X9]

  (19) 0x411a00 FMADD	D3, D30, D1, D2

  (19) 0x411a04 STR	D3, [X18, X9]

  (19) 0x411a08 LDR	D4, [X7, X9]

  (19) 0x411a0c LDR	D5, [X30, X9]

  (19) 0x411a10 FMSUB	D6, D30, D4, D5

  (19) 0x411a14 FMADD	D7, D6, D6, D0

  (19) 0x411a18 STR	D6, [X30, X9]

  (19) 0x411a1c LDR	D16, [X8, X6]

  (19) 0x411a20 LDR	D17, [X18, X6]

  (19) 0x411a24 FMADD	D18, D30, D16, D17

  (19) 0x411a28 STR	D18, [X18, X6]

  (19) 0x411a2c LDR	D19, [X7, X6]

  (19) 0x411a30 LDR	D20, [X30, X6]

  (19) 0x411a34 FMSUB	D21, D30, D19, D20

  (19) 0x411a38 FMADD	D22, D21, D21, D7

  (19) 0x411a3c STR	D21, [X30, X6]

  (19) 0x411a40 LDR	D31, [X18, X21]

  (19) 0x411a44 LDR	D23, [X8, X21]

  (19) 0x411a48 FMADD	D24, D30, D23, D31

  (19) 0x411a4c STR	D24, [X18, X21]

  (19) 0x411a50 LDR	D25, [X7, X21]

  (19) 0x411a54 LDR	D26, [X30, X21]

  (19) 0x411a58 FMSUB	D27, D30, D25, D26

  (19) 0x411a5c FMADD	D31, D27, D27, D22

  (19) 0x411a60 STR	D27, [X30, X21]

  (19) 0x411a64 CMP	X0, X1

  (19) 0x411a68 B.NE	4119c4

0x411a6c ADD	W10, W10, #1

0x411a70 ADD	W11, W11, W12

0x411a74 CMP	W16, W10

0x411a78 B.GT	411900

/home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 108 - 113

--------------------------------------------------------------------------------

108:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

109:       const int index = kk + jj * x;

110:

111:       u[index] += alpha * p[index];

112:       r[index] -= alpha * w[index];

113:       rrn_temp += r[index] * r[index];

Coverage (%)	Name	Source Location	Module
►98.41+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.59+	GOMP_parallel		libgomp.so.1.0.0
○	run_cg_calc_ur(Chunk*, Setting[...]	cg.cpp:105	exec
○	cg_main_step_driver(Chunk*, Se[...]	cg_driver.cpp:69	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:18	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:51	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:179	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	basic_string.h:809	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.10
CQA speedup if FP arith vectorized	1.10
CQA speedup if fully vectorized	2.21
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	cg_calc_ur(int, int, int, double, double, double, double const, double, double const*) [clone ._omp_fn.0]
Source	cg.cpp:108-108,cg.cpp:111-113
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.63
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	3.00
Front-end cycles	6.63
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	5.00
P5 cycles	5.00
P6 cycles	3.75
P7 cycles	3.75
P8 cycles	3.75
P9 cycles	3.75
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	6.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	53.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	2.72
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	9.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	26.22
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.92
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	32.81

Metric	Value
CQA speedup if no scalar integer	1.10
CQA speedup if FP arith vectorized	1.10
CQA speedup if fully vectorized	2.21
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	cg_calc_ur(int, int, int, double, double, double, double const, double, double const*) [clone ._omp_fn.0]
Source	cg.cpp:108-108,cg.cpp:111-113
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.63
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	3.00
Front-end cycles	6.63
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	5.00
P5 cycles	5.00
P6 cycles	3.75
P7 cycles	3.75
P8 cycles	3.75
P9 cycles	3.75
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	6.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	53.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	2.72
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	9.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	26.22
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.92
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	32.81

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	cg_calc_ur(int, int, int, double, double, double, double const, double, double const*) [clone ._omp_fn.0]
Source file and lines	cg.cpp:108-113
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:108-113.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:108,111-113.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.63 to 6.00 cycles (1.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 26% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.63 to 3.00 cycles (2.21x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 9 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 18 FP arithmetical operations:

9: addition or subtraction (all inside FMA instructions)
9: multiply (all inside FMA instructions)

The binary loop does not load or store any data.

General properties

nb instructions	53
nb uops	53
loop length	212
used w registers	6
used x registers	17
used b registers	0
used h registers	0
used s registers	0
used d registers	20
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.63 cycles
front end	6.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	5.00	5.00	5.00	5.00	3.75	3.75	3.75	3.75	6.00	6.00	6.00	0.00	0.00
cycles	3.00	3.00	5.00	5.00	5.00	5.00	3.75	3.75	3.75	3.75	6.00	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.63
Dispatch	6.00
Overall L1	6.63

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	26%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
other	32%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	26%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.63 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.63 to 6.00 cycles (1.10x speedup).

ASM code

In the binary file, the address of the loop is: 411900

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
CMP W20, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 411a6c <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X6, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD X9, X17, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X21, X6, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X0, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X1, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X2, X0, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X4, X3, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X13, X5, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4119c4 <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 411994 <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41196c <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D28, [X8, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D29, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D0, D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D0, [X18, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D1, [X7, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D2, [X30, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMSUB D3, D30, D1, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMADD D31, D3, D3, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D3, [X30, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X8, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D5, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D6, D30, D4, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D6, [X18, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D7, [X7, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D16, [X30, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMSUB D17, D30, D7, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMADD D31, D17, D17, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D17, [X30, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X8, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D19, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D20, D30, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D20, [X18, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D21, [X7, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D22, [X30, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMSUB D23, D30, D21, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMADD D31, D23, D23, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D23, [X30, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 411a6c <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W10, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W11, W11, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W16, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 411900 <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	cg_calc_ur(int, int, int, double, double, double, double const, double, double const*) [clone ._omp_fn.0]
Source file and lines	cg.cpp:108-113
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.63 to 6.00 cycles (1.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 9 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 18 FP arithmetical operations:

9: addition or subtraction (all inside FMA instructions)
9: multiply (all inside FMA instructions)

The binary loop does not load or store any data.

General properties

nb instructions	53
nb uops	53
loop length	212
used w registers	6
used x registers	17
used b registers	0
used h registers	0
used s registers	0
used d registers	20
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.63 cycles
front end	6.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	5.00	5.00	5.00	5.00	3.75	3.75	3.75	3.75	6.00	6.00	6.00	0.00	0.00
cycles	3.00	3.00	5.00	5.00	5.00	5.00	3.75	3.75	3.75	3.75	6.00	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.63
Dispatch	6.00
Overall L1	6.63

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	26%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
other	32%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	26%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.63 cycles.

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 411900

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
CMP W20, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 411a6c <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X6, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD X9, X17, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X21, X6, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X0, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X1, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X2, X0, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X4, X3, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X13, X5, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4119c4 <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 411994 <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41196c <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D28, [X8, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D29, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D0, D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D0, [X18, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D1, [X7, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D2, [X30, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMSUB D3, D30, D1, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMADD D31, D3, D3, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D3, [X30, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X8, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D5, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D6, D30, D4, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D6, [X18, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D7, [X7, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D16, [X30, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMSUB D17, D30, D7, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMADD D31, D17, D17, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D17, [X30, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X8, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D19, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D20, D30, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D20, [X18, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D21, [X7, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D22, [X30, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMSUB D23, D30, D21, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMADD D31, D23, D23, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D23, [X30, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 411a6c <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W10, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W11, W11, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W16, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 411900 <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code