OV - exec - Loop 59

	Loop Id: 59	Module: exec	Source: local_halos.cpp:28-30	Coverage: 0.02%

0x41678c SUB	X2, XZR, X13

0x416790 ADD	X0, X4, X13

0x416794 SUB	X6, X2, #8

0x416798 SUB	X16, X12, #8

0x41679c UBFM	X7, X6, #3, #63

0x4167a0 ADD	X8, X7, #1

0x4167a4 ANDS	X9, X8, #0x7

0x4167a8 B.EQ	41683c

0x4167ac CMP	X9, #1

0x4167b0 B.EQ	416828

0x4167b4 CMP	X9, #2

0x4167b8 B.EQ	41681c

0x4167bc CMP	X9, #3

0x4167c0 B.EQ	416810

0x4167c4 CMP	X9, #4

0x4167c8 B.EQ	416804

0x4167cc CMP	X9, #5

0x4167d0 B.EQ	4167f8

0x4167d4 CMP	X9, #6

0x4167d8 B.EQ	4167ec

0x4167dc SUB	X10, X16, X0

0x4167e0 ADD	X0, X0, #8

0x4167e4 LDR	D31, [X10, X3]

0x4167e8 STR	D31, [X4, X13]

0x4167ec SUB	X11, X16, X0

0x4167f0 LDR	D0, [X11, X3]

0x4167f4 STR	D0, [X0], #8

0x4167f8 SUB	X17, X16, X0

0x4167fc LDR	D1, [X17, X3]

0x416800 STR	D1, [X0], #8

0x416804 SUB	X15, X16, X0

0x416808 LDR	D2, [X15, X3]

0x41680c STR	D2, [X0], #8

0x416810 SUB	X30, X16, X0

0x416814 LDR	D3, [X30, X3]

0x416818 STR	D3, [X0], #8

0x41681c SUB	X21, X16, X0

0x416820 LDR	D4, [X21, X3]

0x416824 STR	D4, [X0], #8

0x416828 SUB	X19, X16, X0

0x41682c LDR	D5, [X19, X3]

0x416830 STR	D5, [X0], #8

0x416834 CMP	X0, X4

0x416838 B.EQ	4168c4

  (58) 0x41683c SUB	X2, X16, X0

  (58) 0x416840 ORR	X1, XZR, X0

  (58) 0x416844 ADD	X6, X0, #24

  (58) 0x416848 ADD	X7, X0, #32

  (58) 0x41684c LDR	D6, [X2, X3]

  (58) 0x416850 SUB	X10, X16, X6

  (58) 0x416854 SUB	X9, X16, X7

  (58) 0x416858 ADD	X8, X0, #40

  (58) 0x41685c ADD	X11, X0, #48

  (58) 0x416860 SUB	X17, X16, X8

  (58) 0x416864 SUB	X30, X16, X11

  (58) 0x416868 ADD	X15, X0, #56

  (58) 0x41686c ADD	X0, X0, #64

  (58) 0x416870 SUB	X21, X16, X15

  (58) 0x416874 STR	D6, [X1], #8

  (58) 0x416878 SUB	X19, X16, X1

  (58) 0x41687c ADD	X2, X1, #8

  (58) 0x416880 SUB	X6, X16, X2

  (58) 0x416884 LDR	D7, [X19, X3]

  (58) 0x416888 STUR	D7, [X0, #456]

  (58) 0x41688c LDR	D16, [X6, X3]

  (58) 0x416890 STR	D16, [X1, #8]

  (58) 0x416894 LDR	D17, [X10, X3]

  (58) 0x416898 STUR	D17, [X0, #472]

  (58) 0x41689c LDR	D18, [X9, X3]

  (58) 0x4168a0 STUR	D18, [X0, #480]

  (58) 0x4168a4 LDR	D19, [X17, X3]

  (58) 0x4168a8 STUR	D19, [X0, #488]

  (58) 0x4168ac LDR	D20, [X30, X3]

  (58) 0x4168b0 STUR	D20, [X0, #496]

  (58) 0x4168b4 LDR	D21, [X21, X3]

  (58) 0x4168b8 STUR	D21, [X0, #504]

  (58) 0x4168bc CMP	X0, X4

  (58) 0x4168c0 B.NE	41683c

0x4168c4 ADD	W5, W5, #1

0x4168c8 ADD	X12, X12, X18

0x4168cc ADD	X4, X4, X20

0x4168d0 CMP	W14, W5

0x4168d4 B.GT	41678c

/home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp: 28 - 30

--------------------------------------------------------------------------------

28:     for (int kk = 0; kk < depth; ++kk) {

29:       int base = jj * x;

30:       buffer[base + (x - halo_depth + kk)] = buffer[base + (x - halo_depth - 1 - kk)];

Coverage (%)	Name	Source Location	Module
►97.83+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.08+	GOMP_parallel		libgomp.so.1.0.0
○	update_face(int, int, int, int[...]	local_halos.cpp:25	exec
○	run_local_halos(Chunk*, Settin[...]	local_halos.cpp:94	exec
○	halo_update_driver(Chunk*, Set[...]	halo_update_driver.cpp:12	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:15	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:51	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:179	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	basic_string.h:809	exec
►1.08+	GOMP_parallel		libgomp.so.1.0.0
○	update_face(int, int, int, int[...]	local_halos.cpp:25	exec
○	run_local_halos(Chunk*, Settin[...]	local_halos.cpp:103	exec
○	halo_update_driver(Chunk*, Set[...]	halo_update_driver.cpp:12	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:15	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:51	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:179	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	basic_string.h:809	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.34
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P2, P3, P4, P5,
Function	update_right(int, int, int, int, double*, bool) [clone ._omp_fn.0]
Source	local_halos.cpp:28-30
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.50
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	6.50
CQA cycles if fully vectorized	1.63
Front-end cycles	6.13
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	6.50
P3 cycles	6.50
P4 cycles	6.50
P5 cycles	6.50
P6 cycles	3.50
P7 cycles	3.50
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	4.83
P11 cycles	4.50
P12 cycles	4.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	49.00
Nb loads	NA
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.34
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P2, P3, P4, P5,
Function	update_right(int, int, int, int, double*, bool) [clone ._omp_fn.0]
Source	local_halos.cpp:28-30
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.50
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	6.50
CQA cycles if fully vectorized	1.63
Front-end cycles	6.13
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	6.50
P3 cycles	6.50
P4 cycles	6.50
P5 cycles	6.50
P6 cycles	3.50
P7 cycles	3.50
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	4.83
P11 cycles	4.50
P12 cycles	4.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	49.00
Nb loads	NA
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	update_right(int, int, int, int, double*, bool) [clone ._omp_fn.0]
Source file and lines	local_halos.cpp:28-30
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:28-30.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=15
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 15 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 4.83 cycles (1.34x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.50 to 1.62 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	49
nb uops	49
loop length	196
used w registers	2
used x registers	21
used b registers	0
used h registers	0
used s registers	0
used d registers	7
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.13 cycles
front end	6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	6.50	6.50	6.50	6.50	3.50	3.50	0.00	0.00	4.83	4.50	4.67	0.00	0.00
cycles	4.50	4.50	6.50	6.50	6.50	6.50	3.50	3.50	0.00	0.00	4.83	4.50	4.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.13
Dispatch	6.50
Overall L1	6.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41678c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
SUB X2, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X4, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X6, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X16, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X7, X6, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X9, X8, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41683c <_Z12update_rightiiiiPdb._omp_fn.0+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 416828 <_Z12update_rightiiiiPdb._omp_fn.0+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41681c <_Z12update_rightiiiiPdb._omp_fn.0+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 416810 <_Z12update_rightiiiiPdb._omp_fn.0+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 416804 <_Z12update_rightiiiiPdb._omp_fn.0+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4167f8 <_Z12update_rightiiiiPdb._omp_fn.0+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4167ec <_Z12update_rightiiiiPdb._omp_fn.0+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X10, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D31, [X10, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D31, [X4, X13]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
SUB X11, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D0, [X11, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D0, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
SUB X17, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D1, [X17, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D1, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
SUB X15, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D2, [X15, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D2, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
SUB X30, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D3, [X30, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D3, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
SUB X21, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D4, [X21, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D4, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
SUB X19, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D5, [X19, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D5, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
CMP X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4168c4 <_Z12update_rightiiiiPdb._omp_fn.0+0x1e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X12, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X4, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W14, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.GT 41678c <_Z12update_rightiiiiPdb._omp_fn.0+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	update_right(int, int, int, int, double*, bool) [clone ._omp_fn.0]
Source file and lines	local_halos.cpp:28-30
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:28-30.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=15
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 4.83 cycles (1.34x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.50 to 1.62 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	49
nb uops	49
loop length	196
used w registers	2
used x registers	21
used b registers	0
used h registers	0
used s registers	0
used d registers	7
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.13 cycles
front end	6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	6.50	6.50	6.50	6.50	3.50	3.50	0.00	0.00	4.83	4.50	4.67	0.00	0.00
cycles	4.50	4.50	6.50	6.50	6.50	6.50	3.50	3.50	0.00	0.00	4.83	4.50	4.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.13
Dispatch	6.50
Overall L1	6.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41678c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
SUB X2, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X4, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X6, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X16, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X7, X6, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X9, X8, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41683c <_Z12update_rightiiiiPdb._omp_fn.0+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 416828 <_Z12update_rightiiiiPdb._omp_fn.0+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41681c <_Z12update_rightiiiiPdb._omp_fn.0+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 416810 <_Z12update_rightiiiiPdb._omp_fn.0+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 416804 <_Z12update_rightiiiiPdb._omp_fn.0+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4167f8 <_Z12update_rightiiiiPdb._omp_fn.0+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4167ec <_Z12update_rightiiiiPdb._omp_fn.0+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X10, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D31, [X10, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D31, [X4, X13]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
SUB X11, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D0, [X11, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D0, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
SUB X17, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D1, [X17, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D1, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
SUB X15, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D2, [X15, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D2, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
SUB X30, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D3, [X30, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D3, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
SUB X21, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D4, [X21, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D4, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
SUB X19, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D5, [X19, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D5, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
CMP X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4168c4 <_Z12update_rightiiiiPdb._omp_fn.0+0x1e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X12, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X4, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W14, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.GT 41678c <_Z12update_rightiiiiPdb._omp_fn.0+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code