OV - exec - Function cg_init(int, int, int, int, double, double, double*, double const*, double const*, double*, double*, double*, double*, double*, double*) [clone .omp

	Function: cg_init(int, int, int, int, double, double, double, double const, double const, double ...	Module: exec	Source: cg.cpp:44-50	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 44 - 50

--------------------------------------------------------------------------------

44:   #pragma omp parallel for

45: #endif

46:   for (int jj = halo_depth; jj < y - 1; ++jj) {

47:     for (int kk = halo_depth; kk < x - 1; ++kk) {

48:       const int index = kk + jj * x;

49:       kx[index] = rx * (w[index - 1] + w[index]) / (2.0 * w[index - 1] * w[index]);

50:       ky[index] = ry * (w[index - x] + w[index]) / (2.0 * w[index - x] * w[index]);

0x410ac0 SUB	SP, SP, #128

0x410ac4 STP	X29, X30, [SP, #32]

0x410ac8 STP	X28, X27, [SP, #48]

0x410acc STP	X26, X25, [SP, #64]

0x410ad0 STP	X24, X23, [SP, #80]

0x410ad4 STP	X22, X21, [SP, #96]

0x410ad8 STP	X20, X19, [SP, #112]

0x410adc ADD	X29, SP, #32

0x410ae0 LDR	W8, [X2]

0x410ae4 LDR	W21, [X3]

0x410ae8 SUB	W8, W8, #1

0x410aec CMP	W21, W8

0x410af0 B.GE	410e04

0x410af4 ORN	W9, WZR, W21

0x410af8 LDR	W1, [X0]

0x410afc ORR	X19, XZR, X6

0x410b00 ORR	X25, XZR, X4

0x410b04 ORR	X24, XZR, X3

0x410b08 ORR	X22, XZR, X5

0x410b0c ORR	X23, XZR, X7

0x410b10 MOVZ	W10, #1

0x410b14 ADD	W20, W8, W9

0x410b18 ADRP	X0,

0x410b1c ADD	X0, X0, #928

0x410b20 ADD	X3, SP, #16

0x410b24 SUB	X4, X29, #4

0x410b28 SUB	X5, X29, #8

0x410b2c SUB	X6, X29, #12

0x410b30 MOVZ	W2, #34

0x410b34 MOVZ	W7, #1

0x410b38 STUR	W10, [X29, #500]

0x410b3c STP	W20, WZR, [X29, #504]

0x410b40 STR	WZR, [SP, #16]

0x410b44 STR	W1, [SP, #8]

0x410b48 STR	W10, [SP]

0x410b4c BL	410120

0x410b50 LDP	W8, W9, [X29, #504]

0x410b54 CMP	W8, W20

0x410b58 CSEL	W8, W8, W20, #3

0x410b5c ADD	W10, W8, #1

0x410b60 STUR	W8, [X29, #504]

0x410b64 CMP	W9, W10

0x410b68 B.CS	410df4

0x410b6c LDRSW	X10, [X25]

0x410b70 LDRSW	X11, [X24]

0x410b74 SUB	W12, W10, #1

0x410b78 CMP	W11, W12

0x410b7c B.GE	410df4

0x410b80 LDP	X18, X13, [X29, #96]

0x410b84 ADD	W16, W9, W21

0x410b88 LDR	X14, [X23]

0x410b8c ORN	X0, XZR, X11

0x410b90 MUL	W23, W10, W16

0x410b94 LDR	X15, [X22]

0x410b98 SUB	X17, X11, X10

0x410b9c ADD	X5, X0, X10

0x410ba0 LDR	X18, [X18]

0x410ba4 MOVN	X0, #1

0x410ba8 ORR	W12, WZR, WZR

0x410bac BIC	X6, X0, X17

0x410bb0 STR	W16, [SP, #12]

0x410bb4 B	410bcc

(10) 0x410bb8 CMP	W9, W8

(10) 0x410bbc ADD	W9, W9, #1

(10) 0x410bc0 ADD	W12, W12, #1

(10) 0x410bc4 ADD	W23, W22, W10

(10) 0x410bc8 B.EQ	410df4

(10) 0x410bcc SBFM	X22, X23, #0, #31

(10) 0x410bd0 CMP	X5, #6

(10) 0x410bd4 ORR	X25, XZR, X11

(10) 0x410bd8 B.CS	410c68

(10) 0x410bdc SBFM	X16, X23, #61, #31

(10) 0x410be0 ADD	X17, X25, X22

(10) 0x410be4 SUB	X0, XZR, X10

(10) 0x410be8 ADD	X0, X17, X0

(10) 0x410bec UBFM	X17, X17, #61, #60

(10) 0x410bf0 ORR	X24, XZR, XZR

(10) 0x410bf4 ADD	X16, X16, X25,LSL #3

(10) 0x410bf8 ADD	X23, X14, X0,LSL #3

(10) 0x410bfc SUB	X0, X10, #1

(10) 0x410c00 SUB	X25, X0, X25

(10) 0x410c04 ADD	X27, X15, X17

(10) 0x410c08 ADD	X28, X18, X17

(10) 0x410c0c ADD	X26, X14, X16

  (9) 0x410c10 ADD	X16, X26, X24

  (9) 0x410c14 LDR	D3, [X19]

  (9) 0x410c18 SUBS	X25, X25, #1

  (9) 0x410c1c LDP	D0, D1, [X16, #1016]

  (9) 0x410c20 FADD	D2, D0, D1

  (9) 0x410c24 FADD	D0, D0, D0

  (9) 0x410c28 FMUL	D2, D3, D2

  (9) 0x410c2c FMUL	D0, D0, D1

  (9) 0x410c30 FDIV	D0, D2, D0

  (9) 0x410c34 STR	D0, [X27, X24]

  (9) 0x410c38 LDR	D0, [X23, X24]

  (9) 0x410c3c LDR	D1, [X16]

  (9) 0x410c40 LDR	D3, [X13]

  (9) 0x410c44 FADD	D2, D0, D1

  (9) 0x410c48 FADD	D0, D0, D0

  (9) 0x410c4c FMUL	D2, D3, D2

  (9) 0x410c50 FMUL	D0, D0, D1

  (9) 0x410c54 FDIV	D0, D2, D0

  (9) 0x410c58 STR	D0, [X28, X24]

  (9) 0x410c5c ADD	X24, X24, #8

  (9) 0x410c60 B.NE	410c10

(10) 0x410c64 B	410bb8

(10) 0x410c68 LDR	W16, [SP, #12]

(10) 0x410c6c SUB	X17, X14, #8

(10) 0x410c70 ADD	X27, X19, #8

(10) 0x410c74 ADD	X2, X13, #8

(10) 0x410c78 ADD	W0, W16, W12

(10) 0x410c7c SUB	X16, X11, X10

(10) 0x410c80 MUL	W0, W10, W0

(10) 0x410c84 SBFM	X4, X0, #0, #31

(10) 0x410c88 ADD	X25, X17, W0,SXTW #3

(10) 0x410c8c ADD	X20, X11, X4

(10) 0x410c90 ADD	X24, X10, X4

(10) 0x410c94 ADD	X0, X16, X4

(10) 0x410c98 UBFM	X20, X20, #61, #60

(10) 0x410c9c UBFM	X24, X24, #61, #60

(10) 0x410ca0 SUB	X16, X15, #8

(10) 0x410ca4 ADD	X26, X14, X0,LSL #3

(10) 0x410ca8 ADD	X1, X15, X20

(10) 0x410cac ADD	X7, X16, X24

(10) 0x410cb0 ADD	X21, X17, X24

(10) 0x410cb4 CMP	X1, X27

(10) 0x410cb8 ADD	X17, X17, X20

(10) 0x410cbc ADD	X3, X18, X20

(10) 0x410cc0 CCMP	X19, X7, #2, #3

(10) 0x410cc4 SUB	X16, X18, #8

(10) 0x410cc8 CSINC	W28, WZR, WZR, #2

(10) 0x410ccc CMP	X1, X25

(10) 0x410cd0 ADD	X16, X16, X24

(10) 0x410cd4 CCMP	X26, X7, #2, #3

(10) 0x410cd8 CSINC	W4, WZR, WZR, #2

(10) 0x410cdc CMP	X1, X21

(10) 0x410ce0 CCMP	X17, X7, #2, #3

(10) 0x410ce4 CSINC	W30, WZR, WZR, #2

(10) 0x410ce8 CMP	X1, X2

(10) 0x410cec CCMP	X13, X7, #2, #3

(10) 0x410cf0 CSINC	W20, WZR, WZR, #2

(10) 0x410cf4 CMP	X3, X27

(10) 0x410cf8 CCMP	X19, X16, #2, #3

(10) 0x410cfc CSINC	W0, WZR, WZR, #2

(10) 0x410d00 CMP	X3, X25

(10) 0x410d04 ORR	X25, XZR, X11

(10) 0x410d08 CCMP	X26, X16, #2, #3

(10) 0x410d0c CSINC	W27, WZR, WZR, #2

(10) 0x410d10 CMP	X3, X21

(10) 0x410d14 CCMP	X17, X16, #2, #3

(10) 0x410d18 CSINC	W26, WZR, WZR, #2

(10) 0x410d1c CMP	X3, X2

(10) 0x410d20 CCMP	X13, X16, #2, #3

(10) 0x410d24 CSINC	W24, WZR, WZR, #2

(10) 0x410d28 CMP	X3, X7

(10) 0x410d2c CCMP	X1, X16, #2, #3

(10) 0x410d30 B.CC	410bdc

(10) 0x410d34 ORR	X25, XZR, X11

(10) 0x410d38 TBNZ	W28, #0, 410bdc

(10) 0x410d3c ORR	X25, XZR, X11

(10) 0x410d40 TBNZ	W4, #0, 410bdc

(10) 0x410d44 ORR	X25, XZR, X11

(10) 0x410d48 TBNZ	W30, #0, 410bdc

(10) 0x410d4c ORR	X25, XZR, X11

(10) 0x410d50 TBNZ	W20, #0, 410bdc

(10) 0x410d54 ORR	X25, XZR, X11

(10) 0x410d58 TBNZ	W0, #0, 410bdc

(10) 0x410d5c ORR	X25, XZR, X11

(10) 0x410d60 TBNZ	W27, #0, 410bdc

(10) 0x410d64 ORR	X25, XZR, X11

(10) 0x410d68 TBNZ	W26, #0, 410bdc

(10) 0x410d6c ORR	X25, XZR, X11

(10) 0x410d70 TBNZ	W24, #0, 410bdc

(10) 0x410d74 ADD	X16, X11, X22

(10) 0x410d78 SUB	X17, X11, X10

(10) 0x410d7c LDR	D0, [X13]

(10) 0x410d80 UBFM	X16, X16, #61, #60

(10) 0x410d84 ADD	X17, X17, X22

(10) 0x410d88 LDR	D1, [X19]

(10) 0x410d8c ADD	X24, X14, X17,LSL #3

(10) 0x410d90 ORR	X28, XZR, X6

(10) 0x410d94 ADD	X25, X14, X16

(10) 0x410d98 ADD	X26, X15, X16

(10) 0x410d9c ADD	X27, X18, X16

  (11) 0x410da0 LDUR	Q2, [X25, #504]

  (11) 0x410da4 LDR	Q3, [X25], #16

  (11) 0x410da8 SUBS	X28, X28, #2

  (11) 0x410dac FADD	V4.2D, V2.2D, V3.2D

  (11) 0x410db0 FADD	V2.2D, V2.2D, V2.2D

  (11) 0x410db4 FMUL	V4.2D, V4.2D, V1.D[0]

  (11) 0x410db8 FMUL	V2.2D, V2.2D, V3.2D

  (11) 0x410dbc FDIV	V2.2D, V4.2D, V2.2D

  (11) 0x410dc0 LDR	Q4, [X24], #16

  (11) 0x410dc4 FADD	V5.2D, V4.2D, V3.2D

  (11) 0x410dc8 FADD	V4.2D, V4.2D, V4.2D

  (11) 0x410dcc FMUL	V3.2D, V4.2D, V3.2D

  (11) 0x410dd0 FMUL	V4.2D, V5.2D, V0.D[0]

  (11) 0x410dd4 FDIV	V3.2D, V4.2D, V3.2D

  (11) 0x410dd8 STR	Q2, [X26], #16

  (11) 0x410ddc STR	Q3, [X27], #16

  (11) 0x410de0 B.NE	410da0

(10) 0x410de4 CMP	X5, X6

(10) 0x410de8 ADD	X25, X6, X11

(10) 0x410dec B.EQ	410bb8

(10) 0x410df0 B	410bdc

0x410df4 LDR	W1, [SP, #8]

0x410df8 ADRP	X0,

0x410dfc ADD	X0, X0, #952

0x410e00 BL	410040

0x410e04 LDP	X20, X19, [SP, #112]

0x410e08 LDP	X22, X21, [SP, #96]

0x410e0c LDP	X24, X23, [SP, #80]

0x410e10 LDP	X26, X25, [SP, #64]

0x410e14 LDP	X28, X27, [SP, #48]

0x410e18 LDP	X29, X30, [SP, #32]

0x410e1c ADD	SP, SP, #128

0x410e20 RET

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	cg_init(int, int, int, int, do[...]	cg.cpp:44	exec
○	run_cg_init(Chunk*, Settings&,[...]	cg.cpp:142	exec
○	cg_init_driver(Chunk*, Setting[...]	cg_driver.cpp:30	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:15	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:45	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:169	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

Coverage (%)	Name	Source Location	Module
►52.24+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►47.76+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	cg_init(int, int, int, int, do[...]	cg.cpp:44	exec
○	run_cg_init(Chunk*, Settings&,[...]	cg.cpp:142	exec
○	cg_init_driver(Chunk*, Setting[...]	cg_driver.cpp:30	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:15	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:45	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:169	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

Coverage (%)	Name	Source Location	Module
►71.83+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►28.17+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	cg_init(int, int, int, int, do[...]	cg.cpp:44	exec
○	run_cg_init(Chunk*, Settings&,[...]	cg.cpp:142	exec
○	cg_init_driver(Chunk*, Setting[...]	cg_driver.cpp:30	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:15	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:45	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:169	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

Coverage (%)	Name	Module
►100.00+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

Coverage (%)	Name	Module
►100.00+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

Coverage (%)	Name	Module
►100.00+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

Coverage (%)	Name	Source Location	Module
►78.79+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►21.21+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	cg_init(int, int, int, int, do[...]	cg.cpp:44	exec
○	run_cg_init(Chunk*, Settings&,[...]	cg.cpp:142	exec
○	cg_init_driver(Chunk*, Setting[...]	cg_driver.cpp:30	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:15	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:45	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:169	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	cg.cpp:44-50
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:44-50.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 10.17 to 2.42 cycles (4.21x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:44
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:44

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 18 bytes. The binary function is storing 18 bytes.

General properties

nb instructions	74
nb uops	74
loop length	296
used w registers	13
used x registers	27
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.25 cycles
front end	9.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	9.75	9.75	9.75	9.75	0.00	0.00	0.00	0.00	10.17	9.83	10.00	6.50	6.50
cycles	3.50	3.50	9.75	9.75	9.75	9.75	0.00	0.00	0.00	0.00	10.17	9.83	10.00	6.50	6.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.25
Dispatch	10.17
Overall L1	10.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	22%
load	22%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.17 cycles. At this rate:

1% of peak load performance is reached (1.77 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.77 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 410ac0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W21, [X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 410e04 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.4+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORN W9, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W1, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X19, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X25, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W20, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <43fb18>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #928	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STUR W10, [X29, #500]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STP W20, WZR, [X29, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W1, [SP, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W10, [SP]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W8, W8, W20, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STUR W8, [X29, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 410df4 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.4+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X10, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDRSW X11, [X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W12, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W11, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 410df4 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.4+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X18, X13, [X29, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W16, W9, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X14, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORN X0, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MUL W23, W10, W16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
LDR X15, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X17, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X18, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR W12, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BIC X6, X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W16, [SP, #12]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 410bcc <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.4+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <43fdf8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #952	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	cg.cpp:44-50
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:44-50.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:44
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:44

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 18 bytes. The binary function is storing 18 bytes.

General properties

nb instructions	74
nb uops	74
loop length	296
used w registers	13
used x registers	27
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.25 cycles
front end	9.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	9.75	9.75	9.75	9.75	0.00	0.00	0.00	0.00	10.17	9.83	10.00	6.50	6.50
cycles	3.50	3.50	9.75	9.75	9.75	9.75	0.00	0.00	0.00	0.00	10.17	9.83	10.00	6.50	6.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.25
Dispatch	10.17
Overall L1	10.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	22%
load	22%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.17 cycles. At this rate:

1% of peak load performance is reached (1.77 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.77 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 410ac0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W21, [X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 410e04 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.4+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORN W9, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W1, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X19, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X25, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W20, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <43fb18>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #928	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STUR W10, [X29, #500]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STP W20, WZR, [X29, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W1, [SP, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W10, [SP]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W8, W8, W20, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STUR W8, [X29, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 410df4 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.4+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X10, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDRSW X11, [X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W12, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W11, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 410df4 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.4+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X18, X13, [X29, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W16, W9, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X14, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORN X0, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MUL W23, W10, W16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
LDR X15, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X17, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X18, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR W12, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BIC X6, X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W16, [SP, #12]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 410bcc <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.4+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <43fdf8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #952	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
1	0	0.96	0	0.9	0	1.78	0					9.14	0	0.34	0.01					1.94	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.32000002264977	0.012304064817727
1x2	2	0.96	1.91	2	0.17499999701977	0.012772771529853
1x4	4	0.9	3.61	4	0.10000000149012	0.013202549889684
1x8	4	1.78	14.22	8	0.044999998062849	0.0054708370007575
1x16
1x24
1x32	1	9.14	292.57	32	0.034999996423721	0.00038343126652762
1x40	30	0.34	13.62	40	0.035000000149012	0.0086259720847011
1x48
1x56
1x64	5	1.94	124.11	64	0.035000000149012	0.00096281542209908

Name	Coverage (%)	Time (s)
▼cg_init(int, int, int, int, double, double, double, double const, double const, double, double, double, double, double, double*) [clone .omp_outlined.4]–	0.01	0.32
▼Loop 10 - cg.cpp:44-50 - exec–	0.00	0.00
○Loop 11 - cg.cpp:47-50 - exec	0.01	0.32
○Loop 9 - cg.cpp:47-50 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency