OV - exec - Function update_bottom(int, int, int, int, double*, bool) [clone .omp

	Function: update_bottom(int, int, int, int, double*, bool) [clone .omp_outlined]	Module: exec	Source: local_halos.cpp:58-62	Coverage (incl. loops): NA% \| (excl. loops): NA%

/home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp: 58 - 62

--------------------------------------------------------------------------------

58:   #pragma omp parallel for

59: #endif

60:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

61:       int base = kk;

62:       buffer[base + (halo_depth - jj - 1) * x] = buffer[base + (halo_depth + jj) * x];

0x415d20 SUB	SP, SP, #96

0x415d24 STP	X29, X30, [SP, #16]

0x415d28 STR	X25, [SP, #32]

0x415d2c STP	X24, X23, [SP, #48]

0x415d30 STP	X22, X21, [SP, #64]

0x415d34 STP	X20, X19, [SP, #80]

0x415d38 ADD	X29, SP, #16

0x415d3c LDR	W24, [X3]

0x415d40 LDR	W8, [X2]

0x415d44 SUB	W8, W8, W24

0x415d48 CMP	W24, W8

0x415d4c B.GE	415e34

0x415d50 LDR	W19, [X0]

0x415d54 ORN	W9, WZR, W24

0x415d58 ORR	X21, XZR, X5

0x415d5c ORR	X20, XZR, X4

0x415d60 ORR	X23, XZR, X3

0x415d64 ORR	X22, XZR, X2

0x415d68 MOVZ	W10, #1

0x415d6c ADD	W25, W8, W9

0x415d70 ADRP	X0,

0x415d74 ADD	X0, X0, #2176

0x415d78 ADD	X3, SP, #8

0x415d7c ADD	X4, X29, #28

0x415d80 ADD	X5, X29, #24

0x415d84 SUB	X6, X29, #4

0x415d88 ORR	W1, WZR, W19

0x415d8c MOVZ	W2, #34

0x415d90 MOVZ	W7, #1

0x415d94 STUR	W10, [X29, #508]

0x415d98 STP	W25, WZR, [X29, #24]

0x415d9c STR	WZR, [SP, #8]

0x415da0 STR	W10, [SP]

0x415da4 BL	410120

0x415da8 LDP	W8, W9, [X29, #24]

0x415dac CMP	W8, W25

0x415db0 CSEL	W10, W8, W25, #3

0x415db4 ADD	W8, W10, #1

0x415db8 STR	W10, [X29, #24]

0x415dbc CMP	W9, W8

0x415dc0 B.CS	415e24

0x415dc4 LDR	W11, [X21]

0x415dc8 LDR	W8, [X23]

0x415dcc SUB	W16, W10, W9

0x415dd0 LDR	W12, [X22]

0x415dd4 ORN	W14, WZR, W11

0x415dd8 ADD	W13, W11, W8

0x415ddc ADD	W8, W8, W14

0x415de0 MUL	W11, W13, W12

0x415de4 ADD	W13, W16, #1

0x415de8 MUL	W12, W8, W12

0x415dec LDR	X8, [X20]

0x415df0 CMP	W13, #18

0x415df4 B.CS	415e50

0x415df8 SUB	W10, W10, W9

0x415dfc ADD	W13, W9, W24

0x415e00 ADD	W9, W10, #1

0x415e04 ADD	W10, W13, W12

0x415e08 ADD	W11, W13, W11

(78) 0x415e0c LDR	D0, [X8, W11,SXTW #3]

(78) 0x415e10 SUBS	W9, W9, #1

(78) 0x415e14 ADD	W11, W11, #1

(78) 0x415e18 STR	D0, [X8, W10,SXTW #3]

(78) 0x415e1c ADD	W10, W10, #1

(78) 0x415e20 B.NE	415e0c

0x415e24 ADRP	X0,

0x415e28 ADD	X0, X0, #2200

0x415e2c ORR	W1, WZR, W19

0x415e30 BL	410040

0x415e34 LDP	X20, X19, [SP, #80]

0x415e38 LDR	X25, [SP, #32]

0x415e3c LDP	X22, X21, [SP, #64]

0x415e40 LDP	X24, X23, [SP, #48]

0x415e44 LDP	X29, X30, [SP, #16]

0x415e48 ADD	SP, SP, #96

0x415e4c RET

0x415e50 ADD	W15, W9, W24

0x415e54 ADD	W14, W15, W12

0x415e58 ADD	W17, W14, W16

0x415e5c CMP	W17, W14

0x415e60 B.LT	415df8

0x415e64 ADD	W15, W15, W11

0x415e68 ADD	W16, W15, W16

0x415e6c CMP	W16, W15

0x415e70 B.LT	415df8

0x415e74 ADD	W16, W9, W24

0x415e78 ADD	W17, W16, W12

0x415e7c ADD	W16, W16, W11

0x415e80 SBFM	X17, X17, #0, #31

0x415e84 SUB	X16, X17, W16,SXTW

0x415e88 ANDS	XZR, X16, #0x1ffffffc

0x415e8c B.EQ	415df8

0x415e90 AND	W16, W13, #0xfffffffc

0x415e94 AND	W17, W13, #0xfffffffc

0x415e98 ADD	W9, W9, W16

(79) 0x415e9c ADD	X18, X8, W15,SXTW #3

(79) 0x415ea0 ADD	X0, X8, W14,SXTW #3

(79) 0x415ea4 SUBS	W17, W17, #4

(79) 0x415ea8 ADD	W15, W15, #4

(79) 0x415eac ADD	W14, W14, #4

(79) 0x415eb0 LDP	Q0, Q1, [X18]

(79) 0x415eb4 STP	Q0, Q1, [X0]

(79) 0x415eb8 B.NE	415e9c

0x415ebc CMP	W13, W16

0x415ec0 B.NE	415df8

0x415ec4 B	415e24

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	local_halos.cpp:58-62
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:58-62.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 15.00 to 8.12 cycles (1.85x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:58
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:58

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 18 bytes. The binary function is storing 12 bytes.

General properties

nb instructions	92
nb uops	92
loop length	368
used w registers	17
used x registers	19
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.50 cycles
front end	11.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	15.00	15.00	15.00	15.00	0.00	0.00	0.00	0.00	7.67	7.67	7.67	5.00	5.00
cycles	5.50	5.50	15.00	15.00	15.00	15.00	0.00	0.00	0.00	0.00	7.67	7.67	7.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.50
Dispatch	15.00
Overall L1	15.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	18%
load	16%
store	30%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 415d20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR W24, [X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W8, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W8, W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W24, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 415e34 <_Z13update_bottomiiiiPdb.omp_outlined+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORN W9, WZR, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W25, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <43fd70>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STUR W10, [X29, #508]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STP W25, WZR, [X29, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W10, [SP]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W10, W8, W25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W8, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STR W10, [X29, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 415e24 <_Z13update_bottomiiiiPdb.omp_outlined+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W11, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W8, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W16, W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR W12, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORN W14, WZR, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W13, W11, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W8, W8, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W11, W13, W12	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W13, W16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MUL W12, W8, W12	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
LDR X8, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W13, #18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 415e50 <_Z13update_bottomiiiiPdb.omp_outlined+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W10, W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W13, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W9, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W10, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W11, W13, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <43fe24>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2200	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X25, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W15, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W14, W15, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W17, W14, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W17, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 415df8 <_Z13update_bottomiiiiPdb.omp_outlined+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W15, W15, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W16, W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W16, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 415df8 <_Z13update_bottomiiiiPdb.omp_outlined+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W16, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W17, W16, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W16, W16, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SBFM X17, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
SUB X16, X17, W16,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ANDS XZR, X16, #0x1ffffffc	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 415df8 <_Z13update_bottomiiiiPdb.omp_outlined+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND W16, W13, #0xfffffffc	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
AND W17, W13, #0xfffffffc	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W9, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W13, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 415df8 <_Z13update_bottomiiiiPdb.omp_outlined+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 415e24 <_Z13update_bottomiiiiPdb.omp_outlined+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	local_halos.cpp:58-62
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:58-62.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:58
- /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:58

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 18 bytes. The binary function is storing 12 bytes.

General properties

nb instructions	92
nb uops	92
loop length	368
used w registers	17
used x registers	19
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.50 cycles
front end	11.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	15.00	15.00	15.00	15.00	0.00	0.00	0.00	0.00	7.67	7.67	7.67	5.00	5.00
cycles	5.50	5.50	15.00	15.00	15.00	15.00	0.00	0.00	0.00	0.00	7.67	7.67	7.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.50
Dispatch	15.00
Overall L1	15.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	18%
load	16%
store	30%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 415d20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR W24, [X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W8, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W8, W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W24, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 415e34 <_Z13update_bottomiiiiPdb.omp_outlined+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORN W9, WZR, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W25, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <43fd70>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STUR W10, [X29, #508]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STP W25, WZR, [X29, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W10, [SP]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W10, W8, W25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W8, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STR W10, [X29, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 415e24 <_Z13update_bottomiiiiPdb.omp_outlined+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W11, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W8, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W16, W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR W12, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORN W14, WZR, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W13, W11, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W8, W8, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W11, W13, W12	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W13, W16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MUL W12, W8, W12	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
LDR X8, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W13, #18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 415e50 <_Z13update_bottomiiiiPdb.omp_outlined+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W10, W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W13, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W9, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W10, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W11, W13, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <43fe24>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2200	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X25, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W15, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W14, W15, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W17, W14, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W17, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 415df8 <_Z13update_bottomiiiiPdb.omp_outlined+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W15, W15, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W16, W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W16, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 415df8 <_Z13update_bottomiiiiPdb.omp_outlined+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W16, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W17, W16, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W16, W16, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SBFM X17, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
SUB X16, X17, W16,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ANDS XZR, X16, #0x1ffffffc	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 415df8 <_Z13update_bottomiiiiPdb.omp_outlined+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND W16, W13, #0xfffffffc	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
AND W17, W13, #0xfffffffc	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W9, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W13, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 415df8 <_Z13update_bottomiiiiPdb.omp_outlined+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 415e24 <_Z13update_bottomiiiiPdb.omp_outlined+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-237-4322/intel/TeaLeaf/run/oneview_runs/multicore/armclang/oneview_run_1782430622OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
				1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1
1x2
1x4	3	1	1	4	0.099999994039536	0.010041376575828
1x8	6	1	1	8	0.079999998211861	0.011549545451999
1x16	12	1	1	16	0.074999995529652	0.010370809584856
1x24	20	1	1	24	0.075000002980232	0.014121467247605
1x32	24	1	1	32	0.065000005066395	0.011722041293979
1x40	24	1	1	40	0.15500000119209	0.015370749868453
1x48	34	1	1	48	0.064999997615814	0.010325725190341
1x56	41	1	1	56	0.070000000298023	0.011485483497381
1x64	37	1	1	64	0.080000005662441	0.0092780403792858

Name	Coverage (%)	Time (s)
▼update_bottom(int, int, int, int, double*, bool) [clone .omp_outlined]–	0.00	0.00
○Loop 78 - local_halos.cpp:60-62 - exec	0.00	0.00
○Loop 79 - local_halos.cpp:60-62 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency