OV - exec - Function std::enable_if<all_of<camp::concepts::metalib::negate_t<RAJA::internal::loop_data_has_reducers<camp::type::cv::rem_s<camp::type::ref::rem_s<RAJA::internal::LoopData<camp::tuple<RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Moment, long, Kripke::Moment*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Direction, long, Kripke::Direction*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Group, long, Kripke::Group*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Zone, long, Kripke::Zone*>, long> >, camp::tuple<>, camp::resources::v1::Host, LTimesSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field<double, Kripke::Direction, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Moment, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Moment, Kripke::Direction>&) const::{lambda(Kripke::Moment, Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&>::type>::type> > >::value, void>::type RAJA::internal::StatementExecutor<RAJA::statement::Collapse<RAJA::omp_parallel_collapse_exec, camp::int_seq<long, 0l, 2l>, RAJA::statement::For<1l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > >, RAJA::internal::LoopTypes<camp::list<void, void, void, void>, camp::list<void, void, void, void> > >::exec<RAJA::internal::LoopData<camp::tuple<RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Moment, long, Kripke::Moment*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Direction, long, Kripke::Direction*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Group, long, Kripke::Group*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Zone, long, Kripke::Zone*>, long> >, camp::tuple<>, camp::resources::v1::Host, LTimesSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field<double, Kripke::Direction, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Moment, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Moment, Kripke::Direction>&) const::{lambda(Kripke::Moment, Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData<camp::tuple<RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Moment, long, Kripke::Moment*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Direction, long, Kripke::Direction*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Group, long, Kripke::Group*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Zone, long, Kripke::Zone*>, long> >, camp::tuple<>, camp::resources::v1::Host, LTimesSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field<double, Kripke::Direction, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Moment, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Moment, Kripke::Direction>&) const::{lambda(Kripke::Moment, Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&) [clone .omp

	Function: std::enable_if<all_of<camp::concepts::metalib::negate_t<RAJA::internal::loop_data_has_redu ...	Module: exec	Source: Collapse.hpp:129-133 [...]	Coverage (incl. loops): 9.02% \| (excl. loops): 0.01%

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp: 142 - 142

--------------------------------------------------------------------------------

142:     for (decltype(distance_it) i = 0; i < distance_it; ++i)

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 129 - 133

--------------------------------------------------------------------------------

129: #pragma omp parallel for private(i0, i1) firstprivate(privatizer)              \

130:     RAJA_COLLAPSE(2)

131:     for (i0 = 0; i0 < l0; ++i0)

132:     {

133:       for (i1 = 0; i1 < l1; ++i1)

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp: 62 - 62

--------------------------------------------------------------------------------

62:            phi(nm,g,z) += ell(nm, d) * psi(d, g, z);

0x44dd00 SUB	SP, SP, #336

0x44dd04 STP	X29, X30, [SP, #240]

0x44dd08 STP	X28, X27, [SP, #256]

0x44dd0c STP	X26, X25, [SP, #272]

0x44dd10 STP	X24, X23, [SP, #288]

0x44dd14 STP	X22, X21, [SP, #304]

0x44dd18 STP	X20, X19, [SP, #320]

0x44dd1c ADD	X29, SP, #240

0x44dd20 LDR	X8, [X2]

0x44dd24 LDR	X26, [X3]

0x44dd28 CMP	X8, #1

0x44dd2c CCMP	X26, #1, #8, #10

0x44dd30 B.LT	44dde8

0x44dd34 LDR	X9, [X4]

0x44dd38 LDR	X11, [X4, #32]

0x44dd3c LDR	W1, [X0]

0x44dd40 MOVZ	W10, #1

0x44dd44 ADRP	X0,

0x44dd48 ADD	X0, X0, #392

0x44dd4c SUB	X3, X29, #36

0x44dd50 SUB	X5, X29, #24

0x44dd54 LDP	X22, X23, [X4, #16]

0x44dd58 LDP	X24, X25, [X4, #48]

0x44dd5c SUB	X6, X29, #32

0x44dd60 MOVZ	W2, #34

0x44dd64 MOVZ	W7, #1

0x44dd68 LDR	X21, [X4, #208]

0x44dd6c LDR	X19, [X4, #248]

0x44dd70 STUR	WZR, [X29, #476]

0x44dd74 STUR	X10, [X29, #480]

0x44dd78 STUR	X9, [X29, #408]

0x44dd7c MOVN	X9, #0

0x44dd80 STUR	X11, [X29, #464]

0x44dd84 LDR	X11, [X4, #72]

0x44dd88 STR	W1, [SP, #20]

0x44dd8c MADD	X20, X26, X8, X9

0x44dd90 LDP	X9, X8, [X4, #104]

0x44dd94 STP	X20, XZR, [X29, #1000]

0x44dd98 STP	X9, X11, [X29, #960]

0x44dd9c STUR	X8, [X29, #440]

0x44dda0 LDR	X9, [X4, #176]

0x44dda4 LDP	X11, X8, [X4, #280]

0x44dda8 SUB	X4, X29, #16

0x44ddac STR	X10, [SP]

0x44ddb0 STP	X11, X9, [X29, #936]

0x44ddb4 STUR	X8, [X29, #416]

0x44ddb8 BL	410150

0x44ddbc LDP	X8, X9, [X29, #1000]

0x44ddc0 CMP	X8, X20

0x44ddc4 CSEL	X8, X8, X20, #11

0x44ddc8 CMP	X9, X8

0x44ddcc STUR	X8, [X29, #488]

0x44ddd0 STUR	X8, [X29, #400]

0x44ddd4 B.LE	44de08

0x44ddd8 LDR	W1, [SP, #20]

0x44dddc ADRP	X0,

0x44dde0 ADD	X0, X0, #416

0x44dde4 BL	410050

0x44dde8 LDP	X20, X19, [SP, #320]

0x44ddec LDP	X22, X21, [SP, #304]

0x44ddf0 LDP	X24, X23, [SP, #288]

0x44ddf4 LDP	X26, X25, [SP, #272]

0x44ddf8 LDP	X28, X27, [SP, #256]

0x44ddfc LDP	X29, X30, [SP, #240]

0x44de00 ADD	SP, SP, #336

0x44de04 RET

0x44de08 SUB	X10, X23, X22

0x44de0c CMP	X10, #1

0x44de10 B.LT	44ddd8

0x44de14 SUB	X11, X25, X24

0x44de18 CMP	X11, #1

0x44de1c B.LT	44ddd8

0x44de20 LDUR	X13, [X29, #456]

0x44de24 LDUR	X18, [X29, #424]

0x44de28 UBFM	X8, X23, #61, #60

0x44de2c MUL	X17, X22, X21

0x44de30 ORN	X16, XZR, X22

0x44de34 CNTW	X0, ALL

0x44de38 SUB	X8, X8, #8

0x44de3c ADD	X16, X23, X16

0x44de40 PTRUE	P0.D, ALL

0x44de44 SUB	X4, X24, X25

0x44de48 ADD	X14, X13, X24,LSL #3

0x44de4c MUL	X12, X22, X18

0x44de50 MUL	X16, X18, X16

0x44de54 UBFM	X27, X18, #61, #60

0x44de58 STP	X14, X26, [SP, #112]

0x44de5c LDUR	X14, [X29, #448]

0x44de60 UBFM	X14, X14, #61, #60

0x44de64 STR	X14, [SP, #104]

0x44de68 LDUR	X14, [X29, #440]

0x44de6c UBFM	X14, X14, #61, #60

0x44de70 STR	X14, [SP, #96]

0x44de74 LDUR	X14, [X29, #416]

0x44de78 UBFM	X15, X14, #61, #60

0x44de7c LDUR	X14, [X29, #432]

0x44de80 ADD	X17, X14, X17,LSL #3

0x44de84 MADD	X8, X21, X8, X14

0x44de88 ADD	X14, X25, X12

0x44de8c STP	X14, X17, [SP, #80]

0x44de90 ADD	X17, X12, X24

0x44de94 ADD	X14, X19, X17,LSL #3

0x44de98 ADD	X8, X8, #8

0x44de9c SUB	X17, XZR, X0

0x44dea0 STP	X8, X14, [SP, #64]

0x44dea4 ADD	X8, X19, X16,LSL #3

0x44dea8 AND	X3, X11, X17

0x44deac STR	X8, [SP, #56]

0x44deb0 LDUR	X8, [X29, #464]

0x44deb4 ADD	X5, X8, X9

0x44deb8 RDVL	X8, #1

0x44debc ADD	X16, X8, X24,LSL #3

0x44dec0 ADD	X8, X19, X8

0x44dec4 ADD	X13, X13, X16

0x44dec8 UBFM	X16, X12, #61, #60

0x44decc ADD	X16, X16, X24,LSL #3

0x44ded0 ADD	X8, X8, X16

0x44ded4 STP	X8, X13, [SP, #40]

0x44ded8 ADD	X8, X19, X16

0x44dedc STR	X8, [SP, #32]

0x44dee0 ADD	X8, X19, X12,LSL #3

0x44dee4 STR	X8, [SP, #24]

0x44dee8 B	44df04

(877) 0x44deec LDUR	X8, [X29, #400]

(877) 0x44def0 LDR	X26, [SP, #120]

(877) 0x44def4 ADD	X5, X5, #1

(877) 0x44def8 CMP	X9, X8

(877) 0x44defc ADD	X9, X9, #1

(877) 0x44df00 B.EQ	44ddd8

(877) 0x44df04 SDIV	X8, X9, X26

(877) 0x44df08 LDUR	X13, [X29, #408]

(877) 0x44df0c LDR	X14, [SP, #80]

(877) 0x44df10 LDR	X28, [SP, #96]

(877) 0x44df14 UBFM	X7, X21, #60, #60

(877) 0x44df18 ORR	X19, XZR, XZR

(877) 0x44df1c MUL	X12, X8, X26

(877) 0x44df20 ADD	X8, X8, X13

(877) 0x44df24 LDUR	X13, [X29, #448]

(877) 0x44df28 LDP	X26, X20, [SP, #104]

(877) 0x44df2c SUB	X16, X9, X12

(877) 0x44df30 SUB	X12, X5, X12

(877) 0x44df34 MADD	X18, X8, X13, X25

(877) 0x44df38 LDUR	X13, [X29, #464]

(877) 0x44df3c MADD	X17, X26, X8, X20

(877) 0x44df40 ADD	X16, X16, X13

(877) 0x44df44 LDUR	X13, [X29, #440]

(877) 0x44df48 MADD	X17, X28, X16, X17

(877) 0x44df4c MADD	X18, X16, X13, X18

(877) 0x44df50 LDR	X13, [SP, #64]

(877) 0x44df54 ADD	X1, X13, X8,LSL #3

(877) 0x44df58 LDUR	X13, [X29, #416]

(877) 0x44df5c CMP	X17, X1

(877) 0x44df60 MADD	X2, X16, X13, X14

(877) 0x44df64 LDUR	X14, [X29, #424]

(877) 0x44df68 LDR	X13, [SP, #88]

(877) 0x44df6c UBFM	X1, X14, #60, #60

(877) 0x44df70 LDUR	X14, [X29, #432]

(877) 0x44df74 ADD	X6, X13, X8,LSL #3

(877) 0x44df78 LDUR	X13, [X29, #456]

(877) 0x44df7c ADD	X23, X14, X8,LSL #3

(877) 0x44df80 LDR	X14, [SP, #56]

(877) 0x44df84 ADD	X18, X13, X18,LSL #3

(877) 0x44df88 CCMP	X6, X18, #2, #3

(877) 0x44df8c CSINC	W6, W7, WZR, #2

(877) 0x44df90 ADD	X2, X14, X2,LSL #3

(877) 0x44df94 LDR	X14, [SP, #72]

(877) 0x44df98 CMP	X17, X2

(877) 0x44df9c MUL	X17, X28, X12

(877) 0x44dfa0 MADD	X17, X26, X8, X17

(877) 0x44dfa4 MUL	X8, X26, X8

(877) 0x44dfa8 MADD	X2, X15, X16, X14

(877) 0x44dfac LDR	X14, [SP, #48]

(877) 0x44dfb0 ADD	X16, X20, X17

(877) 0x44dfb4 MADD	X8, X28, X12, X8

(877) 0x44dfb8 CCMP	X2, X18, #2, #3

(877) 0x44dfbc MUL	X2, X15, X12

(877) 0x44dfc0 CSINC	W18, W1, WZR, #2

(877) 0x44dfc4 ADD	X7, X20, X8

(877) 0x44dfc8 ADD	X17, X14, X17

(877) 0x44dfcc ORR	W18, W6, W18

(877) 0x44dfd0 ADD	X6, X13, X8

(877) 0x44dfd4 LDP	X8, X14, [SP, #24]

(877) 0x44dfd8 ADD	X1, X14, X2

(877) 0x44dfdc LDR	X14, [SP, #40]

(877) 0x44dfe0 MADD	X30, X15, X12, X8

(877) 0x44dfe4 ADD	X2, X14, X2

(877) 0x44dfe8 B	44e004

  (878) 0x44dfec ADD	X19, X19, #1

  (878) 0x44dff0 ADD	X1, X1, X27

  (878) 0x44dff4 ADD	X2, X2, X27

  (878) 0x44dff8 ADD	X30, X30, X27

  (878) 0x44dffc CMP	X19, X10

  (878) 0x44e000 B.EQ	44deec

  (878) 0x44e004 ADD	X12, X19, X22

  (878) 0x44e008 CMP	X11, X0

  (878) 0x44e00c CSINC	W8, WZR, WZR, #2

  (878) 0x44e010 MUL	X28, X12, X21

  (878) 0x44e014 ORR	W8, W8, W18

  (878) 0x44e018 TBZ	W8, #0, 44e024

  (878) 0x44e01c ORR	X8, XZR, XZR

  (878) 0x44e020 B	44e078

  (878) 0x44e024 LDR	D0, [X23, X28,LSL #3]

  (878) 0x44e028 ORR	X8, XZR, XZR

  (878) 0x44e02c DUP	Z0.D, Z0.D[0]

  (878) 0x44e030 HINT	#0

  (878) 0x44e034 HINT	#0

  (878) 0x44e038 HINT	#0

  (878) 0x44e03c HINT	#0

    (876) 0x44e040 LD1D	{Z1.D}, P0/Z, [X1, X8,LSL #3]

    (876) 0x44e044 LD1D	{Z2.D}, P0/Z, [X2, X8,LSL #3]

    (876) 0x44e048 LD1D	{Z3.D}, P0/Z, [X16, X8,LSL #3]

    (876) 0x44e04c FMAD	Z1.D, P0/M, Z0.D, Z3.D

    (876) 0x44e050 LD1D	{Z4.D}, P0/Z, [X17, X8,LSL #3]

    (876) 0x44e054 FMAD	Z2.D, P0/M, Z0.D, Z4.D

    (876) 0x44e058 ST1D	{Z1.D}, P0, [X16, X8,LSL #3]

    (876) 0x44e05c ST1D	{Z2.D}, P0, [X17, X8,LSL #3]

    (876) 0x44e060 ADD	X8, X8, X0

    (876) 0x44e064 CMP	X3, X8

    (876) 0x44e068 B.NE	44e040

  (878) 0x44e06c CMP	X11, X3

  (878) 0x44e070 ORR	X8, XZR, X3

  (878) 0x44e074 B.EQ	44dfec

  (878) 0x44e078 ADD	X26, X24, X8

  (878) 0x44e07c ORR	X20, XZR, X8

  (878) 0x44e080 SUB	W12, W25, W26

  (878) 0x44e084 ANDS	X12, X12, #0x3

  (878) 0x44e088 B.EQ	44e0c0

  (878) 0x44e08c ADD	X26, X6, X26,LSL #3

  (878) 0x44e090 ORR	X20, XZR, X8

  (878) 0x44e094 HINT	#0

  (878) 0x44e098 HINT	#0

  (878) 0x44e09c HINT	#0

    (880) 0x44e0a0 LDR	D0, [X23, X28,LSL #3]

    (880) 0x44e0a4 LDR	D1, [X1, X20,LSL #3]

    (880) 0x44e0a8 LDR	D2, [X26]

    (880) 0x44e0ac ADD	X20, X20, #1

    (880) 0x44e0b0 SUBS	X12, X12, #1

    (880) 0x44e0b4 FMADD	D0, D0, D1, D2

    (880) 0x44e0b8 STR	D0, [X26], #8

    (880) 0x44e0bc B.NE	44e0a0

  (878) 0x44e0c0 ADD	X8, X4, X8

  (878) 0x44e0c4 CMN	X8, #4

  (878) 0x44e0c8 B.HI	44dfec

  (878) 0x44e0cc ADD	X12, X7, X20,LSL #3

  (878) 0x44e0d0 ADD	X26, X4, X20

  (878) 0x44e0d4 ADD	X20, X24, X20

  (878) 0x44e0d8 ORR	X8, XZR, XZR

  (878) 0x44e0dc ADD	X20, X30, X20,LSL #3

    (879) 0x44e0e0 ADD	X13, X20, X8

    (879) 0x44e0e4 ADD	X14, X12, X8

    (879) 0x44e0e8 LDR	D0, [X23, X28,LSL #3]

    (879) 0x44e0ec ADD	X8, X8, #32

    (879) 0x44e0f0 ADDS	X26, X26, #4

    (879) 0x44e0f4 LDR	D1, [X13]

    (879) 0x44e0f8 LDP	D2, D3, [X14]

    (879) 0x44e0fc FMADD	D0, D0, D1, D2

    (879) 0x44e100 STR	D0, [X14]

    (879) 0x44e104 LDR	D0, [X23, X28,LSL #3]

    (879) 0x44e108 LDR	D1, [X13, #8]

    (879) 0x44e10c FMADD	D0, D0, D1, D3

    (879) 0x44e110 LDP	D2, D3, [X14, #16]

    (879) 0x44e114 STR	D0, [X14, #8]

    (879) 0x44e118 LDR	D0, [X23, X28,LSL #3]

    (879) 0x44e11c LDR	D1, [X13, #16]

    (879) 0x44e120 FMADD	D0, D0, D1, D2

    (879) 0x44e124 STR	D0, [X14, #16]

    (879) 0x44e128 LDR	D0, [X23, X28,LSL #3]

    (879) 0x44e12c LDR	D1, [X13, #24]

    (879) 0x44e130 FMADD	D0, D0, D1, D3

    (879) 0x44e134 STR	D0, [X14, #24]

    (879) 0x44e138 B.NE	44e0e0

  (878) 0x44e13c B	44dfec

Coverage (%)	Name	Source Location	Module
►98.42+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.58+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	void Kripke::DispatchHelper<Kr[...]	plugins.hpp:66	exec
○	auto Kripke::dispatch<LTimesSd[...]	ArchLayout.h:206	exec
○	Kripke::Kernel::LTimes(Kripke:[...]	stl_iterator.h:1102	exec
○	Kripke::SteadyStateSolver(Krip[...]	SteadyStateSolver.cpp:62	exec
○	main	kripke.cpp:509	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	LPlusTimes.cpp:0	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run orig_0

Source file and lines	Collapse.hpp:129-133
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129-133
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp:62

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.67 to 3.25 cycles (5.74x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 30% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 18.67 to 9.62 cycles (1.94x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:130

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	123
nb uops	123
loop length	492
used w registers	5
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.38 cycles
front end	15.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	15.25	15.25	15.25	15.25	0.00	0.00	0.00	0.00	18.67	18.67	18.67	14.00	14.00
cycles	4.00	4.00	15.25	15.25	15.25	15.25	0.00	0.00	0.00	0.00	18.67	18.67	18.67	14.00	14.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.38
Dispatch	18.67
Overall L1	18.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	30%
load	31%
store	35%
mul	25%
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.67 cycles. At this rate:

0% of peak load performance is reached (0.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.32 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 44dd00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #272]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #288]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #304]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X8, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X26, #1, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
B.LT 44dde8 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_9DirectionElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK10LTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS25_3ref5rem_sIS1K_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1K_.omp_outlined+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X4]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [X4, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W1, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <4cfd44>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #392	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X3, X29, #36	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X5, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X22, X23, [X4, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X25, [X4, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
SUB X6, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X21, [X4, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X19, [X4, #248]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR WZR, [X29, #476]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STUR X10, [X29, #480]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X9, [X29, #408]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X11, [X29, #464]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [X4, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR W1, [SP, #20]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MADD X20, X26, X8, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X9, X8, [X4, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X20, XZR, [X29, #1000]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X11, [X29, #960]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X4, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X11, X8, [X4, #280]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
SUB X4, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X10, [SP]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X11, X9, [X29, #936]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X8, [X29, #416]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [X29, #1000]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X8, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X8, X20, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 44de08 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_9DirectionElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK10LTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS25_3ref5rem_sIS1K_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1K_.omp_outlined+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <4cfddc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #416	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #304]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #288]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X10, X23, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 44ddd8 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_9DirectionElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK10LTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS25_3ref5rem_sIS1K_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1K_.omp_outlined+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X11, X25, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 44ddd8 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_9DirectionElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK10LTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS25_3ref5rem_sIS1K_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1K_.omp_outlined+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X18, [X29, #424]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X8, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MUL X17, X22, X21	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ORN X16, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CNTW X0, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SUB X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X16, X23, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (100.0%)
SUB X4, X24, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X14, X13, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X12, X22, X18	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
MUL X16, X18, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X27, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X14, X26, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X14, [X29, #448]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X14, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X14, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X14, [X29, #440]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X14, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X14, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X14, [X29, #416]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X15, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDUR X14, [X29, #432]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X17, X14, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X8, X21, X8, X14	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X14, X25, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X14, X17, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X17, X12, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X19, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X8, X14, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X19, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
AND X3, X11, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X16, X8, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X13, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X16, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X16, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X8, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X8, X13, [SP, #40]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X19, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X8, X19, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 44df04 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_9DirectionElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK10LTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS25_3ref5rem_sIS1K_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1K_.omp_outlined+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run orig_0

Source file and lines	Collapse.hpp:129-133
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129-133
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp:62

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.67 to 3.25 cycles (5.74x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:130

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	123
nb uops	123
loop length	492
used w registers	5
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.38 cycles
front end	15.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	15.25	15.25	15.25	15.25	0.00	0.00	0.00	0.00	18.67	18.67	18.67	14.00	14.00
cycles	4.00	4.00	15.25	15.25	15.25	15.25	0.00	0.00	0.00	0.00	18.67	18.67	18.67	14.00	14.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.38
Dispatch	18.67
Overall L1	18.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	30%
load	31%
store	35%
mul	25%
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.67 cycles. At this rate:

0% of peak load performance is reached (0.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.32 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 44dd00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #272]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #288]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #304]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X8, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X26, #1, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
B.LT 44dde8 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_9DirectionElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK10LTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS25_3ref5rem_sIS1K_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1K_.omp_outlined+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X4]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [X4, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W1, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <4cfd44>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #392	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X3, X29, #36	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X5, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X22, X23, [X4, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X25, [X4, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
SUB X6, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X21, [X4, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X19, [X4, #248]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR WZR, [X29, #476]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STUR X10, [X29, #480]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X9, [X29, #408]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X11, [X29, #464]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [X4, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR W1, [SP, #20]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MADD X20, X26, X8, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X9, X8, [X4, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X20, XZR, [X29, #1000]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X11, [X29, #960]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X4, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X11, X8, [X4, #280]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
SUB X4, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X10, [SP]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X11, X9, [X29, #936]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X8, [X29, #416]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [X29, #1000]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X8, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X8, X20, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 44de08 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_9DirectionElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK10LTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS25_3ref5rem_sIS1K_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1K_.omp_outlined+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <4cfddc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #416	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #304]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #288]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X10, X23, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 44ddd8 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_9DirectionElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK10LTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS25_3ref5rem_sIS1K_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1K_.omp_outlined+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X11, X25, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 44ddd8 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_9DirectionElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK10LTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS25_3ref5rem_sIS1K_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1K_.omp_outlined+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X18, [X29, #424]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X8, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MUL X17, X22, X21	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ORN X16, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CNTW X0, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SUB X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X16, X23, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (100.0%)
SUB X4, X24, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X14, X13, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X12, X22, X18	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
MUL X16, X18, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X27, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X14, X26, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X14, [X29, #448]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X14, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X14, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X14, [X29, #440]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X14, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X14, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X14, [X29, #416]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X15, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDUR X14, [X29, #432]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X17, X14, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X8, X21, X8, X14	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X14, X25, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X14, X17, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X17, X12, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X19, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X8, X14, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X19, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
AND X3, X11, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X16, X8, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X13, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X16, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X16, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X8, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X8, X13, [SP, #40]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X19, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X8, X19, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 44df04 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_9DirectionElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK10LTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS25_3ref5rem_sIS1K_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1K_.omp_outlined+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼std::enable_if–	9.02	4.71
▼Loop 877 - For.hpp:142-142 - exec–	0.00	0.01
▼Loop 878 - For.hpp:142-142 - exec–	0.00	0.01
○Loop 876 - For.hpp:142-142 - exec	9.00	4.69
○Loop 879 - For.hpp:142-142 - exec	0.00	0.00
○Loop 880 - For.hpp:142-142 - exec	0.00	0.00

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Details

Matching between your function (in the source code) and the binary function

General properties

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Vector efficiency ratios

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Front-end bottlenecks

ASM code