OV - exec - Function std::enable_if<all_of<camp::concepts::metalib::negate_t<RAJA::internal::loop_data_has_reducers<camp::type::cv::rem_s<camp::type::ref::rem_s<RAJA::internal::LoopData<camp::tuple<RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Direction, long, Kripke::Direction*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Group, long, Kripke::Group*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Zone, long, Kripke::Zone*>, long> >, camp::tuple<>, camp::resources::v1::Host, PopulationSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field<double, Kripke::Direction, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Direction>&, Kripke::Core::Field<double, Kripke::Zone>&, double*) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&>::type>::type> > >::value, void>::type RAJA::internal::StatementExecutor<RAJA::statement::Collapse<RAJA::omp_parallel_collapse_exec, camp::int_seq<long, 0l, 1l>, RAJA::statement::For<2l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > >, RAJA::internal::LoopTypes<camp::list<void, void, void>, camp::list<void, void, void> > >::exec<RAJA::internal::LoopData<camp::tuple<RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Direction, long, Kripke::Direction*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Group, long, Kripke::Group*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Zone, long, Kripke::Zone*>, long> >, camp::tuple<>, camp::resources::v1::Host, PopulationSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field<double, Kripke::Direction, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Direction>&, Kripke::Core::Field<double, Kripke::Zone>&, double*) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData<camp::tuple<RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Direction, long, Kripke::Direction*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Group, long, Kripke::Group*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Zone, long, Kripke::Zone*>, long> >, camp::tuple<>, camp::resources::v1::Host, PopulationSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field<double, Kripke::Direction, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Direction>&, Kripke::Core::Field<double, Kripke::Zone>&, double*) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&) [clone .omp

	Function: std::enable_if<all_of<camp::concepts::metalib::negate_t<RAJA::internal::loop_data_has_redu ...	Module: exec	Source: Collapse.hpp:129-133 [...]	Coverage (incl. loops): 0.34% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp: 142 - 142

--------------------------------------------------------------------------------

142:     for (decltype(distance_it) i = 0; i < distance_it; ++i)

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/reduce.hpp: 60 - 61

--------------------------------------------------------------------------------

60: #pragma omp critical(ompReduceCritical)

61:       Reduce()(Base::parent->local(), Base::my_data);

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 129 - 133

--------------------------------------------------------------------------------

129: #pragma omp parallel for private(i0, i1) firstprivate(privatizer)              \

130:     RAJA_COLLAPSE(2)

131:     for (i0 = 0; i0 < l0; ++i0)

132:     {

133:       for (i1 = 0; i1 < l1; ++i1)

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp: 56 - 58

--------------------------------------------------------------------------------

56:         KRIPKE_LAMBDA (Direction d, Group g, Zone z) {

57:

58:           part_red += w(d) * psi(d,g,z) * volume(z);

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 369 - 369

--------------------------------------------------------------------------------

369:     return Ret {lhs} + rhs;

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp: 78 - 327

--------------------------------------------------------------------------------

78:     val = operator_type::operator()(val, v);

[...]

317:       : parent {other.parent ? other.parent : &other},

318:         identity {other.identity},

[...]

327:     if (parent && my_data != identity)

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/internal/LoopData.hpp: 152 - 152

--------------------------------------------------------------------------------

152:   constexpr LoopData(LoopData const&) = default;

0x454520 STR	D8, [SP, #400]!

0x454524 STP	X29, X30, [SP, #16]

0x454528 STP	X28, X27, [SP, #32]

0x45452c STP	X26, X25, [SP, #48]

0x454530 STP	X24, X23, [SP, #64]

0x454534 STP	X22, X21, [SP, #80]

0x454538 STP	X20, X19, [SP, #96]

0x45453c ADD	X29, SP, #16

0x454540 SUB	SP, SP, #64

0x454544 ADDVL	SP, SP, #63

0x454548 LDR	X8, [X2]

0x45454c LDR	X20, [X3]

0x454550 CMP	X8, #1

0x454554 CCMP	X20, #1, #8, #10

0x454558 B.LT	4547b4

0x45455c LDR	X11, [X4, #16]

0x454560 MOVN	X9, #0

0x454564 LDR	D8, [X4, #64]

0x454568 LDR	W1, [X0]

0x45456c ADDVL	X10, SP, #1

0x454570 ADRP	X0,

0x454574 ADD	X0, X0, #824

0x454578 ADD	X3, SP, #44

0x45457c MADD	X19, X20, X8, X9

0x454580 LDR	X21, [X4]

0x454584 LDP	X23, X27, [X4, #32]

0x454588 LDR	X24, [X4, #80]

0x45458c ADD	X5, SP, #56

0x454590 ADD	X6, SP, #48

0x454594 MOVZ	W2, #34

0x454598 LDR	X25, [X4, #120]

0x45459c LDP	X22, X28, [X4, #152]

0x4545a0 MOVZ	W7, #1

0x4545a4 LDR	X26, [X4, #224]

0x4545a8 STR	XZR, [X10, #72]

0x4545ac MOVZ	W10, #1

0x4545b0 STR	WZR, [SP, #44]

0x4545b4 STP	X10, X19, [SP, #48]

0x4545b8 STR	X11, [SP, #16]

0x4545bc ORR	X11, XZR, X4

0x4545c0 ADD	X4, SP, #72

0x4545c4 ADDVL	X4, X4, #1

0x4545c8 LDR	X8, [X11, #56]!

0x4545cc STR	X10, [SP]

0x4545d0 STR	W1, [SP, #28]

0x4545d4 CMP	X8, #0

0x4545d8 CSEL	X8, X11, X8, #0

0x4545dc STR	X8, [SP, #32]

0x4545e0 BL	410150

0x4545e4 ADDVL	X9, SP, #1

0x4545e8 LDR	X8, [SP, #56]

0x4545ec FMOV	D6, D8

0x4545f0 LDR	X9, [X9, #72]

0x4545f4 CMP	X8, X19

0x4545f8 CSEL	X8, X8, X19, #11

0x4545fc STR	X8, [SP, #56]

0x454600 CMP	X9, X8

0x454604 B.GT	454740

0x454608 SUB	X10, X27, X23

0x45460c FMOV	D6, D8

0x454610 CMP	X10, #1

0x454614 B.LT	454740

0x454618 LDR	X18, [SP, #16]

0x45461c CNTW	X11, ALL

0x454620 FMOV	D6, D8

0x454624 ADD	X12, X26, X23,LSL #3

0x454628 ADD	X15, X25, X23,LSL #3

0x45462c UBFM	X16, X22, #61, #60

0x454630 UBFM	X17, X28, #61, #60

0x454634 RDVL	X13, #1

0x454638 SUB	X1, X23, X27

0x45463c SUB	X14, XZR, X11

0x454640 ADD	X0, X13, X23,LSL #3

0x454644 PTRUE	P0.D, ALL

0x454648 AND	X13, X10, X14

0x45464c ADD	X14, X26, X0

0x454650 ADD	X0, X25, X0

0x454654 ADD	X18, X18, X9

0x454658 B	454670

0x45465c HINT	#0

  (1009) 0x454660 CMP	X9, X8

  (1009) 0x454664 ADD	X9, X9, #1

  (1009) 0x454668 ADD	X18, X18, #1

  (1009) 0x45466c B.EQ	454740

  (1009) 0x454670 SDIV	X2, X9, X20

  (1009) 0x454674 CMP	X10, X11

  (1009) 0x454678 MUL	X3, X20, X2

  (1009) 0x45467c ADD	X2, X2, X21

  (1009) 0x454680 LDR	D0, [X24, X2,LSL #3]

  (1009) 0x454684 B.CS	4546a0

  (1009) 0x454688 ORR	X5, XZR, XZR

  (1009) 0x45468c B	454700

0x454690 HINT	#0

0x454694 HINT	#0

0x454698 HINT	#0

0x45469c HINT	#0

(1007) 0x4546a0 SUB	X5, X18, X3

(1007) 0x4546a4 DUP	Z1.D, Z0.D[0]

(1007) 0x4546a8 ORR	X4, XZR, XZR

(1007) 0x4546ac MUL	X5, X17, X5

(1007) 0x4546b0 MADD	X6, X16, X2, X5

(1007) 0x4546b4 ADD	X5, X15, X6

(1007) 0x4546b8 ADD	X6, X0, X6

(1007) 0x4546bc HINT	#0

  (1006) 0x4546c0 LD1D	{Z2.D}, P0/Z, [X5, X4,LSL #3]

  (1006) 0x4546c4 LD1D	{Z4.D}, P0/Z, [X12, X4,LSL #3]

  (1006) 0x4546c8 FMUL	Z2.D, Z1.D, Z2.D

  (1006) 0x4546cc LD1D	{Z3.D}, P0/Z, [X6, X4,LSL #3]

  (1006) 0x4546d0 LD1D	{Z5.D}, P0/Z, [X14, X4,LSL #3]

  (1006) 0x4546d4 FMUL	Z3.D, Z1.D, Z3.D

  (1006) 0x4546d8 ADD	X4, X4, X11

  (1006) 0x4546dc CMP	X13, X4

  (1006) 0x4546e0 FMUL	Z2.D, Z2.D, Z4.D

  (1006) 0x4546e4 FMUL	Z3.D, Z3.D, Z5.D

  (1006) 0x4546e8 FADDA	D6, P0, D6, Z2.D

  (1006) 0x4546ec FADDA	D6, P0, D6, Z3.D

  (1006) 0x4546f0 B.NE	4546c0

(1007) 0x4546f4 CMP	X10, X13

(1007) 0x4546f8 ORR	X5, XZR, X13

(1007) 0x4546fc B.EQ	454660

  (1009) 0x454700 SUB	X3, X18, X3

  (1009) 0x454704 ADD	X6, X23, X5

  (1009) 0x454708 ADD	X4, X1, X5

  (1009) 0x45470c MUL	X3, X17, X3

  (1009) 0x454710 ADD	X5, X26, X6,LSL #3

  (1009) 0x454714 MADD	X2, X16, X2, X3

  (1009) 0x454718 ADD	X2, X2, X6,LSL #3

  (1009) 0x45471c ADD	X2, X25, X2

    (1008) 0x454720 LDR	D1, [X2], #8

    (1008) 0x454724 LDR	D2, [X5], #8

    (1008) 0x454728 ADDS	X4, X4, #1

    (1008) 0x45472c FMUL	D1, D0, D1

    (1008) 0x454730 FMUL	D1, D1, D2

    (1008) 0x454734 FADD	D6, D6, D1

    (1008) 0x454738 B.CC	454720

  (1009) 0x45473c B	454660

0x454740 LDR	W1, [SP, #28]

0x454744 SUB	X8, X29, #16

0x454748 ADRP	X0,

0x45474c ADD	X0, X0, #848

0x454750 STR	Z6, [X8, #511, MUL VL]

0x454754 BL	410050

0x454758 ADRP	X19,

0x45475c ADD	X19, X19, #896

0x454760 ORR	X0, XZR, X19

0x454764 BL	410120

0x454768 ADRP	X21,

0x45476c ORR	W20, WZR, W0

0x454770 ORR	X0, XZR, X19

0x454774 ORR	W1, WZR, W20

0x454778 LDR	X21, [X21, #3688]

0x45477c ORR	X2, XZR, X21

0x454780 BL	410360

0x454784 LDR	X22, [SP, #32]

0x454788 SUB	X8, X29, #16

0x45478c ORR	X0, XZR, X19

0x454790 ORR	W1, WZR, W20

0x454794 ORR	X2, XZR, X21

0x454798 LDR	Z1, [X8, #511, MUL VL]

0x45479c LDR	D0, [X22, #16]

0x4547a0 FADD	D0, D1, D0

0x4547a4 STR	D0, [X22, #16]

0x4547a8 BL	410180

0x4547ac FCMP	D8, D8

0x4547b0 B.VS	4547dc

0x4547b4 ADDVL	SP, SP, #1

0x4547b8 ADD	SP, SP, #64

0x4547bc LDP	X20, X19, [SP, #96]

0x4547c0 LDP	X22, X21, [SP, #80]

0x4547c4 LDP	X24, X23, [SP, #64]

0x4547c8 LDP	X26, X25, [SP, #48]

0x4547cc LDP	X28, X27, [SP, #32]

0x4547d0 LDP	X29, X30, [SP, #16]

0x4547d4 LDR	D8, [SP], #112

0x4547d8 RET

0x4547dc LDR	D0, [X22, #16]

0x4547e0 FADD	D0, D8, D0

0x4547e4 STR	D0, [X22, #16]

0x4547e8 B	4547b4

0x4547ec HINT	#0

Coverage (%)	Name	Source Location	Module
►98.50+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.50+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	void PopulationSdom::operator([...]	reduce.hpp:60	exec
○	auto Kripke::dispatch<Populati[...]	ArchLayout.h:206	exec
○	Kripke::Kernel::population(Kri[...]	stl_iterator.h:1102	exec
○	Kripke::SteadyStateSolver(Krip[...]	SteadyStateSolver.cpp:107	exec
○	main	kripke.cpp:509	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	LPlusTimes.cpp:0	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	Collapse.hpp:129-133
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/reduce.hpp:60-61
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129-133
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp:56-58
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:369
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp:78,317-318,327
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/internal/LoopData.hpp:152

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.25 to 3.17 cycles (5.13x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 31% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 16.25 to 11.28 cycles (1.44x speedup).

Details

2% of VPU instructions are used in vector version (process two or more data elements in vector registers):

5% of VPU loads are used in vector version.
5% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 5 occurrences►
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:130
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/reduce.hpp:60
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/reduce.hpp:60
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/reduce.hpp:61

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 38 bytes. The binary function is storing 38 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	128
nb uops	122
loop length	512
used w registers	7
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	4
used q registers	0
used v registers	0
used z registers	2
nb stack references	25

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.25 cycles
front end	15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	16.25	16.25	16.25	16.25	2.50	2.50	2.50	2.50	15.50	15.17	15.33	7.00	7.00
cycles	6.00	6.00	16.25	16.25	16.25	16.25	2.50	2.50	2.50	2.50	15.50	15.17	15.33	7.00	7.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.25
Dispatch	16.25
Overall L1	16.25

Vectorization ratios

INT

all	3%
load	5%
store	5%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	5%
store	5%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	32%
load	36%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
other	26%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	31%
load	36%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.25 cycles. At this rate:

2% of peak load performance is reached (2.34 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.34 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 454520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STR D8, [SP, #400]!	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB SP, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #63	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X20, #1, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.LT 4547b4 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS21_3ref5rem_sIS1F_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1F_.omp_outlined+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D8, [X4, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADDVL X10, SP, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADRP X0, <4cf570>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #824	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #44	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X19, X20, X8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X21, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X23, X27, [X4, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X24, [X4, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X5, SP, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X4, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X22, X28, [X4, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X26, [X4, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR XZR, [X10, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR WZR, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STP X10, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X11, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL X4, X4, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X8, [X11, #56]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W1, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X11, X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL X9, SP, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D6, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X9, [X9, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X8, X19, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 454740 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS21_3ref5rem_sIS1F_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1F_.omp_outlined+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X10, X27, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D6, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 454740 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS21_3ref5rem_sIS1F_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1F_.omp_outlined+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTW X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FMOV D6, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X12, X26, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X15, X25, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X16, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X17, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
RDVL X13, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X1, X23, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X14, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X13, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
AND X13, X10, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X26, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X25, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X18, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 454670 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS21_3ref5rem_sIS1F_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1F_.omp_outlined+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W1, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB X8, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4cf748>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #848	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z6, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X19, <4cf758>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X19, #896	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X21, <4cf768>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X21, [X21, #3688]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410360 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X8, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X2, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Z1, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR D0, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X22, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
BL 410180 <@plt_start@+0x160>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D8, D8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.VS 4547dc <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS21_3ref5rem_sIS1F_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1F_.omp_outlined+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR D8, [SP], #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X22, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 4547b4 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS21_3ref5rem_sIS1F_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1F_.omp_outlined+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	Collapse.hpp:129-133
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/reduce.hpp:60-61
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129-133
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp:56-58
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:369
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp:78,317-318,327
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/internal/LoopData.hpp:152

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.25 to 3.17 cycles (5.13x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

2% of VPU instructions are used in vector version (process two or more data elements in vector registers):

5% of VPU loads are used in vector version.
5% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 5 occurrences►
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:130
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/reduce.hpp:60
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/reduce.hpp:60
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/reduce.hpp:61

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 38 bytes. The binary function is storing 38 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	128
nb uops	122
loop length	512
used w registers	7
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	4
used q registers	0
used v registers	0
used z registers	2
nb stack references	25

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.25 cycles
front end	15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	16.25	16.25	16.25	16.25	2.50	2.50	2.50	2.50	15.50	15.17	15.33	7.00	7.00
cycles	6.00	6.00	16.25	16.25	16.25	16.25	2.50	2.50	2.50	2.50	15.50	15.17	15.33	7.00	7.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.25
Dispatch	16.25
Overall L1	16.25

Vectorization ratios

INT

all	3%
load	5%
store	5%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	5%
store	5%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	32%
load	36%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
other	26%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	31%
load	36%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.25 cycles. At this rate:

2% of peak load performance is reached (2.34 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.34 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 454520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STR D8, [SP, #400]!	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB SP, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #63	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X20, #1, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.LT 4547b4 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS21_3ref5rem_sIS1F_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1F_.omp_outlined+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D8, [X4, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADDVL X10, SP, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADRP X0, <4cf570>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #824	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #44	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X19, X20, X8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X21, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X23, X27, [X4, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X24, [X4, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X5, SP, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X4, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X22, X28, [X4, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X26, [X4, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR XZR, [X10, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR WZR, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STP X10, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X11, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL X4, X4, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X8, [X11, #56]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W1, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X11, X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL X9, SP, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D6, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X9, [X9, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X8, X19, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 454740 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS21_3ref5rem_sIS1F_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1F_.omp_outlined+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X10, X27, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D6, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 454740 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS21_3ref5rem_sIS1F_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1F_.omp_outlined+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTW X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FMOV D6, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X12, X26, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X15, X25, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X16, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X17, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
RDVL X13, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X1, X23, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X14, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X13, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
AND X13, X10, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X26, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X25, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X18, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 454670 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS21_3ref5rem_sIS1F_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1F_.omp_outlined+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W1, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB X8, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4cf748>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #848	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z6, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X19, <4cf758>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X19, #896	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X21, <4cf768>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X21, [X21, #3688]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410360 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X8, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X2, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Z1, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR D0, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X22, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
BL 410180 <@plt_start@+0x160>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D8, D8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.VS 4547dc <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS21_3ref5rem_sIS1F_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1F_.omp_outlined+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR D8, [SP], #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X22, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 4547b4 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsr6all_ofINS5_8concepts7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS21_3ref5rem_sIS1F_E4typeEE4typeEEEEEEE5valueEvE4typeEOS1F_.omp_outlined+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼std::enable_if–	0.34	0.18
▼Loop 1007 - Collapse.hpp:131-131 - exec–	0.00	0.00
○Loop 1006 - For.hpp:142-142 - exec	0.34	0.18
▼Loop 1009 - For.hpp:142-142 - exec–	0.00	0.00
○Loop 1008 - For.hpp:142-142 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code