OV - exec - Function std::enable_if<camp::concepts::all_of<camp::concepts::metalib::negate_t<RAJA::internal::loop_data_has_reducers<camp::type::cv::rem_s<camp::type::ref::rem_s<RAJA::internal::LoopData<camp::tuple<RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Direction, long, Kripke::Direction*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Group, long, Kripke::Group*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneK, long, Kripke::ZoneK*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneJ, long, Kripke::ZoneJ*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneI, long, Kripke::ZoneI*>, long> >, camp::tuple<>, camp::resources::v1::Host, SweepSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&>::type>::type> > >::value, void>::type RAJA::internal::StatementExecutor<RAJA::statement::Collapse<RAJA::omp_parallel_collapse_exec, camp::int_seq<long, 0l, 1l>, RAJA::statement::For<2l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<4l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > > >, RAJA::internal::LoopTypes<camp::list<void, void, void, void, void>, camp::list<void, void, void, void, void> > >::exec<RAJA::internal::LoopData<camp::tuple<RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Direction, long, Kripke::Direction*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Group, long, Kripke::Group*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneK, long, Kripke::ZoneK*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneJ, long, Kripke::ZoneJ*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneI, long, Kripke::ZoneI*>, long> >, camp::tuple<>, camp::resources::v1::Host, SweepSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&>(RAJA::internal::LoopData<camp::tuple<RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Direction, long, Kripke::Direction*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Group, long, Kripke::Group*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneK, long, Kripke::ZoneK*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneJ, long, Kripke::ZoneJ*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneI, long, Kripke::ZoneI*>, long> >, camp::tuple<>, camp::resources::v1::Host, SweepSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&) [clone ._omp

	Function: std::enable_if<camp::concepts::all_of<camp::concepts::metalib::negate_t<RAJA::internal::lo ...	Module: exec	Source: Collapse.hpp:129-129 [...]	Coverage (incl. loops): 0.96% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 187 - 187

--------------------------------------------------------------------------------

187:     return sum<IdxLin>((RangeInts == stride_one_dim

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp: 142 - 142

--------------------------------------------------------------------------------

142:     for (decltype(distance_it) i = 0; i < distance_it; ++i)

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 129 - 129

--------------------------------------------------------------------------------

129: #pragma omp parallel for private(i0, i1) firstprivate(privatizer)              \

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp: 88 - 106

--------------------------------------------------------------------------------

88:             double xcos_dxi = 2.0 * xcos(d) / dx(i);

89:             double ycos_dyj = 2.0 * ycos(d) / dy(j);

90:             double zcos_dzk = 2.0 * zcos(d) / dz(k);

91:

92:             Zone z(zone_layout(*k, *j, *i));

93:

94:             /* Calculate new zonal flux */

95:             double psi_d_g_z = (rhs(d,g,z)

96:                 + psi_lf(d, g, j, k) * xcos_dxi

97:                 + psi_fr(d, g, i, k) * ycos_dyj

98:                 + psi_bo(d, g, i, j) * zcos_dzk)

99:                 / (xcos_dxi + ycos_dyj + zcos_dzk + sigt(g, z));

100:

101:             psi(d, g, z) = psi_d_g_z;

102:

103:             /* Apply diamond-difference relationships */

104:             psi_lf(d, g, j, k) = 2.0 * psi_d_g_z - psi_lf(d, g, j, k);

105:             psi_fr(d, g, i, k) = 2.0 * psi_d_g_z - psi_fr(d, g, i, k);

106:             psi_bo(d, g, i, j) = 2.0 * psi_d_g_z - psi_bo(d, g, i, j);

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 369 - 369

--------------------------------------------------------------------------------

369:     return Ret {lhs} + rhs;

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/TypedViewBase.hpp: 216 - 216

--------------------------------------------------------------------------------

216:     return data[stripIndexType(layout(args...))];

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp: 291 - 377

--------------------------------------------------------------------------------

291:     return value_type(val + rhs);

[...]

373:     difference_type diff = (static_cast<difference_type>(val) -

374:                             (static_cast<difference_type>(rhs.val)));

375:

376:     return (diff % stride != difference_type {0})

377:                ? (difference_type {1} + diff / stride)

0x488580 SUB	SP, SP, #528

0x488584 STP	X29, X30, [SP]

0x488588 ADD	X29, SP, #0

0x48858c STP	X19, X20, [SP, #16]

0x488590 ORR	X20, XZR, X0

0x488594 STP	X21, X22, [SP, #32]

0x488598 LDP	X21, X0, [X0]

0x48859c STR	X0, [SP, #192]

0x4885a0 CMP	X21, #0

0x4885a4 B.LE	488a6c

0x4885a8 CMP	X0, #0

0x4885ac B.LE	488a6c

0x4885b0 MUL	X21, X21, X0

0x4885b4 BL	410520

0x4885b8 SBFM	X19, X0, #0, #31

0x4885bc BL	410420

0x4885c0 UDIV	X9, X21, X19

0x4885c4 SBFM	X1, X0, #0, #31

0x4885c8 MSUB	X0, X9, X19, X21

0x4885cc CMP	X1, X0

0x4885d0 B.CC	488a80

0x4885d4 MADD	X1, X9, X1, X0

0x4885d8 ADD	X0, X9, X1

0x4885dc CMP	X1, X0

0x4885e0 B.CS	488a6c

0x4885e4 LDR	X3, [SP, #192]

0x4885e8 STP	X23, X24, [SP, #48]

0x4885ec LDR	X12, [X20, #16]

0x4885f0 UDIV	X2, X1, X3

0x4885f4 STP	X25, X26, [SP, #64]

0x4885f8 STP	X27, X28, [SP, #80]

0x4885fc LDR	X0, [X12]

0x488600 LDP	X6, X14, [X12, #72]

0x488604 MSUB	X1, X2, X3, X1

0x488608 LDP	X10, X15, [X12, #104]

0x48860c STP	X1, X2, [SP, #160]

0x488610 LDR	X2, [X12, #64]

0x488614 STR	X0, [SP, #232]

0x488618 LDR	X0, [X12, #16]

0x48861c LDR	X1, [X12, #40]

0x488620 STR	X2, [SP, #184]

0x488624 LDR	X2, [X12, #88]

0x488628 STR	X0, [SP, #208]

0x48862c LDR	X0, [X12, #32]

0x488630 LDR	X16, [X12, #56]

0x488634 STR	X2, [SP, #224]

0x488638 LDR	X2, [X12, #96]

0x48863c LDR	X19, [X12, #176]

0x488640 STR	X2, [SP, #176]

0x488644 LDR	X2, [X12, #120]

0x488648 STR	X2, [SP, #152]

0x48864c LDR	X2, [X12, #136]

0x488650 STR	X2, [SP, #280]

0x488654 LDR	X2, [X12, #216]

0x488658 LDP	X5, X11, [X12, #400]

0x48865c STR	X2, [SP, #296]

0x488660 LDR	X2, [X12, #296]

0x488664 LDR	X13, [X12, #48]

0x488668 LDR	X18, [X12, #256]

0x48866c STR	X2, [SP, #288]

0x488670 LDR	X2, [X12, #472]

0x488674 SUB	X13, X13, X0

0x488678 LDR	X17, [X12, #336]

0x48867c SDIV	X7, X13, X16

0x488680 LDR	X8, [X12, #416]

0x488684 STR	X2, [SP, #272]

0x488688 LDR	X2, [X12, #504]

0x48868c LDR	X3, [X12, #640]

0x488690 CMP	X8, #1

0x488694 LDR	X4, [X12, #776]

0x488698 CCMP	X10, #1, #0, #0

0x48869c STR	X2, [SP, #264]

0x4886a0 LDR	X2, [X12, #512]

0x4886a4 MSUB	X13, X7, X16, X13

0x4886a8 STR	X2, [SP, #256]

0x4886ac LDR	X2, [X12, #576]

0x4886b0 STR	X2, [SP, #216]

0x4886b4 LDR	X2, [X12, #616]

0x4886b8 STR	X2, [SP, #240]

0x4886bc LDR	X2, [X12, #624]

0x4886c0 STR	X2, [SP, #248]

0x4886c4 LDR	X2, [X12, #712]

0x4886c8 STR	X2, [SP, #304]

0x4886cc LDR	X2, [X12, #752]

0x4886d0 STR	X2, [SP, #312]

0x4886d4 LDR	X2, [X12, #760]

0x4886d8 STR	X2, [SP, #320]

0x4886dc LDR	X2, [X12, #848]

0x4886e0 STR	X2, [SP, #328]

0x4886e4 LDR	X2, [X12, #888]

0x4886e8 LDR	X20, [X12, #984]

0x4886ec LDR	X16, [X12, #1088]

0x4886f0 STR	X2, [SP, #336]

0x4886f4 LDR	X2, [X12, #896]

0x4886f8 STR	X20, [SP, #352]

0x4886fc LDR	X20, [X12, #1008]

0x488700 STR	X16, [SP, #376]

0x488704 STR	X2, [SP, #344]

0x488708 LDR	X2, [X12, #912]

0x48870c STR	X20, [SP, #360]

0x488710 LDR	X20, [X12, #1056]

0x488714 LDR	X12, [X12, #1096]

0x488718 STR	X20, [SP, #368]

0x48871c STR	X12, [SP, #384]

0x488720 B.NE	488a9c

0x488724 LDR	X12, [SP, #184]

0x488728 SUB	X8, X9, #1

0x48872c UBFM	X16, X6, #61, #60

0x488730 CMP	X13, #0

0x488734 CSINC	X7, X7, X7, #0

0x488738 ADD	X13, X17, X0,LSL #3

0x48873c STR	X8, [SP, #440]

0x488740 MUL	X8, X6, X11

0x488744 CMP	X7, #0

0x488748 MUL	X6, X6, X2

0x48874c STR	X7, [SP, #392]

0x488750 FMOV	D4, #2.0000000

0x488754 LDR	X24, [SP, #152]

0x488758 SUB	X9, X14, X12

0x48875c MUL	X10, X12, X11

0x488760 ORR	X11, XZR, X12

0x488764 LDR	X12, [SP, #176]

0x488768 UBFM	X14, X1, #61, #60

0x48876c STR	X9, [SP, #448]

0x488770 MUL	X9, X1, X4

0x488774 STR	XZR, [SP, #200]

0x488778 STR	X13, [SP, #408]

0x48877c UBFM	X9, X9, #61, #60

0x488780 MADD	X4, X0, X4, X12

0x488784 SUB	X30, X15, X12

0x488788 UBFM	X15, X8, #61, #60

0x48878c ORR	X8, XZR, X7

0x488790 ORR	X7, XZR, X11

0x488794 ADD	X11, X18, X11,LSL #3

0x488798 UBFM	X18, X6, #61, #60

0x48879c MADD	X6, X0, X5, X10

0x4887a0 CSEL	X8, X8, XZR, #10

0x4887a4 MUL	X0, X0, X3

0x4887a8 STP	X8, X14, [SP, #104]

0x4887ac MUL	X5, X1, X5

0x4887b0 STP	X4, X0, [SP, #416]

0x4887b4 MUL	X0, X1, X3

0x4887b8 STR	X0, [SP, #128]

0x4887bc MADD	X0, X2, X7, X12

0x4887c0 STP	X5, X11, [SP, #136]

0x4887c4 ADD	X11, X19, X12,LSL #3

0x4887c8 STR	X9, [SP, #120]

0x4887cc STR	X0, [SP, #400]

0x4887d0 STR	X6, [SP, #432]

(2424) 0x4887d4 LDR	X0, [SP, #392]

(2424) 0x4887d8 CMP	X0, #0

(2424) 0x4887dc B.LE	488a28

(2424) 0x4887e0 LDR	X0, [SP, #168]

(2424) 0x4887e4 MOVZ	X20, #0

(2424) 0x4887e8 LDP	X4, X2, [SP, #224]

(2424) 0x4887ec LDP	X21, X22, [SP, #424]

(2424) 0x4887f0 ADD	X23, X0, X2

(2424) 0x4887f4 UBFM	X10, X23, #61, #60

(2424) 0x4887f8 LDR	X0, [SP, #160]

(2424) 0x4887fc LDR	X2, [SP, #208]

(2424) 0x488800 LDR	X1, [SP, #448]

(2424) 0x488804 LDR	X5, [SP, #360]

(2424) 0x488808 ADD	X0, X0, X2

(2424) 0x48880c LDR	X2, [SP, #280]

(2424) 0x488810 SDIV	X25, X1, X4

(2424) 0x488814 LDR	X8, [SP, #408]

(2424) 0x488818 ADD	X13, X2, X10

(2424) 0x48881c LDR	X2, [SP, #296]

(2424) 0x488820 ADD	X12, X2, X10

(2424) 0x488824 LDR	X2, [SP, #288]

(2424) 0x488828 MSUB	X1, X25, X4, X1

(2424) 0x48882c LDR	X4, [SP, #400]

(2424) 0x488830 CMP	X1, #0

(2424) 0x488834 LDR	X1, [SP, #328]

(2424) 0x488838 CSINC	X25, X25, X25, #0

(2424) 0x48883c ADD	X10, X2, X10

(2424) 0x488840 CMP	X25, #0

(2424) 0x488844 CSEL	X19, X25, XZR, #10

(2424) 0x488848 LDR	X2, [SP, #312]

(2424) 0x48884c MUL	X3, X2, X23

(2424) 0x488850 LDR	X2, [SP, #264]

(2424) 0x488854 MUL	X28, X2, X23

(2424) 0x488858 LDR	X2, [SP, #240]

(2424) 0x48885c MUL	X27, X2, X23

(2424) 0x488860 LDR	X2, [SP, #336]

(2424) 0x488864 MUL	X26, X2, X23

(2424) 0x488868 LDR	X2, [SP, #376]

(2424) 0x48886c MUL	X23, X2, X23

(2424) 0x488870 LDR	X2, [SP, #320]

(2424) 0x488874 MADD	X3, X2, X0, X3

(2424) 0x488878 LDR	X2, [SP, #256]

(2424) 0x48887c MADD	X28, X2, X0, X28

(2424) 0x488880 LDR	X2, [SP, #248]

(2424) 0x488884 MADD	X27, X2, X0, X27

(2424) 0x488888 LDR	X2, [SP, #344]

(2424) 0x48888c MADD	X26, X2, X0, X26

(2424) 0x488890 LDR	X2, [SP, #416]

(2424) 0x488894 ADD	X26, X26, X4

(2424) 0x488898 ADD	X26, X1, X26,LSL #3

(2424) 0x48889c LDR	X1, [SP, #368]

(2424) 0x4888a0 ADD	X3, X3, X2

(2424) 0x4888a4 LDR	X2, [SP, #384]

(2424) 0x4888a8 MADD	X23, X2, X0, X23

(2424) 0x4888ac LDR	X2, [SP, #176]

(2424) 0x4888b0 MADD	X0, X5, X0, X2

(2424) 0x4888b4 ADD	X28, X28, X2

(2424) 0x4888b8 ADD	X23, X23, X2

(2424) 0x4888bc LDR	X2, [SP, #304]

(2424) 0x4888c0 ADD	X23, X1, X23,LSL #3

(2424) 0x4888c4 LDR	X5, [SP, #184]

(2424) 0x4888c8 ADD	X3, X2, X3,LSL #3

(2424) 0x4888cc LDR	X2, [SP, #272]

(2424) 0x4888d0 ADD	X27, X27, X5

(2424) 0x4888d4 ADD	X28, X2, X28,LSL #3

(2424) 0x4888d8 LDR	X2, [SP, #216]

(2424) 0x4888dc LDR	X1, [SP, #352]

(2424) 0x4888e0 ADD	X27, X2, X27,LSL #3

(2424) 0x4888e4 ADD	X0, X1, X0,LSL #3

(2424) 0x4888e8 STR	X0, [SP, #152]

  (2425) 0x4888ec CMP	X25, #0

  (2425) 0x4888f0 B.LE	4889f8

  (2425) 0x4888f4 SDIV	X17, X30, X24

  (2425) 0x4888f8 LDP	X5, X0, [SP, #144]

  (2425) 0x4888fc UBFM	X4, X22, #61, #60

  (2425) 0x488900 ADD	X7, X28, X4

  (2425) 0x488904 ORR	X2, XZR, X26

  (2425) 0x488908 MOVZ	X14, #0

  (2425) 0x48890c ADD	X1, X27, X21,LSL #3

  (2425) 0x488910 ADD	X6, X4, X0

  (2425) 0x488914 ADD	X4, X4, X23

  (2425) 0x488918 MSUB	X0, X17, X24, X30

  (2425) 0x48891c CMP	X0, #0

  (2425) 0x488920 CSINC	X17, X17, X17, #0

  (2425) 0x488924 CMP	X17, #0

  (2425) 0x488928 CSEL	X9, X17, XZR, #10

    (2426) 0x48892c MOVZ	X0, #0

    (2426) 0x488930 CMP	X17, #0

    (2426) 0x488934 B.LE	4889d4

    (2426) 0x488938 HINT	#0

    (2426) 0x48893c HINT	#0

      (2427) 0x488940 LDR	D0, [X13]

      (2427) 0x488944 LDR	D3, [X12]

      (2427) 0x488948 LDR	D1, [X11, X0,LSL #3]

      (2427) 0x48894c FADD	D0, D0, D0

      (2427) 0x488950 LDR	D5, [X5]

      (2427) 0x488954 FADD	D3, D3, D3

      (2427) 0x488958 LDR	D2, [X10]

      (2427) 0x48895c LDR	D17, [X8]

      (2427) 0x488960 FDIV	D0, D0, D1

      (2427) 0x488964 LDR	D16, [X1]

      (2427) 0x488968 FADD	D2, D2, D2

      (2427) 0x48896c LDR	D1, [X7, X0,LSL #3]

      (2427) 0x488970 LDR	D7, [X3, X0,LSL #3]

      (2427) 0x488974 FDIV	D3, D3, D5

      (2427) 0x488978 LDR	D6, [X2, X0,LSL #3]

      (2427) 0x48897c LDR	D5, [X6, X0,LSL #3]

      (2427) 0x488980 FDIV	D2, D2, D17

      (2427) 0x488984 FMADD	D1, D16, D0, D1

      (2427) 0x488988 FADD	D0, D3, D0

      (2427) 0x48898c FMADD	D1, D7, D3, D1

      (2427) 0x488990 FADD	D0, D0, D2

      (2427) 0x488994 FMADD	D1, D6, D2, D1

      (2427) 0x488998 FADD	D0, D0, D5

      (2427) 0x48899c FDIV	D0, D1, D0

      (2427) 0x4889a0 STR	D0, [X4, X0,LSL #3]

      (2427) 0x4889a4 LDR	D1, [X1]

      (2427) 0x4889a8 FNMSUB	D1, D0, D4, D1

      (2427) 0x4889ac STR	D1, [X1]

      (2427) 0x4889b0 LDR	D1, [X3, X0,LSL #3]

      (2427) 0x4889b4 FNMSUB	D1, D0, D4, D1

      (2427) 0x4889b8 STR	D1, [X3, X0,LSL #3]

      (2427) 0x4889bc LDR	D1, [X2, X0,LSL #3]

      (2427) 0x4889c0 FNMSUB	D0, D0, D4, D1

      (2427) 0x4889c4 STR	D0, [X2, X0,LSL #3]

      (2427) 0x4889c8 ADD	X0, X0, #1

      (2427) 0x4889cc CMP	X9, X0

      (2427) 0x4889d0 B.GT	488940

    (2426) 0x4889d4 ADD	X14, X14, #1

    (2426) 0x4889d8 ADD	X5, X5, X16

    (2426) 0x4889dc ADD	X7, X7, X15

    (2426) 0x4889e0 ADD	X1, X1, X16

    (2426) 0x4889e4 ADD	X2, X2, X18

    (2426) 0x4889e8 ADD	X6, X6, X15

    (2426) 0x4889ec ADD	X4, X4, X15

    (2426) 0x4889f0 CMP	X19, X14

    (2426) 0x4889f4 B.GT	48892c

  (2425) 0x4889f8 LDR	X0, [SP, #112]

  (2425) 0x4889fc ADD	X20, X20, #1

  (2425) 0x488a00 ADD	X8, X8, X0

  (2425) 0x488a04 LDR	X0, [SP, #120]

  (2425) 0x488a08 ADD	X3, X3, X0

  (2425) 0x488a0c LDR	X0, [SP, #128]

  (2425) 0x488a10 ADD	X21, X21, X0

  (2425) 0x488a14 LDR	X0, [SP, #136]

  (2425) 0x488a18 ADD	X22, X22, X0

  (2425) 0x488a1c LDR	X0, [SP, #104]

  (2425) 0x488a20 CMP	X0, X20

  (2425) 0x488a24 B.GT	4888ec

(2424) 0x488a28 LDR	X0, [SP, #200]

(2424) 0x488a2c LDR	X1, [SP, #440]

(2424) 0x488a30 CMP	X0, X1

(2424) 0x488a34 B.EQ	488a60

(2424) 0x488a38 LDR	X0, [SP, #160]

(2424) 0x488a3c LDR	X1, [SP, #192]

(2424) 0x488a40 ADD	X0, X0, #1

(2424) 0x488a44 STR	X0, [SP, #160]

(2424) 0x488a48 CMP	X1, X0

(2424) 0x488a4c B.LE	488a8c

(2424) 0x488a50 LDR	X0, [SP, #200]

(2424) 0x488a54 ADD	X0, X0, #1

(2424) 0x488a58 STR	X0, [SP, #200]

(2424) 0x488a5c B	4887d4

0x488a60 LDP	X23, X24, [SP, #48]

0x488a64 LDP	X25, X26, [SP, #64]

0x488a68 LDP	X27, X28, [SP, #80]

0x488a6c LDP	X29, X30, [SP]

0x488a70 LDP	X19, X20, [SP, #16]

0x488a74 LDP	X21, X22, [SP, #32]

0x488a78 ADD	SP, SP, #528

0x488a7c RET

0x488a80 ADD	X9, X9, #1

0x488a84 MOVZ	X0, #0

0x488a88 B	4885d4

(2424) 0x488a8c LDR	X0, [SP, #168]

(2424) 0x488a90 ADD	X0, X0, #1

(2424) 0x488a94 STP	XZR, X0, [SP, #160]

(2424) 0x488a98 B	488a50

0x488a9c LDR	X16, [SP, #184]

0x488aa0 SUB	X9, X9, #1

0x488aa4 UBFM	X22, X10, #61, #60

0x488aa8 FMOV	D4, #2.0000000

0x488aac CMP	X13, #0

0x488ab0 MUL	X25, X6, X2

0x488ab4 STR	X9, [SP, #512]

0x488ab8 MUL	X9, X6, X11

0x488abc UBFM	X21, X6, #61, #60

0x488ac0 CSINC	X7, X7, X7, #0

0x488ac4 CMP	X7, #0

0x488ac8 STR	XZR, [SP, #112]

0x488acc STR	X7, [SP, #464]

0x488ad0 CSEL	X7, X7, XZR, #10

0x488ad4 MUL	X12, X16, X11

0x488ad8 SUB	X11, X14, X16

0x488adc LDR	X14, [SP, #176]

0x488ae0 UBFM	X28, X9, #61, #60

0x488ae4 ADD	X13, X18, X16,LSL #3

0x488ae8 STR	X7, [SP, #128]

0x488aec STR	X11, [SP, #520]

0x488af0 MADD	X9, X0, X5, X12

0x488af4 MUL	X5, X1, X5

0x488af8 STR	X13, [SP, #136]

0x488afc SUB	X11, X15, X14

0x488b00 ADD	X27, X19, X14,LSL #3

0x488b04 STR	X9, [SP, #504]

0x488b08 STR	X5, [SP, #408]

0x488b0c MUL	X5, X14, X8

0x488b10 STR	X11, [SP, #456]

0x488b14 MUL	X11, X8, X10

0x488b18 UBFM	X10, X1, #61, #60

0x488b1c STR	X10, [SP, #200]

0x488b20 ADD	X10, X17, X0,LSL #3

0x488b24 STR	X5, [SP, #472]

0x488b28 MUL	X5, X1, X4

0x488b2c UBFM	X26, X11, #61, #60

0x488b30 MUL	X4, X0, X4

0x488b34 MUL	X0, X0, X3

0x488b38 STR	X10, [SP, #480]

0x488b3c STR	X5, [SP, #392]

0x488b40 STR	X4, [SP, #488]

0x488b44 STR	X0, [SP, #496]

0x488b48 MUL	X0, X1, X3

0x488b4c STR	X0, [SP, #400]

0x488b50 MUL	X0, X2, X16

0x488b54 STR	X0, [SP, #144]

(2420) 0x488b58 LDR	X0, [SP, #464]

(2420) 0x488b5c CMP	X0, #0

(2420) 0x488b60 B.LE	488e00

(2420) 0x488b64 LDP	X0, X3, [SP, #160]

(2420) 0x488b68 STR	XZR, [SP, #104]

(2420) 0x488b6c LDR	X1, [SP, #208]

(2420) 0x488b70 LDP	X10, X23, [SP, #480]

(2420) 0x488b74 LDP	X24, X30, [SP, #496]

(2420) 0x488b78 ADD	X0, X0, X1

(2420) 0x488b7c LDR	X1, [SP, #232]

(2420) 0x488b80 LDR	X7, [SP, #264]

(2420) 0x488b84 LDR	X12, [SP, #336]

(2420) 0x488b88 ADD	X18, X1, X3

(2420) 0x488b8c LDR	X1, [SP, #280]

(2420) 0x488b90 UBFM	X11, X18, #61, #60

(2420) 0x488b94 LDR	X3, [SP, #344]

(2420) 0x488b98 LDR	X9, [SP, #224]

(2420) 0x488b9c ADD	X14, X1, X11

(2420) 0x488ba0 LDR	X1, [SP, #296]

(2420) 0x488ba4 MUL	X3, X3, X0

(2420) 0x488ba8 LDR	X8, [SP, #520]

(2420) 0x488bac ADD	X13, X1, X11

(2420) 0x488bb0 LDR	X1, [SP, #288]

(2420) 0x488bb4 SDIV	X2, X8, X9

(2420) 0x488bb8 ADD	X11, X1, X11

(2420) 0x488bbc LDR	X1, [SP, #256]

(2420) 0x488bc0 MUL	X6, X1, X0

(2420) 0x488bc4 MADD	X6, X7, X18, X6

(2420) 0x488bc8 LDP	X7, X1, [SP, #240]

(2420) 0x488bcc MUL	X5, X1, X0

(2420) 0x488bd0 MADD	X5, X7, X18, X5

(2420) 0x488bd4 LDP	X7, X1, [SP, #376]

(2420) 0x488bd8 MUL	X4, X1, X0

(2420) 0x488bdc MADD	X4, X7, X18, X4

(2420) 0x488be0 LDP	X7, X1, [SP, #312]

(2420) 0x488be4 MUL	X1, X1, X0

(2420) 0x488be8 MADD	X1, X7, X18, X1

(2420) 0x488bec LDR	X7, [SP, #472]

(2420) 0x488bf0 MADD	X18, X12, X18, X3

(2420) 0x488bf4 LDR	X3, [SP, #184]

(2420) 0x488bf8 ADD	X6, X6, X7

(2420) 0x488bfc ADD	X4, X4, X7

(2420) 0x488c00 ADD	X5, X5, X3

(2420) 0x488c04 LDR	X3, [SP, #360]

(2420) 0x488c08 MADD	X0, X3, X0, X7

(2420) 0x488c0c LDR	X7, [SP, #176]

(2420) 0x488c10 MSUB	X3, X2, X9, X8

(2420) 0x488c14 CMP	X3, #0

(2420) 0x488c18 CSINC	X2, X2, X2, #0

(2420) 0x488c1c ADD	X1, X1, X7

(2420) 0x488c20 ADD	X18, X18, X7

(2420) 0x488c24 LDR	X7, [SP, #272]

(2420) 0x488c28 CMP	X2, #0

(2420) 0x488c2c CSEL	X19, X2, XZR, #10

(2420) 0x488c30 ADD	X6, X7, X6,LSL #3

(2420) 0x488c34 STR	X6, [SP, #424]

(2420) 0x488c38 LDR	X6, [SP, #216]

(2420) 0x488c3c ADD	X5, X6, X5,LSL #3

(2420) 0x488c40 STR	X5, [SP, #432]

(2420) 0x488c44 LDR	X5, [SP, #368]

(2420) 0x488c48 STR	X2, [SP, #120]

(2420) 0x488c4c LDR	X3, [SP, #304]

(2420) 0x488c50 ADD	X4, X5, X4,LSL #3

(2420) 0x488c54 ADD	X1, X3, X1,LSL #3

(2420) 0x488c58 STR	X4, [SP, #448]

(2420) 0x488c5c STR	X1, [SP, #416]

(2420) 0x488c60 LDR	X1, [SP, #328]

(2420) 0x488c64 ADD	X18, X1, X18,LSL #3

(2420) 0x488c68 LDR	X1, [SP, #352]

(2420) 0x488c6c ADD	X0, X1, X0,LSL #3

(2420) 0x488c70 STR	X0, [SP, #440]

  (2421) 0x488c74 LDR	X0, [SP, #120]

  (2421) 0x488c78 CMP	X0, #0

  (2421) 0x488c7c B.LE	488dc8

  (2421) 0x488c80 LDR	X2, [SP, #424]

  (2421) 0x488c84 UBFM	X6, X30, #61, #60

  (2421) 0x488c88 MOVZ	X15, #0

  (2421) 0x488c8c LDP	X7, X16, [SP, #136]

  (2421) 0x488c90 ADD	X9, X2, X6

  (2421) 0x488c94 LDR	X2, [SP, #440]

  (2421) 0x488c98 LDR	X1, [SP, #152]

  (2421) 0x488c9c LDR	X0, [SP, #456]

  (2421) 0x488ca0 ADD	X8, X6, X2

  (2421) 0x488ca4 LDR	X2, [SP, #448]

  (2421) 0x488ca8 SDIV	X17, X0, X1

  (2421) 0x488cac ADD	X6, X6, X2

  (2421) 0x488cb0 LDR	X2, [SP, #432]

  (2421) 0x488cb4 ADD	X3, X2, X24,LSL #3

  (2421) 0x488cb8 LDR	X2, [SP, #416]

  (2421) 0x488cbc MSUB	X0, X17, X1, X0

  (2421) 0x488cc0 ADD	X20, X2, X23,LSL #3

  (2421) 0x488cc4 CMP	X0, #0

  (2421) 0x488cc8 CSINC	X17, X17, X17, #0

  (2421) 0x488ccc CMP	X17, #0

  (2421) 0x488cd0 CSEL	X12, X17, XZR, #10

  (2421) 0x488cd4 HINT	#0

  (2421) 0x488cd8 HINT	#0

  (2421) 0x488cdc HINT	#0

    (2422) 0x488ce0 CMP	X17, #0

    (2422) 0x488ce4 B.LE	488da4

    (2422) 0x488ce8 ADD	X2, X18, X16,LSL #3

    (2422) 0x488cec ORR	X1, XZR, X20

    (2422) 0x488cf0 ORR	X5, XZR, X27

    (2422) 0x488cf4 MOVZ	X0, #0

    (2422) 0x488cf8 MOVZ	X4, #0

    (2422) 0x488cfc HINT	#0

      (2423) 0x488d00 LDR	D0, [X14]

      (2423) 0x488d04 ADD	X4, X4, #1

      (2423) 0x488d08 LDR	D3, [X13]

      (2423) 0x488d0c LDR	D1, [X5]

      (2423) 0x488d10 ADD	X5, X5, X22

      (2423) 0x488d14 FADD	D0, D0, D0

      (2423) 0x488d18 LDR	D5, [X7]

      (2423) 0x488d1c FADD	D3, D3, D3

      (2423) 0x488d20 LDR	D2, [X11]

      (2423) 0x488d24 LDR	D17, [X10]

      (2423) 0x488d28 FDIV	D0, D0, D1

      (2423) 0x488d2c LDR	D16, [X3]

      (2423) 0x488d30 FADD	D2, D2, D2

      (2423) 0x488d34 LDR	D1, [X9, X0]

      (2423) 0x488d38 LDR	D7, [X1]

      (2423) 0x488d3c FDIV	D3, D3, D5

      (2423) 0x488d40 LDR	D6, [X2]

      (2423) 0x488d44 LDR	D5, [X8, X0]

      (2423) 0x488d48 FDIV	D2, D2, D17

      (2423) 0x488d4c FMADD	D1, D0, D16, D1

      (2423) 0x488d50 FADD	D0, D0, D3

      (2423) 0x488d54 FMADD	D1, D3, D7, D1

      (2423) 0x488d58 FADD	D0, D0, D2

      (2423) 0x488d5c FMADD	D1, D2, D6, D1

      (2423) 0x488d60 FADD	D0, D0, D5

      (2423) 0x488d64 FDIV	D0, D1, D0

      (2423) 0x488d68 STR	D0, [X6, X0]

      (2423) 0x488d6c ADD	X0, X0, X26

      (2423) 0x488d70 LDR	D1, [X3]

      (2423) 0x488d74 FNMSUB	D1, D0, D4, D1

      (2423) 0x488d78 STR	D1, [X3]

      (2423) 0x488d7c LDR	D1, [X1]

      (2423) 0x488d80 FNMSUB	D1, D0, D4, D1

      (2423) 0x488d84 STR	D1, [X1]

      (2423) 0x488d88 ADD	X1, X1, X22

      (2423) 0x488d8c LDR	D1, [X2]

      (2423) 0x488d90 FNMSUB	D0, D0, D4, D1

      (2423) 0x488d94 STR	D0, [X2]

      (2423) 0x488d98 ADD	X2, X2, X22

      (2423) 0x488d9c CMP	X4, X12

      (2423) 0x488da0 B.LT	488d00

    (2422) 0x488da4 ADD	X15, X15, #1

    (2422) 0x488da8 ADD	X7, X7, X21

    (2422) 0x488dac ADD	X9, X9, X28

    (2422) 0x488db0 ADD	X3, X3, X21

    (2422) 0x488db4 ADD	X16, X16, X25

    (2422) 0x488db8 ADD	X8, X8, X28

    (2422) 0x488dbc ADD	X6, X6, X28

    (2422) 0x488dc0 CMP	X15, X19

    (2422) 0x488dc4 B.LT	488ce0

  (2421) 0x488dc8 LDR	X1, [SP, #200]

  (2421) 0x488dcc LDR	X0, [SP, #104]

  (2421) 0x488dd0 ADD	X10, X10, X1

  (2421) 0x488dd4 LDR	X1, [SP, #392]

  (2421) 0x488dd8 ADD	X0, X0, #1

  (2421) 0x488ddc STR	X0, [SP, #104]

  (2421) 0x488de0 ADD	X23, X23, X1

  (2421) 0x488de4 LDR	X1, [SP, #400]

  (2421) 0x488de8 ADD	X24, X24, X1

  (2421) 0x488dec LDR	X1, [SP, #408]

  (2421) 0x488df0 ADD	X30, X30, X1

  (2421) 0x488df4 LDR	X1, [SP, #128]

  (2421) 0x488df8 CMP	X0, X1

  (2421) 0x488dfc B.LT	488c74

(2420) 0x488e00 LDR	X0, [SP, #112]

(2420) 0x488e04 LDR	X1, [SP, #512]

(2420) 0x488e08 CMP	X0, X1

(2420) 0x488e0c B.EQ	488a60

(2420) 0x488e10 LDR	X0, [SP, #160]

(2420) 0x488e14 LDR	X1, [SP, #192]

(2420) 0x488e18 ADD	X0, X0, #1

(2420) 0x488e1c STR	X0, [SP, #160]

(2420) 0x488e20 CMP	X1, X0

(2420) 0x488e24 B.LE	488e38

(2420) 0x488e28 LDR	X0, [SP, #112]

(2420) 0x488e2c ADD	X0, X0, #1

(2420) 0x488e30 STR	X0, [SP, #112]

(2420) 0x488e34 B	488b58

(2420) 0x488e38 LDR	X0, [SP, #168]

(2420) 0x488e3c ADD	X0, X0, #1

(2420) 0x488e40 STP	XZR, X0, [SP, #160]

(2420) 0x488e44 B	488e28

Coverage (%)	Name	Source Location	Module
►98.44+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.56+	GOMP_parallel		libgomp.so.1.0.0
○	void Kripke::DispatchHelper<Kr[...]	plugins.hpp:66	exec
○	Kripke::Kernel::sweepSubdomain[...]	ArchLayout.h:155	exec
○	Kripke::SweepSolver(Kripke::Co[...]	SweepSolver.cpp:78	exec
○	Kripke::SteadyStateSolver(Krip[...]	stl_vector.h:678	exec
○	main	kripke.cpp:512	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	iostream:74	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	Collapse.hpp:129-129
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:187
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:88-106
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:369
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/TypedViewBase.hpp:216
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:291,373-377

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 60.00 to 30.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 60.00 to 39.17 cycles (1.53x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	207
nb uops	207
loop length	828
used w registers	0
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	75

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.88 cycles
front end	25.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	20.25	20.25	20.25	20.25	0.50	0.50	0.50	0.50	39.17	38.83	39.00	31.50	31.50
cycles	4.50	4.50	20.25	20.25	20.25	20.25	0.50	0.50	0.50	0.50	39.17	38.83	39.00	31.50	31.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

15.00-60.00

Cycles summary

Front-end	25.88
Dispatch	39.17
DIV/SQRT	15.00-60.00
Overall L1	39.17-60.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	28%
load	29%
store	28%
mul	25%
add-sub	25%
fma	25%
other	29%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	28%
load	29%
store	28%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 60.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 488580

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 488a6c <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 488a6c <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL X21, X21, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
BL 410520 <@plt_start@+0x500>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
BL 410420 <@plt_start@+0x400>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV X9, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
MSUB X0, X9, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 488a80 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X1, X9, X1, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X0, X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 488a6c <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X12, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UDIV X2, X1, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X6, X14, [X12, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MSUB X1, X2, X3, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X10, X15, [X12, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X1, X2, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X2, [X12, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X12, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X12, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X19, [X12, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X5, X11, [X12, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X2, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X12, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X12, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X13, X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X17, [X12, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SDIV X7, X13, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
LDR X8, [X12, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X3, [X12, #640]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X4, [X12, #776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CCMP X10, #1, #0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB X13, X7, X16, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR X2, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #616]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #624]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #712]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #752]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #760]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #888]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X20, [X12, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12, #1088]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #896]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X20, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X12, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X2, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #912]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X20, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X12, #1056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12, #1096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.NE 488a9c <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x51c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X8, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X16, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSINC X7, X7, X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X17, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X8, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X8, X6, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
CMP X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
MUL X6, X6, X2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X7, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
FMOV D4, #2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X24, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X9, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X10, X12, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ORR X11, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X12, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X14, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X9, X1, X4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR XZR, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X4, X0, X4, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X30, X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X15, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X7, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X18, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X18, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X6, X0, X5, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CSEL X8, X8, XZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X0, X0, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STP X8, X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MUL X5, X1, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STP X4, X0, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MUL X0, X1, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X0, X2, X7, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STP X5, X11, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X19, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD SP, SP, #528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4885d4 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X22, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D4, #2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
MUL X25, X6, X2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X9, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X9, X6, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X21, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC X7, X7, X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR XZR, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CSEL X7, X7, XZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X12, X16, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
SUB X11, X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X14, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X28, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X18, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X9, X0, X5, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MUL X5, X1, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X11, X15, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X27, X19, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X5, X14, X8	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X11, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X11, X8, X10	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X10, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X10, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X10, X17, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X5, X1, X4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X26, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X4, X0, X4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
MUL X0, X0, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X10, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X0, X1, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X0, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X0, X2, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X0, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	Collapse.hpp:129-129
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:187
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:88-106
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:369
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/TypedViewBase.hpp:216
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:291,373-377

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 60.00 to 39.17 cycles (1.53x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	207
nb uops	207
loop length	828
used w registers	0
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	75

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.88 cycles
front end	25.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	20.25	20.25	20.25	20.25	0.50	0.50	0.50	0.50	39.17	38.83	39.00	31.50	31.50
cycles	4.50	4.50	20.25	20.25	20.25	20.25	0.50	0.50	0.50	0.50	39.17	38.83	39.00	31.50	31.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

15.00-60.00

Cycles summary

Front-end	25.88
Dispatch	39.17
DIV/SQRT	15.00-60.00
Overall L1	39.17-60.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	28%
load	29%
store	28%
mul	25%
add-sub	25%
fma	25%
other	29%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	28%
load	29%
store	28%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 60.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 488580

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 488a6c <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 488a6c <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL X21, X21, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
BL 410520 <@plt_start@+0x500>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
BL 410420 <@plt_start@+0x400>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV X9, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
MSUB X0, X9, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 488a80 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X1, X9, X1, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X0, X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 488a6c <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X12, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UDIV X2, X1, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X6, X14, [X12, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MSUB X1, X2, X3, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X10, X15, [X12, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X1, X2, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X2, [X12, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X12, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X12, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X19, [X12, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X5, X11, [X12, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X2, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X12, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X12, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X13, X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X17, [X12, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SDIV X7, X13, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
LDR X8, [X12, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X3, [X12, #640]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X4, [X12, #776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CCMP X10, #1, #0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB X13, X7, X16, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR X2, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #616]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #624]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #712]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #752]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #760]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #888]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X20, [X12, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12, #1088]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #896]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X20, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X12, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X2, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #912]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X20, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X12, #1056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12, #1096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.NE 488a9c <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x51c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X8, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X16, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSINC X7, X7, X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X17, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X8, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X8, X6, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
CMP X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
MUL X6, X6, X2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X7, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
FMOV D4, #2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X24, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X9, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X10, X12, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ORR X11, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X12, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X14, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X9, X1, X4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR XZR, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X4, X0, X4, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X30, X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X15, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X7, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X18, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X18, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X6, X0, X5, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CSEL X8, X8, XZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X0, X0, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STP X8, X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MUL X5, X1, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STP X4, X0, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MUL X0, X1, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X0, X2, X7, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STP X5, X11, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X19, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD SP, SP, #528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4885d4 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X22, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D4, #2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
MUL X25, X6, X2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X9, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X9, X6, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X21, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC X7, X7, X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR XZR, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CSEL X7, X7, XZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X12, X16, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
SUB X11, X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X14, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X28, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X18, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X9, X0, X5, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MUL X5, X1, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X11, X15, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X27, X19, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X5, X14, X8	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X11, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X11, X8, X10	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X10, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X10, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X10, X17, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X5, X1, X4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X26, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X4, X0, X4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
MUL X0, X0, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X10, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X0, X1, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X0, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X0, X2, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X0, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)

Name	Coverage (%)	Time (s)
▼std::enable_if–	0.96	1.11
▼Loop 2420 - For.hpp:142-142 - exec–	0.00	0.00
▼Loop 2421 - For.hpp:142-142 - exec–	0.00	0.00
▼Loop 2422 - For.hpp:142-142 - exec–	0.00	0.00
○Loop 2423 - For.hpp:142-142 - exec	0.48	0.54
▼Loop 2424 - For.hpp:142-142 - exec–	0.00	0.00
▼Loop 2425 - For.hpp:142-142 - exec–	0.00	0.00
▼Loop 2426 - For.hpp:142-142 - exec–	0.00	0.00
○Loop 2427 - For.hpp:142-142 - exec	0.48	0.55

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Vectorization

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Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code