| Loop Id: 2213 | Module: exec | Source: For.hpp:142-142 [...] | Coverage: 13.92% |
|---|
| Loop Id: 2213 | Module: exec | Source: For.hpp:142-142 [...] | Coverage: 13.92% |
|---|
0x47d280 LDRSW X1, [X10, X3,LSL #2] |
0x47d284 MOVI D1, #0 |
0x47d288 LDR X2, [X11, X3,LSL #3] |
0x47d28c ADD X0, X1, X2 |
0x47d290 CMP X2, X0 |
0x47d294 B.GE 47d2d8 |
0x47d298 UBFM X2, X2, #61, #60 |
0x47d29c MOVZ X0, #0 |
0x47d2a0 WHILELO P0.D, XZR, X1 |
0x47d2a4 ADD X14, X12, X2 |
0x47d2a8 ADD X2, X13, X2 |
(2216) 0x47d2ac LD1D {Z0.D}, P0/Z, [X14, X0,LSL #3] |
(2216) 0x47d2b0 LD1D {Z2.D}, P0/Z, [X2, X0,LSL #3] |
(2216) 0x47d2b4 MAD Z0.D, P1/M, Z4.D, Z5.D |
(2216) 0x47d2b8 ADD X0, X0, X5 |
(2216) 0x47d2bc ADD Z0.D, Z6.D, Z0.D |
(2216) 0x47d2c0 ADD Z0.D, Z0.D, Z3.D |
(2216) 0x47d2c4 LD1D {Z0.D}, P0/Z, [X6, Z0.D,LSL #3] |
(2216) 0x47d2c8 FMUL Z0.D, Z0.D, Z2.D |
(2216) 0x47d2cc FADDA D1, P0, D1, Z0.D |
(2216) 0x47d2d0 WHILELO P0.D, X0, X1 |
(2216) 0x47d2d4 B.NE 47d2ac |
0x47d2d8 LDR D2, [X7, X3,LSL #3] |
0x47d2dc LDR D0, [X4, X3,LSL #3] |
0x47d2e0 FMADD D0, D2, D1, D0 |
0x47d2e4 STR D0, [X4, X3,LSL #3] |
0x47d2e8 ADD X3, X3, #1 |
0x47d2ec CMP X3, X9 |
0x47d2f0 B.LT 47d280 |
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp: 87 - 97 |
-------------------------------------------------------------------------------- |
87: MixElem mix_start = zone_to_mixelem(z); |
88: MixElem mix_stop = mix_start + zone_to_num_mixelem(z); |
89: |
90: double sigs_z = 0.0; |
91: for(MixElem mix = mix_start;mix < mix_stop;++ mix){ |
92: Material mat = mixelem_to_material(mix); |
93: double fraction = mixelem_to_fraction(mix); |
94: |
95: sigs_z += sigs(mat, n, global_g, global_gp) * fraction; |
96: } |
97: phi_out(nm, g, z) += sigs_z * phi(nm, gp, z); |
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp: 142 - 142 |
-------------------------------------------------------------------------------- |
142: for (decltype(distance_it) i = 0; i < distance_it; ++i) |
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 369 - 369 |
-------------------------------------------------------------------------------- |
369: return Ret {lhs} + rhs; |
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp: 109 - 109 |
-------------------------------------------------------------------------------- |
109: return TYPE(value + a); |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►98.44+ | omp_fulfill_event | libgomp.so.1.0.0 | |
| ○ | start_thread | libc.so.6 | |
| ○ | thread_start | libc.so.6 | |
| ►1.56+ | GOMP_parallel | libgomp.so.1.0.0 | |
| ○ | void Kripke::DispatchHelper<Kr[...] | Collapse.hpp:129 | exec |
| ○ | Kripke::Kernel::scattering(Kri[...] | ArchLayout.h:155 | exec |
| ○ | Kripke::SteadyStateSolver(Krip[...] | SteadyStateSolver.cpp:73 | exec |
| ○ | main | kripke.cpp:512 | exec |
| ○ | __libc_start_call_main | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | iostream:74 | exec |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.75 |
| CQA speedup if FP arith vectorized | 1.11 |
| CQA speedup if fully vectorized | 5.03 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.17 |
| Bottlenecks | |
| Function | std::enable_if |
| Source | Scattering.cpp:87-91,Scattering.cpp:97-97,For.hpp:142-142,IndexValue.hpp:109-109 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 2.04 |
| CQA cycles if no scalar integer | 1.17 |
| CQA cycles if FP arith vectorized | 1.83 |
| CQA cycles if fully vectorized | 0.41 |
| Front-end cycles | 1.94 |
| P0 cycles | 1.00 |
| P1 cycles | 1.00 |
| P2 cycles | 1.63 |
| P3 cycles | 1.63 |
| P4 cycles | 1.63 |
| P5 cycles | 1.63 |
| P6 cycles | 0.75 |
| P7 cycles | 0.75 |
| P8 cycles | 0.75 |
| P9 cycles | 0.75 |
| P10 cycles | 1.83 |
| P11 cycles | 1.50 |
| P12 cycles | 1.67 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 15.50 |
| Nb uops | 15.50 |
| Nb loads | NA |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.98 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 1.48 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 3.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 1.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 23.82 |
| Vector-efficiency ratio load | 21.88 |
| Vector-efficiency ratio store | 25.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 25.00 |
| Vector-efficiency ratio fma | 25.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 25.00 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.93 |
| CQA speedup if FP arith vectorized | 1.23 |
| CQA speedup if fully vectorized | 5.14 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.23 |
| Bottlenecks | micro-operation queue, P2, P3, P4, P5, |
| Function | std::enable_if |
| Source | Scattering.cpp:87-91,Scattering.cpp:97-97,For.hpp:142-142,IndexValue.hpp:109-109 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 2.25 |
| CQA cycles if no scalar integer | 1.17 |
| CQA cycles if FP arith vectorized | 1.83 |
| CQA cycles if fully vectorized | 0.44 |
| Front-end cycles | 2.25 |
| P0 cycles | 1.00 |
| P1 cycles | 1.00 |
| P2 cycles | 2.25 |
| P3 cycles | 2.25 |
| P4 cycles | 2.25 |
| P5 cycles | 2.25 |
| P6 cycles | 0.75 |
| P7 cycles | 0.75 |
| P8 cycles | 0.75 |
| P9 cycles | 0.75 |
| P10 cycles | 1.83 |
| P11 cycles | 1.50 |
| P12 cycles | 1.67 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 18.00 |
| Nb uops | 18.00 |
| Nb loads | NA |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.89 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 1.33 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 3.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 1.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 24.04 |
| Vector-efficiency ratio load | 21.88 |
| Vector-efficiency ratio store | 25.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 25.00 |
| Vector-efficiency ratio fma | 25.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 25.00 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.57 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 4.89 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.10 |
| Bottlenecks | P10, |
| Function | std::enable_if |
| Source | Scattering.cpp:87-91,Scattering.cpp:97-97,For.hpp:142-142,IndexValue.hpp:109-109 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 1.83 |
| CQA cycles if no scalar integer | 1.17 |
| CQA cycles if FP arith vectorized | 1.83 |
| CQA cycles if fully vectorized | 0.38 |
| Front-end cycles | 1.63 |
| P0 cycles | 1.00 |
| P1 cycles | 1.00 |
| P2 cycles | 1.00 |
| P3 cycles | 1.00 |
| P4 cycles | 1.00 |
| P5 cycles | 1.00 |
| P6 cycles | 0.75 |
| P7 cycles | 0.75 |
| P8 cycles | 0.75 |
| P9 cycles | 0.75 |
| P10 cycles | 1.83 |
| P11 cycles | 1.50 |
| P12 cycles | 1.67 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 13.00 |
| Nb uops | 13.00 |
| Nb loads | NA |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 1.09 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 1.64 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 3.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 23.61 |
| Vector-efficiency ratio load | 21.88 |
| Vector-efficiency ratio store | 25.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 25.00 |
| Vector-efficiency ratio fma | 25.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 25.00 |
| Path / |
 |
| nb instructions | 15.50 |
| nb uops | 15.50 |
| loop length | 62 |
| used w registers | 0 |
| used x registers | 11 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 3 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 1.94 cycles |
| front end | 1.94 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 1.63 | 1.63 | 1.63 | 1.63 | 0.75 | 0.75 | 0.75 | 0.75 | 1.83 | 1.50 | 1.67 | 0.00 | 0.00 |
| cycles | 1.00 | 1.00 | 1.63 | 1.63 | 1.63 | 1.63 | 0.75 | 0.75 | 0.75 | 0.75 | 1.83 | 1.50 | 1.67 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 1.94 |
| Dispatch | 2.04 |
| Data deps. | 1.00 |
| Overall L1 | 2.04 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 23% |
| load | 21% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 25% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 25% |
| all | 25% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 25% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 23% |
| load | 21% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 25% |
| fma | 25% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
|
| nb instructions | 18 |
| nb uops | 18 |
| loop length | 72 |
| used w registers | 0 |
| used x registers | 13 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 3 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 2.25 cycles |
| front end | 2.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 2.25 | 2.25 | 2.25 | 2.25 | 0.75 | 0.75 | 0.75 | 0.75 | 1.83 | 1.50 | 1.67 | 0.00 | 0.00 |
| cycles | 1.00 | 1.00 | 2.25 | 2.25 | 2.25 | 2.25 | 0.75 | 0.75 | 0.75 | 0.75 | 1.83 | 1.50 | 1.67 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 2.25 |
| Dispatch | 2.25 |
| Data deps. | 1.00 |
| Overall L1 | 2.25 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 23% |
| load | 21% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 25% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 25% |
| all | 25% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 25% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 24% |
| load | 21% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 25% |
| fma | 25% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDRSW X1, [X10, X3,LSL #2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| MOVI D1, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| LDR X2, [X11, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| ADD X0, X1, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| CMP X2, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.GE 47d2d8 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_5GroupElPSX_EElEES10_NSP_INSR_INSS_4ZoneElPS11_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14ScatteringSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdES1H_RKNSS_4Core3SetES1L_S1L_RNS1I_5FieldIdJST_SX_S11_EEES1O_RNS1M_IdJNSS_8MaterialENSS_8LegendreENSS_11GlobalGroupES1R_EEERNS1M_INSS_7MixElemEJS11_EEERNS1M_IiJS11_EEERNS1M_IS1P_JS1U_EEERNS1M_IdJS1U_EEERNS1M_IS1Q_JST_EEEEUlST_SX_SX_S11_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS29_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS2E_3ref5rem_sIS1G_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1G_._omp_fn.0+0x1d8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| UBFM X2, X2, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| MOVZ X0, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| WHILELO P0.D, XZR, X1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| ADD X14, X12, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X2, X13, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDR D2, [X7, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| LDR D0, [X4, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FMADD D0, D2, D1, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| STR D0, [X4, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADD X3, X3, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X3, X9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| B.LT 47d280 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_5GroupElPSX_EElEES10_NSP_INSR_INSS_4ZoneElPS11_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14ScatteringSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdES1H_RKNSS_4Core3SetES1L_S1L_RNS1I_5FieldIdJST_SX_S11_EEES1O_RNS1M_IdJNSS_8MaterialENSS_8LegendreENSS_11GlobalGroupES1R_EEERNS1M_INSS_7MixElemEJS11_EEERNS1M_IiJS11_EEERNS1M_IS1P_JS1U_EEERNS1M_IdJS1U_EEERNS1M_IS1Q_JST_EEEEUlST_SX_SX_S11_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS29_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS2E_3ref5rem_sIS1G_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1G_._omp_fn.0+0x180> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
|
| nb instructions | 13 |
| nb uops | 13 |
| loop length | 52 |
| used w registers | 0 |
| used x registers | 9 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 3 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 1.63 cycles |
| front end | 1.63 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 0.75 | 0.75 | 0.75 | 0.75 | 1.83 | 1.50 | 1.67 | 0.00 | 0.00 |
| cycles | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 0.75 | 0.75 | 0.75 | 0.75 | 1.83 | 1.50 | 1.67 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 1.63 |
| Dispatch | 1.83 |
| Data deps. | 1.00 |
| Overall L1 | 1.83 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 23% |
| load | 21% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 25% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 25% |
| all | 25% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 25% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 23% |
| load | 21% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 25% |
| fma | 25% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDRSW X1, [X10, X3,LSL #2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| MOVI D1, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| LDR X2, [X11, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| ADD X0, X1, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| CMP X2, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.GE 47d2d8 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_5GroupElPSX_EElEES10_NSP_INSR_INSS_4ZoneElPS11_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14ScatteringSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdES1H_RKNSS_4Core3SetES1L_S1L_RNS1I_5FieldIdJST_SX_S11_EEES1O_RNS1M_IdJNSS_8MaterialENSS_8LegendreENSS_11GlobalGroupES1R_EEERNS1M_INSS_7MixElemEJS11_EEERNS1M_IiJS11_EEERNS1M_IS1P_JS1U_EEERNS1M_IdJS1U_EEERNS1M_IS1Q_JST_EEEEUlST_SX_SX_S11_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS29_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS2E_3ref5rem_sIS1G_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1G_._omp_fn.0+0x1d8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D2, [X7, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| LDR D0, [X4, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FMADD D0, D2, D1, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| STR D0, [X4, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADD X3, X3, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X3, X9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| B.LT 47d280 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_5GroupElPSX_EElEES10_NSP_INSR_INSS_4ZoneElPS11_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14ScatteringSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdES1H_RKNSS_4Core3SetES1L_S1L_RNS1I_5FieldIdJST_SX_S11_EEES1O_RNS1M_IdJNSS_8MaterialENSS_8LegendreENSS_11GlobalGroupES1R_EEERNS1M_INSS_7MixElemEJS11_EEERNS1M_IiJS11_EEERNS1M_IS1P_JS1U_EEERNS1M_IdJS1U_EEERNS1M_IS1Q_JST_EEEEUlST_SX_SX_S11_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS29_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS2E_3ref5rem_sIS1G_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1G_._omp_fn.0+0x180> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |