OV - exec - Function std::enable_if<camp::concepts::all_of<camp::concepts::metalib::negate_t<RAJA::internal::loop_data_has_reducers<camp::type::cv::rem_s<camp::type::ref::rem_s<RAJA::internal::LoopData<camp::tuple<RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Direction, long, Kripke::Direction*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Group, long, Kripke::Group*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Zone, long, Kripke::Zone*>, long> >, camp::tuple<>, camp::resources::v1::Host, PopulationSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field<double, Kripke::Direction, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Direction>&, Kripke::Core::Field<double, Kripke::Zone>&, double*) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&>::type>::type> > >::value, void>::type RAJA::internal::StatementExecutor<RAJA::statement::Collapse<RAJA::omp_parallel_collapse_exec, camp::int_seq<long, 0l, 1l>, RAJA::statement::For<2l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > >, RAJA::internal::LoopTypes<camp::list<void, void, void>, camp::list<void, void, void> > >::exec<RAJA::internal::LoopData<camp::tuple<RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Direction, long, Kripke::Direction*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Group, long, Kripke::Group*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Zone, long, Kripke::Zone*>, long> >, camp::tuple<>, camp::resources::v1::Host, PopulationSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field<double, Kripke::Direction, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Direction>&, Kripke::Core::Field<double, Kripke::Zone>&, double*) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData<camp::tuple<RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Direction, long, Kripke::Direction*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Group, long, Kripke::Group*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Zone, long, Kripke::Zone*>, long> >, camp::tuple<>, camp::resources::v1::Host, PopulationSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field<double, Kripke::Direction, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Direction>&, Kripke::Core::Field<double, Kripke::Zone>&, double*) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&) [clone ._omp

	Function: std::enable_if<camp::concepts::all_of<camp::concepts::metalib::negate_t<RAJA::internal::lo ...	Module: exec	Source: Collapse.hpp:129-129 [...]	Coverage (incl. loops): 0.29% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 187 - 187

--------------------------------------------------------------------------------

187:     return sum<IdxLin>((RangeInts == stride_one_dim

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp: 142 - 142

--------------------------------------------------------------------------------

142:     for (decltype(distance_it) i = 0; i < distance_it; ++i)

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/reduce.hpp: 46 - 60

--------------------------------------------------------------------------------

46: class ReduceOMP

[...]

60: #pragma omp critical(ompReduceCritical)

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 129 - 129

--------------------------------------------------------------------------------

129: #pragma omp parallel for private(i0, i1) firstprivate(privatizer)              \

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp: 56 - 58

--------------------------------------------------------------------------------

56:         KRIPKE_LAMBDA (Direction d, Group g, Zone z) {

57:

58:           part_red += w(d) * psi(d,g,z) * volume(z);

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 369 - 369

--------------------------------------------------------------------------------

369:     return Ret {lhs} + rhs;

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp: 78 - 318

--------------------------------------------------------------------------------

78:     val = operator_type::operator()(val, v);

[...]

317:       : parent {other.parent ? other.parent : &other},

318:         identity {other.identity},

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/TypedViewBase.hpp: 216 - 216

--------------------------------------------------------------------------------

216:     return data[stripIndexType(layout(args...))];

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/internal/LoopData.hpp: 152 - 152

--------------------------------------------------------------------------------

152:   constexpr LoopData(LoopData const&) = default;

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp: 232 - 291

--------------------------------------------------------------------------------

232:     return val - rhs.val;

[...]

291:     return value_type(val + rhs);

0x493060 STP	X29, X30, [SP, #928]!

0x493064 ADD	X29, SP, #0

0x493068 STP	X19, X20, [SP, #16]

0x49306c STP	X25, X26, [SP, #64]

0x493070 LDP	X20, X26, [X0, #8]

0x493074 STP	X21, X22, [SP, #32]

0x493078 LDR	X21, [X26, #56]

0x49307c STP	X23, X24, [SP, #48]

0x493080 LDR	X22, [X26]

0x493084 LDP	X19, X24, [X26, #32]

0x493088 CMP	X21, #0

0x49308c LDR	X23, [X26, #16]

0x493090 STR	X27, [SP, #80]

0x493094 LDR	X27, [X0]

0x493098 ADD	X0, X26, #56

0x49309c CSEL	X21, X21, X0, #1

0x4930a0 STR	D8, [SP, #88]

0x4930a4 LDR	D8, [X26, #64]

0x4930a8 CMP	X27, #0

0x4930ac B.LE	493354

0x4930b0 CMP	X20, #0

0x4930b4 B.LE	493354

0x4930b8 BL	4101e0

0x4930bc MUL	X27, X27, X20

0x4930c0 SBFM	X25, X0, #0, #31

0x4930c4 BL	4101f0

0x4930c8 SBFM	X4, X0, #0, #31

0x4930cc UDIV	X8, X27, X25

0x4930d0 MSUB	X1, X8, X25, X27

0x4930d4 CMP	X4, X1

0x4930d8 B.CC	4933ac

0x4930dc MADD	X2, X8, X4, X1

0x4930e0 ADD	X3, X8, X2

0x4930e4 CMP	X2, X3

0x4930e8 B.CS	493354

0x4930ec UDIV	X10, X2, X20

0x4930f0 LDR	X12, [X26, #224]

0x4930f4 SUB	X6, X24, X19

0x4930f8 LDP	X15, X14, [X26, #152]

0x4930fc CMP	X6, #0

0x493100 CSINC	X13, X6, XZR, #12

0x493104 UBFM	X7, X13, #1, #63

0x493108 SUB	X8, X8, #1

0x49310c CSEL	X17, X6, XZR, #10

0x493110 UBFM	X7, X7, #60, #59

0x493114 AND	X11, X13, #0xfffffffe

0x493118 MOVZ	X5, #0

0x49311c LDR	X16, [X26, #80]

0x493120 ADD	X3, X12, X19,LSL #3

0x493124 LDR	X9, [X26, #120]

0x493128 MSUB	X4, X10, X20, X2

(2137) 0x49312c CMP	X6, #0

(2137) 0x493130 B.LE	493338

(2137) 0x493134 ADD	X18, X4, X23

(2137) 0x493138 ADD	X30, X10, X22

(2137) 0x49313c MUL	X26, X18, X14

(2137) 0x493140 LDR	D2, [X16, X30,LSL #3]

(2137) 0x493144 MADD	X27, X30, X15, X26

(2137) 0x493148 CMP	X6, #2

(2137) 0x49314c B.LE	4933a4

(2137) 0x493150 SUB	X0, X7, #16

(2137) 0x493154 ADD	X25, X27, X19

(2137) 0x493158 DUP	V1.2D, V2.D[0]

(2137) 0x49315c UBFM	X1, X0, #4, #63

(2137) 0x493160 UBFM	X2, X25, #61, #60

(2137) 0x493164 MOVI	V0.2D, #0

(2137) 0x493168 ADD	X18, X1, #1

(2137) 0x49316c ADD	X24, X9, X2

(2137) 0x493170 ANDS	X30, X18, #0x7

(2137) 0x493174 MOVZ	X0, #0

(2137) 0x493178 B.EQ	493240

(2137) 0x49317c CMP	X30, #1

(2137) 0x493180 B.EQ	493224

(2137) 0x493184 CMP	X30, #2

(2137) 0x493188 B.EQ	493210

(2137) 0x49318c CMP	X30, #3

(2137) 0x493190 B.EQ	4931fc

(2137) 0x493194 CMP	X30, #4

(2137) 0x493198 B.EQ	4931e8

(2137) 0x49319c CMP	X30, #5

(2137) 0x4931a0 B.EQ	4931d4

(2137) 0x4931a4 CMP	X30, #6

(2137) 0x4931a8 B.EQ	4931c0

(2137) 0x4931ac LDR	Q4, [X9, X2]

(2137) 0x4931b0 MOVZ	X0, #16

(2137) 0x4931b4 LDR	Q3, [X3]

(2137) 0x4931b8 FMUL	V5.2D, V3.2D, V4.2D

(2137) 0x4931bc FMLA	V0.2D, V1.2D, V5.2D

(2137) 0x4931c0 LDR	Q6, [X3, X0]

(2137) 0x4931c4 LDR	Q7, [X24, X0]

(2137) 0x4931c8 ADD	X0, X0, #16

(2137) 0x4931cc FMUL	V16.2D, V6.2D, V7.2D

(2137) 0x4931d0 FMLA	V0.2D, V1.2D, V16.2D

(2137) 0x4931d4 LDR	Q17, [X3, X0]

(2137) 0x4931d8 LDR	Q18, [X24, X0]

(2137) 0x4931dc ADD	X0, X0, #16

(2137) 0x4931e0 FMUL	V19.2D, V17.2D, V18.2D

(2137) 0x4931e4 FMLA	V0.2D, V1.2D, V19.2D

(2137) 0x4931e8 LDR	Q20, [X3, X0]

(2137) 0x4931ec LDR	Q21, [X24, X0]

(2137) 0x4931f0 ADD	X0, X0, #16

(2137) 0x4931f4 FMUL	V22.2D, V20.2D, V21.2D

(2137) 0x4931f8 FMLA	V0.2D, V1.2D, V22.2D

(2137) 0x4931fc LDR	Q23, [X3, X0]

(2137) 0x493200 LDR	Q24, [X24, X0]

(2137) 0x493204 ADD	X0, X0, #16

(2137) 0x493208 FMUL	V25.2D, V23.2D, V24.2D

(2137) 0x49320c FMLA	V0.2D, V1.2D, V25.2D

(2137) 0x493210 LDR	Q26, [X3, X0]

(2137) 0x493214 LDR	Q27, [X24, X0]

(2137) 0x493218 ADD	X0, X0, #16

(2137) 0x49321c FMUL	V28.2D, V26.2D, V27.2D

(2137) 0x493220 FMLA	V0.2D, V1.2D, V28.2D

(2137) 0x493224 LDR	Q29, [X3, X0]

(2137) 0x493228 LDR	Q30, [X24, X0]

(2137) 0x49322c ADD	X0, X0, #16

(2137) 0x493230 FMUL	V31.2D, V29.2D, V30.2D

(2137) 0x493234 FMLA	V0.2D, V1.2D, V31.2D

(2137) 0x493238 CMP	X7, X0

(2137) 0x49323c B.EQ	4932e8

  (2138) 0x493240 LDR	Q6, [X3, X0]

  (2138) 0x493244 ADD	X25, X0, #16

  (2138) 0x493248 ADD	X2, X0, #32

  (2138) 0x49324c ADD	X1, X0, #48

  (2138) 0x493250 ADD	X26, X0, #64

  (2138) 0x493254 LDR	Q4, [X24, X0]

  (2138) 0x493258 ADD	X30, X0, #80

  (2138) 0x49325c ADD	X18, X0, #96

  (2138) 0x493260 LDR	Q5, [X3, X25]

  (2138) 0x493264 LDR	Q3, [X24, X25]

  (2138) 0x493268 ADD	X25, X0, #112

  (2138) 0x49326c ADD	X0, X0, #128

  (2138) 0x493270 FMUL	V16.2D, V6.2D, V4.2D

  (2138) 0x493274 LDR	Q17, [X3, X2]

  (2138) 0x493278 LDR	Q7, [X24, X2]

  (2138) 0x49327c FMUL	V18.2D, V5.2D, V3.2D

  (2138) 0x493280 LDR	Q19, [X3, X1]

  (2138) 0x493284 FMLA	V0.2D, V1.2D, V16.2D

  (2138) 0x493288 LDR	Q20, [X24, X1]

  (2138) 0x49328c FMUL	V21.2D, V17.2D, V7.2D

  (2138) 0x493290 LDR	Q22, [X3, X26]

  (2138) 0x493294 FMLA	V0.2D, V1.2D, V18.2D

  (2138) 0x493298 LDR	Q23, [X24, X26]

  (2138) 0x49329c LDR	Q24, [X3, X30]

  (2138) 0x4932a0 FMUL	V25.2D, V19.2D, V20.2D

  (2138) 0x4932a4 LDR	Q26, [X24, X30]

  (2138) 0x4932a8 FMLA	V0.2D, V1.2D, V21.2D

  (2138) 0x4932ac LDR	Q27, [X3, X18]

  (2138) 0x4932b0 FMUL	V28.2D, V22.2D, V23.2D

  (2138) 0x4932b4 LDR	Q29, [X24, X18]

  (2138) 0x4932b8 FMLA	V0.2D, V1.2D, V25.2D

  (2138) 0x4932bc LDR	Q30, [X3, X25]

  (2138) 0x4932c0 LDR	Q31, [X24, X25]

  (2138) 0x4932c4 FMUL	V6.2D, V24.2D, V26.2D

  (2138) 0x4932c8 FMUL	V4.2D, V27.2D, V29.2D

  (2138) 0x4932cc FMLA	V0.2D, V1.2D, V28.2D

  (2138) 0x4932d0 FMUL	V5.2D, V30.2D, V31.2D

  (2138) 0x4932d4 FMLA	V0.2D, V1.2D, V6.2D

  (2138) 0x4932d8 FMLA	V0.2D, V1.2D, V4.2D

  (2138) 0x4932dc FMLA	V0.2D, V1.2D, V5.2D

  (2138) 0x4932e0 CMP	X7, X0

  (2138) 0x4932e4 B.NE	493240

(2137) 0x4932e8 ORR	X24, XZR, X11

(2137) 0x4932ec FADDP	D1, V0.2D

(2137) 0x4932f0 FADD	D8, D8, D1

(2137) 0x4932f4 CMP	X11, X13

(2137) 0x4932f8 B.EQ	493338

(2137) 0x4932fc ADD	X1, X19, X24

(2137) 0x493300 ADD	X24, X24, #1

(2137) 0x493304 ADD	X0, X27, X1

(2137) 0x493308 LDR	D0, [X12, X1,LSL #3]

(2137) 0x49330c LDR	D3, [X9, X0,LSL #3]

(2137) 0x493310 FMUL	D16, D2, D0

(2137) 0x493314 FMADD	D8, D3, D16, D8

(2137) 0x493318 CMP	X17, X24

(2137) 0x49331c B.LE	493338

(2137) 0x493320 ADD	X26, X19, X24

(2137) 0x493324 ADD	X27, X27, X26

(2137) 0x493328 LDR	D17, [X12, X26,LSL #3]

(2137) 0x49332c LDR	D7, [X9, X27,LSL #3]

(2137) 0x493330 FMUL	D2, D2, D17

(2137) 0x493334 FMADD	D8, D2, D7, D8

(2137) 0x493338 CMP	X5, X8

(2137) 0x49333c B.EQ	493354

(2137) 0x493340 ADD	X4, X4, #1

(2137) 0x493344 CMP	X20, X4

(2137) 0x493348 B.LE	493394

(2137) 0x49334c ADD	X5, X5, #1

(2137) 0x493350 B	49312c

0x493354 ADRP	X2,

0x493358 LDR	X25, [X2, #3584]

0x49335c ORR	X0, XZR, X25

0x493360 BL	410350

0x493364 LDR	D18, [X21, #16]

0x493368 ORR	X0, XZR, X25

0x49336c LDP	X19, X20, [SP, #16]

0x493370 LDP	X23, X24, [SP, #48]

0x493374 FADD	D19, D18, D8

0x493378 LDP	X25, X26, [SP, #64]

0x49337c LDR	X27, [SP, #80]

0x493380 LDR	D8, [SP, #88]

0x493384 STR	D19, [X21, #16]

0x493388 LDP	X21, X22, [SP, #32]

0x49338c LDP	X29, X30, [SP], #96

0x493390 B	410190

(2137) 0x493394 ADD	X10, X10, #1

(2137) 0x493398 MOVZ	X4, #0

(2137) 0x49339c ADD	X5, X5, #1

(2137) 0x4933a0 B	49312c

(2137) 0x4933a4 MOVZ	X24, #0

(2137) 0x4933a8 B	4932fc

0x4933ac ADD	X8, X8, #1

0x4933b0 MOVZ	X1, #0

0x4933b4 B	4930dc

0x4933b8 HINT	#0

0x4933bc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.54+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.46+	GOMP_parallel		libgomp.so.1.0.0
○	void PopulationSdom::operator([...]	Population.cpp:56	exec
○	Kripke::Kernel::population(Kri[...]	ArchLayout.h:193	exec
○	Kripke::SteadyStateSolver(Krip[...]	SteadyStateSolver.cpp:108	exec
○	main	new_allocator.h:79	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	iostream:74	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_9

Source file and lines	Collapse.hpp:129-129
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:187
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/reduce.hpp:46,60
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp:56-58
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:369
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp:78,317-318
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/TypedViewBase.hpp:216
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/internal/LoopData.hpp:152
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:232,291

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 40.00 to 20.00 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 33% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 40.00 to 30.00 cycles (1.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 9.33 cycles (4.29x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp:318
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp:318
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/reduce.hpp:60

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function does not load or store any data.

General properties

nb instructions	72
nb uops	70
loop length	288
used w registers	0
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.75 cycles
front end	8.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	9.00	9.00	9.00	9.00	1.00	1.00	0.50	0.50	9.33	9.33	9.33	3.00	3.00
cycles	4.50	4.50	9.00	9.00	9.00	9.00	1.00	1.00	0.50	0.50	9.33	9.33	9.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	8.75
Dispatch	9.33
DIV/SQRT	10.00-40.00
Overall L1	10.00-40.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	33%
load	32%
store	40%
mul	25%
add-sub	25%
fma	25%
other	34%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	33%
load	32%
store	40%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	35%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 493060

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X20, X26, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X26, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X22, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X24, [X26, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X23, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X26, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X21, X21, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D8, [SP, #88]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D8, [X26, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 493354 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1X_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS22_3ref5rem_sIS1F_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1F_._omp_fn.0+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 493354 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1X_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS22_3ref5rem_sIS1F_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1F_._omp_fn.0+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4101e0 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL X27, X27, X20	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
SBFM X25, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X4, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
UDIV X8, X27, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X1, X8, X25, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 4933ac <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1X_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS22_3ref5rem_sIS1F_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1F_._omp_fn.0+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X2, X8, X4, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X3, X8, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X2, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 493354 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1X_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS22_3ref5rem_sIS1F_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1F_._omp_fn.0+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV X10, X2, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
LDR X12, [X26, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X6, X24, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X15, X14, [X26, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSINC X13, X6, XZR, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X7, X13, #1, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X17, X6, XZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X7, X7, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X11, X13, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X16, [X26, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X3, X12, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X26, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB X4, X10, X20, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADRP X2, <4ff354>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X2, #3584]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410350 <@plt_start@+0x330>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D18, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORR X0, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
FADD D19, D18, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D19, [X21, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 410190 <@plt_start@+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4930dc <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1X_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS22_3ref5rem_sIS1F_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1F_._omp_fn.0+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_9

Source file and lines	Collapse.hpp:129-129
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:187
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/reduce.hpp:46,60
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp:56-58
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:369
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp:78,317-318
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/TypedViewBase.hpp:216
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/internal/LoopData.hpp:152
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:232,291

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 9.33 cycles (4.29x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp:318
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp:318
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/reduce.hpp:60

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function does not load or store any data.

General properties

nb instructions	72
nb uops	70
loop length	288
used w registers	0
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.75 cycles
front end	8.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	9.00	9.00	9.00	9.00	1.00	1.00	0.50	0.50	9.33	9.33	9.33	3.00	3.00
cycles	4.50	4.50	9.00	9.00	9.00	9.00	1.00	1.00	0.50	0.50	9.33	9.33	9.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	8.75
Dispatch	9.33
DIV/SQRT	10.00-40.00
Overall L1	10.00-40.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	33%
load	32%
store	40%
mul	25%
add-sub	25%
fma	25%
other	34%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	33%
load	32%
store	40%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	35%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 493060

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X20, X26, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X26, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X22, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X24, [X26, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X23, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X26, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X21, X21, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D8, [SP, #88]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D8, [X26, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 493354 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1X_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS22_3ref5rem_sIS1F_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1F_._omp_fn.0+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 493354 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1X_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS22_3ref5rem_sIS1F_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1F_._omp_fn.0+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4101e0 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL X27, X27, X20	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
SBFM X25, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X4, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
UDIV X8, X27, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X1, X8, X25, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 4933ac <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1X_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS22_3ref5rem_sIS1F_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1F_._omp_fn.0+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X2, X8, X4, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X3, X8, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X2, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 493354 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1X_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS22_3ref5rem_sIS1F_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1F_._omp_fn.0+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV X10, X2, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
LDR X12, [X26, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X6, X24, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X15, X14, [X26, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSINC X13, X6, XZR, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X7, X13, #1, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X17, X6, XZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X7, X7, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X11, X13, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X16, [X26, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X3, X12, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X26, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB X4, X10, X20, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADRP X2, <4ff354>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X2, #3584]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410350 <@plt_start@+0x330>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D18, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORR X0, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
FADD D19, D18, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D19, [X21, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 410190 <@plt_start@+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4930dc <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1X_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS22_3ref5rem_sIS1F_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1F_._omp_fn.0+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼std::enable_if–	0.29	0.18
▼Loop 2137 - For.hpp:142-142 - exec–	0.00	0.00
○Loop 2138 - For.hpp:142-142 - exec	0.29	0.17

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Matching between your function (in the source code) and the binary function

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Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

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ASM code