OV - exec - Function std::enable_if<camp::concepts::all_of<camp::concepts::metalib::negate_t<RAJA::internal::loop_data_has_reducers<camp::type::cv::rem_s<camp::type::ref::rem_s<RAJA::internal::LoopData<camp::tuple<RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Direction, long, Kripke::Direction*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Group, long, Kripke::Group*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneK, long, Kripke::ZoneK*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneJ, long, Kripke::ZoneJ*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneI, long, Kripke::ZoneI*>, long> >, camp::tuple<>, camp::resources::v1::Host, SweepSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&>::type>::type> > >::value, void>::type RAJA::internal::StatementExecutor<RAJA::statement::Collapse<RAJA::omp_parallel_collapse_exec, camp::int_seq<long, 0l, 1l>, RAJA::statement::For<2l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<4l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > > >, RAJA::internal::LoopTypes<camp::list<void, void, void, void, void>, camp::list<void, void, void, void, void> > >::exec<RAJA::internal::LoopData<camp::tuple<RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Direction, long, Kripke::Direction*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Group, long, Kripke::Group*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneK, long, Kripke::ZoneK*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneJ, long, Kripke::ZoneJ*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneI, long, Kripke::ZoneI*>, long> >, camp::tuple<>, camp::resources::v1::Host, SweepSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&>(RAJA::internal::LoopData<camp::tuple<RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Direction, long, Kripke::Direction*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Group, long, Kripke::Group*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneK, long, Kripke::ZoneK*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneJ, long, Kripke::ZoneJ*>, long>, RAJA::Span<RAJA::Iterators::strided_numeric_iterator<Kripke::ZoneI, long, Kripke::ZoneI*>, long> >, camp::tuple<>, camp::resources::v1::Host, SweepSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&) [clone ._omp

	Function: std::enable_if<camp::concepts::all_of<camp::concepts::metalib::negate_t<RAJA::internal::lo ...	Module: exec	Source: Collapse.hpp:129-129 [...]	Coverage (incl. loops): 1.60% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 187 - 187

--------------------------------------------------------------------------------

187:     return sum<IdxLin>((RangeInts == stride_one_dim

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp: 142 - 142

--------------------------------------------------------------------------------

142:     for (decltype(distance_it) i = 0; i < distance_it; ++i)

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 129 - 129

--------------------------------------------------------------------------------

129: #pragma omp parallel for private(i0, i1) firstprivate(privatizer)              \

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp: 88 - 106

--------------------------------------------------------------------------------

88:             double xcos_dxi = 2.0 * xcos(d) / dx(i);

89:             double ycos_dyj = 2.0 * ycos(d) / dy(j);

90:             double zcos_dzk = 2.0 * zcos(d) / dz(k);

91:

92:             Zone z(zone_layout(*k, *j, *i));

93:

94:             /* Calculate new zonal flux */

95:             double psi_d_g_z = (rhs(d,g,z)

96:                 + psi_lf(d, g, j, k) * xcos_dxi

97:                 + psi_fr(d, g, i, k) * ycos_dyj

98:                 + psi_bo(d, g, i, j) * zcos_dzk)

99:                 / (xcos_dxi + ycos_dyj + zcos_dzk + sigt(g, z));

100:

101:             psi(d, g, z) = psi_d_g_z;

102:

103:             /* Apply diamond-difference relationships */

104:             psi_lf(d, g, j, k) = 2.0 * psi_d_g_z - psi_lf(d, g, j, k);

105:             psi_fr(d, g, i, k) = 2.0 * psi_d_g_z - psi_fr(d, g, i, k);

106:             psi_bo(d, g, i, j) = 2.0 * psi_d_g_z - psi_bo(d, g, i, j);

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 369 - 369

--------------------------------------------------------------------------------

369:     return Ret {lhs} + rhs;

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/TypedViewBase.hpp: 216 - 216

--------------------------------------------------------------------------------

216:     return data[stripIndexType(layout(args...))];

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp: 291 - 377

--------------------------------------------------------------------------------

291:     return value_type(val + rhs);

[...]

373:     difference_type diff = (static_cast<difference_type>(val) -

374:                             (static_cast<difference_type>(rhs.val)));

375:

376:     return (diff % stride != difference_type {0})

377:                ? (difference_type {1} + diff / stride)

0x4a6b80 SUB	SP, SP, #528

0x4a6b84 STP	X29, X30, [SP]

0x4a6b88 ADD	X29, SP, #0

0x4a6b8c STP	X19, X20, [SP, #16]

0x4a6b90 ORR	X20, XZR, X0

0x4a6b94 STP	X21, X22, [SP, #32]

0x4a6b98 LDP	X21, X0, [X0]

0x4a6b9c STR	X0, [SP, #200]

0x4a6ba0 CMP	X21, #0

0x4a6ba4 B.LE	4a7240

0x4a6ba8 CMP	X0, #0

0x4a6bac B.LE	4a7240

0x4a6bb0 MUL	X22, X21, X0

0x4a6bb4 BL	4101e0

0x4a6bb8 SBFM	X19, X0, #0, #31

0x4a6bbc BL	4101f0

0x4a6bc0 UDIV	X9, X22, X19

0x4a6bc4 SBFM	X1, X0, #0, #31

0x4a6bc8 MSUB	X2, X9, X19, X22

0x4a6bcc CMP	X1, X2

0x4a6bd0 B.CC	4a7254

0x4a6bd4 MADD	X4, X9, X1, X2

0x4a6bd8 ADD	X3, X9, X4

0x4a6bdc CMP	X4, X3

0x4a6be0 B.CS	4a7240

0x4a6be4 LDR	X7, [SP, #200]

0x4a6be8 STP	X23, X24, [SP, #48]

0x4a6bec LDR	X12, [X20, #16]

0x4a6bf0 UDIV	X8, X4, X7

0x4a6bf4 STP	X25, X26, [SP, #64]

0x4a6bf8 STP	X27, X28, [SP, #80]

0x4a6bfc LDR	X5, [X12]

0x4a6c00 LDP	X6, X14, [X12, #72]

0x4a6c04 MSUB	X11, X8, X7, X4

0x4a6c08 LDP	X10, X15, [X12, #104]

0x4a6c0c STP	X11, X8, [SP, #168]

0x4a6c10 LDR	X13, [X12, #16]

0x4a6c14 STR	X5, [SP, #240]

0x4a6c18 LDR	X16, [X12, #64]

0x4a6c1c LDR	X18, [X12, #88]

0x4a6c20 STR	X13, [SP, #216]

0x4a6c24 LDR	X24, [X12, #96]

0x4a6c28 STR	X16, [SP, #192]

0x4a6c2c LDR	X25, [X12, #120]

0x4a6c30 STR	X18, [SP, #232]

0x4a6c34 LDR	X26, [X12, #136]

0x4a6c38 STR	X24, [SP, #184]

0x4a6c3c LDR	X0, [X12, #32]

0x4a6c40 STR	X25, [SP, #152]

0x4a6c44 LDR	X30, [X12, #40]

0x4a6c48 STR	X26, [SP, #288]

0x4a6c4c LDR	X17, [X12, #56]

0x4a6c50 LDR	X23, [X12, #176]

0x4a6c54 LDR	X27, [X12, #216]

0x4a6c58 LDP	X5, X28, [X12, #400]

0x4a6c5c LDR	X20, [X12, #48]

0x4a6c60 STR	X27, [SP, #304]

0x4a6c64 LDR	X22, [X12, #296]

0x4a6c68 LDR	X2, [X12, #472]

0x4a6c6c SUB	X21, X20, X0

0x4a6c70 LDR	X13, [X12, #512]

0x4a6c74 SDIV	X7, X21, X17

0x4a6c78 STR	X22, [SP, #296]

0x4a6c7c LDR	X16, [X12, #576]

0x4a6c80 STR	X2, [SP, #280]

0x4a6c84 LDR	X18, [X12, #616]

0x4a6c88 STR	X13, [SP, #264]

0x4a6c8c LDR	X24, [X12, #624]

0x4a6c90 STR	X16, [SP, #224]

0x4a6c94 LDR	X25, [X12, #712]

0x4a6c98 STR	X18, [SP, #248]

0x4a6c9c LDR	X26, [X12, #752]

0x4a6ca0 MSUB	X11, X7, X17, X21

0x4a6ca4 STR	X24, [SP, #256]

0x4a6ca8 LDR	X17, [X12, #504]

0x4a6cac STR	X25, [SP, #312]

0x4a6cb0 LDR	X27, [X12, #760]

0x4a6cb4 STR	X26, [SP, #320]

0x4a6cb8 LDR	X20, [X12, #848]

0x4a6cbc STR	X17, [SP, #272]

0x4a6cc0 LDR	X8, [X12, #416]

0x4a6cc4 STR	X27, [SP, #328]

0x4a6cc8 LDR	X19, [X12, #256]

0x4a6ccc STR	X20, [SP, #336]

0x4a6cd0 LDR	X1, [X12, #336]

0x4a6cd4 CMP	X8, #1

0x4a6cd8 LDR	X3, [X12, #640]

0x4a6cdc CCMP	X10, #1, #0, #0

0x4a6ce0 LDR	X4, [X12, #776]

0x4a6ce4 LDR	X21, [X12, #888]

0x4a6ce8 LDR	X17, [X12, #896]

0x4a6cec LDR	X18, [X12, #912]

0x4a6cf0 STR	X21, [SP, #344]

0x4a6cf4 LDR	X22, [X12, #984]

0x4a6cf8 STR	X17, [SP, #352]

0x4a6cfc LDR	X13, [X12, #1008]

0x4a6d00 LDR	X16, [X12, #1056]

0x4a6d04 STR	X22, [SP, #360]

0x4a6d08 LDR	X2, [X12, #1088]

0x4a6d0c STR	X13, [SP, #368]

0x4a6d10 LDR	X12, [X12, #1096]

0x4a6d14 STR	X16, [SP, #376]

0x4a6d18 STR	X2, [SP, #384]

0x4a6d1c STR	X12, [SP, #392]

0x4a6d20 B.NE	4a7270

0x4a6d24 CMP	X11, #0

0x4a6d28 LDR	X11, [SP, #192]

0x4a6d2c UBFM	X17, X6, #61, #60

0x4a6d30 SUB	X27, X9, #1

0x4a6d34 FMOV	D4, #2.0000000

0x4a6d38 ADD	X21, X1, X0,LSL #3

0x4a6d3c LDR	X12, [SP, #184]

0x4a6d40 UBFM	X10, X30, #61, #60

0x4a6d44 CSINC	X22, X7, X7, #0

0x4a6d48 STR	X27, [SP, #448]

0x4a6d4c CMP	X22, #0

0x4a6d50 CSEL	X13, X22, XZR, #10

0x4a6d54 LDR	X24, [SP, #152]

0x4a6d58 MUL	X26, X11, X28

0x4a6d5c SUB	X20, X14, X11

0x4a6d60 ORR	X25, XZR, X11

0x4a6d64 ADD	X14, X19, X11,LSL #3

0x4a6d68 STP	X13, X10, [SP, #104]

0x4a6d6c MUL	X19, X30, X4

0x4a6d70 SUB	X27, X15, X12

0x4a6d74 MUL	X28, X6, X28

0x4a6d78 MUL	X6, X6, X18

0x4a6d7c STR	X14, [SP, #144]

0x4a6d80 MADD	X4, X0, X4, X12

0x4a6d84 UBFM	X2, X19, #61, #60

0x4a6d88 STR	XZR, [SP, #208]

0x4a6d8c ADD	X11, X23, X12,LSL #3

0x4a6d90 UBFM	X16, X28, #61, #60

0x4a6d94 STR	X22, [SP, #400]

0x4a6d98 MADD	X23, X0, X5, X26

0x4a6d9c UBFM	X19, X6, #61, #60

0x4a6da0 STR	X2, [SP, #120]

0x4a6da4 MUL	X5, X30, X5

0x4a6da8 STR	X21, [SP, #416]

0x4a6dac MUL	X0, X0, X3

0x4a6db0 STR	X20, [SP, #456]

0x4a6db4 MUL	X3, X30, X3

0x4a6db8 STR	X23, [SP, #440]

0x4a6dbc MADD	X30, X18, X25, X12

0x4a6dc0 STR	X5, [SP, #136]

0x4a6dc4 STP	X4, X0, [SP, #424]

0x4a6dc8 STR	X3, [SP, #128]

0x4a6dcc STR	X30, [SP, #408]

(2424) 0x4a6dd0 LDR	X18, [SP, #400]

(2424) 0x4a6dd4 CMP	X18, #0

(2424) 0x4a6dd8 B.LE	4a71fc

(2424) 0x4a6ddc LDP	X28, X7, [SP, #232]

(2424) 0x4a6de0 MOVZ	X21, #0

(2424) 0x4a6de4 LDP	X22, X23, [SP, #432]

(2424) 0x4a6de8 LDR	X20, [SP, #456]

(2424) 0x4a6dec LDR	X14, [SP, #168]

(2424) 0x4a6df0 LDR	X26, [SP, #216]

(2424) 0x4a6df4 SDIV	X25, X20, X28

(2424) 0x4a6df8 LDR	X15, [SP, #176]

(2424) 0x4a6dfc LDR	X13, [SP, #288]

(2424) 0x4a6e00 ADD	X0, X14, X26

(2424) 0x4a6e04 LDR	X26, [SP, #248]

(2424) 0x4a6e08 ADD	X8, X15, X7

(2424) 0x4a6e0c LDR	X4, [SP, #296]

(2424) 0x4a6e10 UBFM	X10, X8, #61, #60

(2424) 0x4a6e14 ADD	X13, X13, X10

(2424) 0x4a6e18 LDR	X12, [SP, #304]

(2424) 0x4a6e1c MSUB	X1, X25, X28, X20

(2424) 0x4a6e20 LDR	X7, [SP, #344]

(2424) 0x4a6e24 MUL	X28, X26, X8

(2424) 0x4a6e28 LDR	X3, [SP, #320]

(2424) 0x4a6e2c CMP	X1, #0

(2424) 0x4a6e30 CSINC	X25, X25, X25, #0

(2424) 0x4a6e34 ADD	X12, X12, X10

(2424) 0x4a6e38 ADD	X10, X4, X10

(2424) 0x4a6e3c LDR	X26, [SP, #352]

(2424) 0x4a6e40 CMP	X25, #0

(2424) 0x4a6e44 CSEL	X20, X25, XZR, #10

(2424) 0x4a6e48 MUL	X14, X7, X8

(2424) 0x4a6e4c LDR	X30, [SP, #272]

(2424) 0x4a6e50 MUL	X18, X3, X8

(2424) 0x4a6e54 LDR	X4, [SP, #328]

(2424) 0x4a6e58 MADD	X7, X26, X0, X14

(2424) 0x4a6e5c LDR	X1, [SP, #384]

(2424) 0x4a6e60 MUL	X15, X30, X8

(2424) 0x4a6e64 LDR	X3, [SP, #264]

(2424) 0x4a6e68 MADD	X18, X4, X0, X18

(2424) 0x4a6e6c LDR	X5, [SP, #408]

(2424) 0x4a6e70 MUL	X8, X1, X8

(2424) 0x4a6e74 LDR	X14, [SP, #424]

(2424) 0x4a6e78 MADD	X30, X3, X0, X15

(2424) 0x4a6e7c LDR	X2, [SP, #336]

(2424) 0x4a6e80 ADD	X5, X7, X5

(2424) 0x4a6e84 LDR	X1, [SP, #392]

(2424) 0x4a6e88 ADD	X4, X18, X14

(2424) 0x4a6e8c LDR	X18, [SP, #184]

(2424) 0x4a6e90 ADD	X26, X2, X5,LSL #3

(2424) 0x4a6e94 LDR	X15, [SP, #256]

(2424) 0x4a6e98 MADD	X8, X1, X0, X8

(2424) 0x4a6e9c LDR	X6, [SP, #368]

(2424) 0x4a6ea0 ADD	X30, X30, X18

(2424) 0x4a6ea4 LDR	X2, [SP, #376]

(2424) 0x4a6ea8 MADD	X28, X15, X0, X28

(2424) 0x4a6eac LDR	X7, [SP, #192]

(2424) 0x4a6eb0 MADD	X0, X6, X0, X18

(2424) 0x4a6eb4 ADD	X6, X8, X18

(2424) 0x4a6eb8 LDR	X5, [SP, #280]

(2424) 0x4a6ebc ADD	X15, X2, X6,LSL #3

(2424) 0x4a6ec0 LDR	X2, [SP, #224]

(2424) 0x4a6ec4 ADD	X28, X28, X7

(2424) 0x4a6ec8 LDR	X3, [SP, #312]

(2424) 0x4a6ecc ADD	X30, X5, X30,LSL #3

(2424) 0x4a6ed0 LDR	X9, [SP, #416]

(2424) 0x4a6ed4 STR	X15, [SP, #160]

(2424) 0x4a6ed8 ADD	X28, X2, X28,LSL #3

(2424) 0x4a6edc LDR	X14, [SP, #360]

(2424) 0x4a6ee0 ADD	X4, X3, X4,LSL #3

(2424) 0x4a6ee4 ADD	X1, X14, X0,LSL #3

(2424) 0x4a6ee8 STR	X1, [SP, #152]

  (2425) 0x4a6eec CMP	X25, #0

  (2425) 0x4a6ef0 B.LE	4a71cc

  (2425) 0x4a6ef4 SDIV	X18, X27, X24

  (2425) 0x4a6ef8 LDP	X6, X0, [SP, #144]

  (2425) 0x4a6efc ORR	X3, XZR, X26

  (2425) 0x4a6f00 MOVZ	X15, #0

  (2425) 0x4a6f04 UBFM	X5, X23, #61, #60

  (2425) 0x4a6f08 ADD	X8, X30, X5

  (2425) 0x4a6f0c LDR	X14, [SP, #160]

  (2425) 0x4a6f10 ADD	X2, X28, X22,LSL #3

  (2425) 0x4a6f14 ADD	X7, X5, X0

  (2425) 0x4a6f18 ADD	X5, X5, X14

  (2425) 0x4a6f1c MSUB	X1, X18, X24, X27

  (2425) 0x4a6f20 CMP	X1, #0

  (2425) 0x4a6f24 CSINC	X18, X18, X18, #0

  (2425) 0x4a6f28 CMP	X18, #0

  (2425) 0x4a6f2c CSEL	X14, X18, XZR, #10

    (2426) 0x4a6f30 CMP	X18, #0

    (2426) 0x4a6f34 B.LE	4a71a8

    (2426) 0x4a6f38 LDR	D22, [X10]

    (2426) 0x4a6f3c SUB	X1, X14, #1

    (2426) 0x4a6f40 MOVZ	X0, #1

    (2426) 0x4a6f44 AND	X1, X1, X0

    (2426) 0x4a6f48 LDR	D28, [X12]

    (2426) 0x4a6f4c LDR	D21, [X9]

    (2426) 0x4a6f50 FADD	D23, D22, D22

    (2426) 0x4a6f54 LDR	D19, [X6]

    (2426) 0x4a6f58 FADD	D29, D28, D28

    (2426) 0x4a6f5c LDR	D5, [X13]

    (2426) 0x4a6f60 LDR	D2, [X3]

    (2426) 0x4a6f64 FDIV	D24, D23, D21

    (2426) 0x4a6f68 LDR	D18, [X4]

    (2426) 0x4a6f6c FADD	D6, D5, D5

    (2426) 0x4a6f70 LDR	D27, [X11]

    (2426) 0x4a6f74 LDR	D26, [X8]

    (2426) 0x4a6f78 FDIV	D30, D29, D19

    (2426) 0x4a6f7c LDR	D20, [X7]

    (2426) 0x4a6f80 LDR	D17, [X2]

    (2426) 0x4a6f84 FDIV	D3, D6, D27

    (2426) 0x4a6f88 FMUL	D25, D24, D2

    (2426) 0x4a6f8c FMADD	D31, D18, D30, D25

    (2426) 0x4a6f90 FADD	D7, D24, D30

    (2426) 0x4a6f94 FADD	D16, D7, D20

    (2426) 0x4a6f98 FADD	D0, D31, D26

    (2426) 0x4a6f9c FADD	D1, D16, D3

    (2426) 0x4a6fa0 FMADD	D2, D17, D3, D0

    (2426) 0x4a6fa4 FDIV	D18, D2, D1

    (2426) 0x4a6fa8 STR	D18, [X5]

    (2426) 0x4a6fac LDR	D19, [X2]

    (2426) 0x4a6fb0 FNMSUB	D20, D18, D4, D19

    (2426) 0x4a6fb4 STR	D20, [X2]

    (2426) 0x4a6fb8 LDR	D21, [X4]

    (2426) 0x4a6fbc FNMSUB	D22, D18, D4, D21

    (2426) 0x4a6fc0 STR	D22, [X4]

    (2426) 0x4a6fc4 LDR	D23, [X3]

    (2426) 0x4a6fc8 FNMSUB	D24, D18, D4, D23

    (2426) 0x4a6fcc STR	D24, [X3]

    (2426) 0x4a6fd0 CMP	X14, X0

    (2426) 0x4a6fd4 B.LE	4a71a8

    (2426) 0x4a6fd8 CBZ	X1, 4a7080

    (2426) 0x4a6fdc LDR	D31, [X10]

    (2426) 0x4a6fe0 LDR	D5, [X12]

    (2426) 0x4a6fe4 LDR	D30, [X9]

    (2426) 0x4a6fe8 FADD	D7, D31, D31

    (2426) 0x4a6fec LDR	D29, [X6]

    (2426) 0x4a6ff0 FADD	D6, D5, D5

    (2426) 0x4a6ff4 LDR	D21, [X13]

    (2426) 0x4a6ff8 LDR	D25, [X3, X0,LSL #3]

    (2426) 0x4a6ffc FDIV	D16, D7, D30

    (2426) 0x4a7000 LDR	D26, [X4, X0,LSL #3]

    (2426) 0x4a7004 FADD	D22, D21, D21

    (2426) 0x4a7008 LDR	D27, [X11, X0,LSL #3]

    (2426) 0x4a700c LDR	D17, [X8, X0,LSL #3]

    (2426) 0x4a7010 FDIV	D3, D6, D29

    (2426) 0x4a7014 LDR	D28, [X7, X0,LSL #3]

    (2426) 0x4a7018 LDR	D20, [X2]

    (2426) 0x4a701c FDIV	D23, D22, D27

    (2426) 0x4a7020 FMUL	D0, D16, D25

    (2426) 0x4a7024 FMADD	D2, D26, D3, D0

    (2426) 0x4a7028 FADD	D1, D16, D3

    (2426) 0x4a702c FADD	D18, D1, D28

    (2426) 0x4a7030 FADD	D19, D2, D17

    (2426) 0x4a7034 FADD	D24, D18, D23

    (2426) 0x4a7038 FMADD	D25, D20, D23, D19

    (2426) 0x4a703c FDIV	D26, D25, D24

    (2426) 0x4a7040 STR	D26, [X5, X0,LSL #3]

    (2426) 0x4a7044 LDR	D27, [X2]

    (2426) 0x4a7048 FNMSUB	D28, D26, D4, D27

    (2426) 0x4a704c STR	D28, [X2]

    (2426) 0x4a7050 LDR	D29, [X4, X0,LSL #3]

    (2426) 0x4a7054 FNMSUB	D30, D26, D4, D29

    (2426) 0x4a7058 STR	D30, [X4, X0,LSL #3]

    (2426) 0x4a705c LDR	D31, [X3, X0,LSL #3]

    (2426) 0x4a7060 FNMSUB	D7, D26, D4, D31

    (2426) 0x4a7064 STR	D7, [X3, X0,LSL #3]

    (2426) 0x4a7068 MOVZ	X0, #2

    (2426) 0x4a706c CMP	X14, X0

    (2426) 0x4a7070 B.LE	4a71a8

    (2426) 0x4a7074 HINT	#0

    (2426) 0x4a7078 HINT	#0

    (2426) 0x4a707c HINT	#0

      (2427) 0x4a7080 LDR	D3, [X10]

      (2427) 0x4a7084 ADD	X1, X0, #1

      (2427) 0x4a7088 LDR	D21, [X12]

      (2427) 0x4a708c LDR	D6, [X9]

      (2427) 0x4a7090 FADD	D1, D3, D3

      (2427) 0x4a7094 LDR	D5, [X6]

      (2427) 0x4a7098 FADD	D22, D21, D21

      (2427) 0x4a709c LDR	D29, [X13]

      (2427) 0x4a70a0 LDR	D0, [X3, X0,LSL #3]

      (2427) 0x4a70a4 FDIV	D18, D1, D6

      (2427) 0x4a70a8 LDR	D16, [X4, X0,LSL #3]

      (2427) 0x4a70ac FADD	D30, D29, D29

      (2427) 0x4a70b0 LDR	D17, [X11, X0,LSL #3]

      (2427) 0x4a70b4 LDR	D19, [X8, X0,LSL #3]

      (2427) 0x4a70b8 FDIV	D23, D22, D5

      (2427) 0x4a70bc LDR	D2, [X7, X0,LSL #3]

      (2427) 0x4a70c0 LDR	D28, [X2]

      (2427) 0x4a70c4 FDIV	D31, D30, D17

      (2427) 0x4a70c8 FMUL	D20, D18, D0

      (2427) 0x4a70cc FMADD	D24, D16, D23, D20

      (2427) 0x4a70d0 FADD	D25, D18, D23

      (2427) 0x4a70d4 FADD	D26, D25, D2

      (2427) 0x4a70d8 FADD	D27, D24, D19

      (2427) 0x4a70dc FADD	D7, D26, D31

      (2427) 0x4a70e0 FMADD	D0, D28, D31, D27

      (2427) 0x4a70e4 FDIV	D16, D0, D7

      (2427) 0x4a70e8 STR	D16, [X5, X0,LSL #3]

      (2427) 0x4a70ec LDR	D17, [X2]

      (2427) 0x4a70f0 FNMSUB	D2, D16, D4, D17

      (2427) 0x4a70f4 STR	D2, [X2]

      (2427) 0x4a70f8 LDR	D5, [X4, X0,LSL #3]

      (2427) 0x4a70fc FNMSUB	D6, D16, D4, D5

      (2427) 0x4a7100 STR	D6, [X4, X0,LSL #3]

      (2427) 0x4a7104 LDR	D3, [X3, X0,LSL #3]

      (2427) 0x4a7108 FNMSUB	D1, D16, D4, D3

      (2427) 0x4a710c STR	D1, [X3, X0,LSL #3]

      (2427) 0x4a7110 ADD	X0, X0, #2

      (2427) 0x4a7114 LDR	D24, [X10]

      (2427) 0x4a7118 LDR	D29, [X12]

      (2427) 0x4a711c LDR	D23, [X9]

      (2427) 0x4a7120 FADD	D25, D24, D24

      (2427) 0x4a7124 LDR	D22, [X6]

      (2427) 0x4a7128 FADD	D30, D29, D29

      (2427) 0x4a712c LDR	D2, [X13]

      (2427) 0x4a7130 LDR	D18, [X3, X1,LSL #3]

      (2427) 0x4a7134 FDIV	D26, D25, D23

      (2427) 0x4a7138 LDR	D19, [X4, X1,LSL #3]

      (2427) 0x4a713c FADD	D6, D2, D2

      (2427) 0x4a7140 LDR	D20, [X11, X1,LSL #3]

      (2427) 0x4a7144 LDR	D27, [X8, X1,LSL #3]

      (2427) 0x4a7148 FDIV	D31, D30, D22

      (2427) 0x4a714c LDR	D21, [X7, X1,LSL #3]

      (2427) 0x4a7150 LDR	D5, [X2]

      (2427) 0x4a7154 FDIV	D3, D6, D20

      (2427) 0x4a7158 FMUL	D28, D26, D18

      (2427) 0x4a715c FMADD	D7, D19, D31, D28

      (2427) 0x4a7160 FADD	D0, D26, D31

      (2427) 0x4a7164 FADD	D16, D0, D21

      (2427) 0x4a7168 FADD	D17, D7, D27

      (2427) 0x4a716c FADD	D1, D16, D3

      (2427) 0x4a7170 FMADD	D18, D5, D3, D17

      (2427) 0x4a7174 FDIV	D19, D18, D1

      (2427) 0x4a7178 STR	D19, [X5, X1,LSL #3]

      (2427) 0x4a717c LDR	D20, [X2]

      (2427) 0x4a7180 FNMSUB	D21, D19, D4, D20

      (2427) 0x4a7184 STR	D21, [X2]

      (2427) 0x4a7188 LDR	D22, [X4, X1,LSL #3]

      (2427) 0x4a718c FNMSUB	D23, D19, D4, D22

      (2427) 0x4a7190 STR	D23, [X4, X1,LSL #3]

      (2427) 0x4a7194 LDR	D24, [X3, X1,LSL #3]

      (2427) 0x4a7198 FNMSUB	D25, D19, D4, D24

      (2427) 0x4a719c STR	D25, [X3, X1,LSL #3]

      (2427) 0x4a71a0 CMP	X14, X0

      (2427) 0x4a71a4 B.GT	4a7080

    (2426) 0x4a71a8 ADD	X15, X15, #1

    (2426) 0x4a71ac ADD	X6, X6, X17

    (2426) 0x4a71b0 ADD	X8, X8, X16

    (2426) 0x4a71b4 ADD	X2, X2, X17

    (2426) 0x4a71b8 ADD	X3, X3, X19

    (2426) 0x4a71bc ADD	X7, X7, X16

    (2426) 0x4a71c0 ADD	X5, X5, X16

    (2426) 0x4a71c4 CMP	X20, X15

    (2426) 0x4a71c8 B.GT	4a6f30

  (2425) 0x4a71cc LDR	X6, [SP, #104]

  (2425) 0x4a71d0 ADD	X21, X21, #1

  (2425) 0x4a71d4 LDR	X0, [SP, #112]

  (2425) 0x4a71d8 LDR	X2, [SP, #120]

  (2425) 0x4a71dc LDR	X3, [SP, #128]

  (2425) 0x4a71e0 ADD	X9, X9, X0

  (2425) 0x4a71e4 LDR	X5, [SP, #136]

  (2425) 0x4a71e8 ADD	X4, X4, X2

  (2425) 0x4a71ec ADD	X22, X22, X3

  (2425) 0x4a71f0 ADD	X23, X23, X5

  (2425) 0x4a71f4 CMP	X6, X21

  (2425) 0x4a71f8 B.GT	4a6eec

(2424) 0x4a71fc LDR	X4, [SP, #208]

(2424) 0x4a7200 LDR	X7, [SP, #448]

(2424) 0x4a7204 CMP	X4, X7

(2424) 0x4a7208 B.EQ	4a7234

(2424) 0x4a720c LDR	X8, [SP, #168]

(2424) 0x4a7210 LDR	X9, [SP, #200]

(2424) 0x4a7214 ADD	X10, X8, #1

(2424) 0x4a7218 STR	X10, [SP, #168]

(2424) 0x4a721c CMP	X9, X10

(2424) 0x4a7220 B.LE	4a7260

(2424) 0x4a7224 LDR	X14, [SP, #208]

(2424) 0x4a7228 ADD	X15, X14, #1

(2424) 0x4a722c STR	X15, [SP, #208]

(2424) 0x4a7230 B	4a6dd0

0x4a7234 LDP	X23, X24, [SP, #48]

0x4a7238 LDP	X25, X26, [SP, #64]

0x4a723c LDP	X27, X28, [SP, #80]

0x4a7240 LDP	X29, X30, [SP]

0x4a7244 LDP	X19, X20, [SP, #16]

0x4a7248 LDP	X21, X22, [SP, #32]

0x4a724c ADD	SP, SP, #528

0x4a7250 RET

0x4a7254 ADD	X9, X9, #1

0x4a7258 MOVZ	X2, #0

0x4a725c B	4a6bd4

(2424) 0x4a7260 LDR	X12, [SP, #176]

(2424) 0x4a7264 ADD	X13, X12, #1

(2424) 0x4a7268 STP	XZR, X13, [SP, #168]

(2424) 0x4a726c B	4a7224

0x4a7270 LDR	X24, [SP, #192]

0x4a7274 CMP	X11, #0

0x4a7278 MUL	X25, X6, X18

0x4a727c UBFM	X21, X6, #61, #60

0x4a7280 MUL	X6, X6, X28

0x4a7284 FMOV	D4, #2.0000000

0x4a7288 MUL	X17, X30, X4

0x4a728c UBFM	X22, X10, #61, #60

0x4a7290 SUB	X9, X9, #1

0x4a7294 MUL	X4, X0, X4

0x4a7298 CSINC	X7, X7, X7, #0

0x4a729c CMP	X7, #0

0x4a72a0 ADD	X1, X1, X0,LSL #3

0x4a72a4 CSEL	X2, X7, XZR, #10

0x4a72a8 STR	XZR, [SP, #112]

0x4a72ac SUB	X11, X14, X24

0x4a72b0 LDR	X14, [SP, #184]

0x4a72b4 MUL	X26, X24, X28

0x4a72b8 ADD	X19, X19, X24,LSL #3

0x4a72bc UBFM	X28, X6, #61, #60

0x4a72c0 STR	X2, [SP, #128]

0x4a72c4 STR	X17, [SP, #208]

0x4a72c8 MADD	X20, X0, X5, X26

0x4a72cc STR	X7, [SP, #464]

0x4a72d0 MUL	X5, X30, X5

0x4a72d4 STR	X19, [SP, #136]

0x4a72d8 ADD	X27, X23, X14,LSL #3

0x4a72dc SUB	X15, X15, X14

0x4a72e0 STR	X1, [SP, #480]

0x4a72e4 MUL	X23, X14, X8

0x4a72e8 STR	X4, [SP, #488]

0x4a72ec MUL	X8, X8, X10

0x4a72f0 UBFM	X10, X30, #61, #60

0x4a72f4 STR	X5, [SP, #408]

0x4a72f8 MUL	X0, X0, X3

0x4a72fc STR	X15, [SP, #456]

0x4a7300 MUL	X30, X30, X3

0x4a7304 STR	X10, [SP, #160]

0x4a7308 MUL	X3, X18, X24

0x4a730c UBFM	X26, X8, #61, #60

0x4a7310 STR	X23, [SP, #472]

0x4a7314 STR	X0, [SP, #496]

0x4a7318 STR	X30, [SP, #400]

0x4a731c STR	X3, [SP, #144]

0x4a7320 STR	X20, [SP, #504]

0x4a7324 STR	X9, [SP, #512]

0x4a7328 STR	X11, [SP, #520]

(2420) 0x4a732c LDR	X13, [SP, #464]

(2420) 0x4a7330 CMP	X13, #0

(2420) 0x4a7334 B.LE	4a75c8

(2420) 0x4a7338 LDP	X18, X6, [SP, #168]

(2420) 0x4a733c STR	XZR, [SP, #104]

(2420) 0x4a7340 LDR	X11, [SP, #216]

(2420) 0x4a7344 LDP	X10, X23, [SP, #480]

(2420) 0x4a7348 LDP	X24, X30, [SP, #496]

(2420) 0x4a734c ADD	X15, X18, X11

(2420) 0x4a7350 LDR	X19, [SP, #264]

(2420) 0x4a7354 LDR	X5, [SP, #240]

(2420) 0x4a7358 LDR	X7, [SP, #272]

(2420) 0x4a735c MUL	X3, X19, X15

(2420) 0x4a7360 LDR	X9, [SP, #232]

(2420) 0x4a7364 ADD	X8, X5, X6

(2420) 0x4a7368 LDR	X20, [SP, #520]

(2420) 0x4a736c UBFM	X17, X8, #61, #60

(2420) 0x4a7370 MADD	X6, X7, X8, X3

(2420) 0x4a7374 LDP	X18, X7, [SP, #248]

(2420) 0x4a7378 SDIV	X2, X20, X9

(2420) 0x4a737c LDR	X14, [SP, #288]

(2420) 0x4a7380 LDR	X16, [SP, #296]

(2420) 0x4a7384 LDR	X1, [SP, #304]

(2420) 0x4a7388 MUL	X5, X7, X15

(2420) 0x4a738c ADD	X14, X14, X17

(2420) 0x4a7390 LDR	X4, [SP, #352]

(2420) 0x4a7394 ADD	X11, X16, X17

(2420) 0x4a7398 LDR	X12, [SP, #344]

(2420) 0x4a739c ADD	X13, X1, X17

(2420) 0x4a73a0 MADD	X17, X18, X8, X5

(2420) 0x4a73a4 LDP	X3, X18, [SP, #320]

(2420) 0x4a73a8 MSUB	X9, X2, X9, X20

(2420) 0x4a73ac MUL	X0, X4, X15

(2420) 0x4a73b0 LDP	X16, X4, [SP, #384]

(2420) 0x4a73b4 CMP	X9, #0

(2420) 0x4a73b8 CSINC	X20, X2, X2, #0

(2420) 0x4a73bc MUL	X7, X18, X15

(2420) 0x4a73c0 CMP	X20, #0

(2420) 0x4a73c4 MADD	X12, X12, X8, X0

(2420) 0x4a73c8 LDR	X2, [SP, #184]

(2420) 0x4a73cc MUL	X1, X4, X15

(2420) 0x4a73d0 LDR	X0, [SP, #472]

(2420) 0x4a73d4 MADD	X19, X16, X8, X1

(2420) 0x4a73d8 LDR	X4, [SP, #368]

(2420) 0x4a73dc MADD	X16, X3, X8, X7

(2420) 0x4a73e0 ADD	X18, X12, X2

(2420) 0x4a73e4 LDR	X8, [SP, #192]

(2420) 0x4a73e8 ADD	X6, X6, X0

(2420) 0x4a73ec ADD	X1, X16, X2

(2420) 0x4a73f0 LDR	X16, [SP, #224]

(2420) 0x4a73f4 MADD	X15, X4, X15, X0

(2420) 0x4a73f8 LDR	X3, [SP, #280]

(2420) 0x4a73fc ADD	X5, X17, X8

(2420) 0x4a7400 ADD	X17, X19, X0

(2420) 0x4a7404 CSEL	X19, X20, XZR, #10

(2420) 0x4a7408 ADD	X12, X16, X5,LSL #3

(2420) 0x4a740c ADD	X7, X3, X6,LSL #3

(2420) 0x4a7410 STR	X12, [SP, #432]

(2420) 0x4a7414 STR	X7, [SP, #424]

(2420) 0x4a7418 LDR	X8, [SP, #376]

(2420) 0x4a741c STR	X20, [SP, #120]

(2420) 0x4a7420 LDR	X0, [SP, #312]

(2420) 0x4a7424 LDR	X4, [SP, #360]

(2420) 0x4a7428 ADD	X6, X8, X17,LSL #3

(2420) 0x4a742c LDR	X17, [SP, #336]

(2420) 0x4a7430 ADD	X5, X0, X1,LSL #3

(2420) 0x4a7434 STR	X6, [SP, #448]

(2420) 0x4a7438 ADD	X15, X4, X15,LSL #3

(2420) 0x4a743c STR	X5, [SP, #416]

(2420) 0x4a7440 ADD	X18, X17, X18,LSL #3

(2420) 0x4a7444 STR	X15, [SP, #440]

  (2421) 0x4a7448 LDR	X9, [SP, #120]

  (2421) 0x4a744c CMP	X9, #0

  (2421) 0x4a7450 B.LE	4a7590

  (2421) 0x4a7454 LDR	X1, [SP, #152]

  (2421) 0x4a7458 UBFM	X20, X30, #61, #60

  (2421) 0x4a745c MOVZ	X15, #0

  (2421) 0x4a7460 LDP	X7, X16, [SP, #136]

  (2421) 0x4a7464 LDR	X3, [SP, #456]

  (2421) 0x4a7468 LDR	X4, [SP, #416]

  (2421) 0x4a746c LDR	X2, [SP, #424]

  (2421) 0x4a7470 SDIV	X12, X3, X1

  (2421) 0x4a7474 LDR	X5, [SP, #432]

  (2421) 0x4a7478 LDR	X0, [SP, #440]

  (2421) 0x4a747c ADD	X9, X2, X20

  (2421) 0x4a7480 LDR	X6, [SP, #448]

  (2421) 0x4a7484 MSUB	X8, X12, X1, X3

  (2421) 0x4a7488 ADD	X6, X20, X6

  (2421) 0x4a748c ADD	X3, X5, X24,LSL #3

  (2421) 0x4a7490 CMP	X8, #0

  (2421) 0x4a7494 ADD	X8, X20, X0

  (2421) 0x4a7498 ADD	X20, X4, X23,LSL #3

  (2421) 0x4a749c CSINC	X17, X12, X12, #0

  (2421) 0x4a74a0 CMP	X17, #0

  (2421) 0x4a74a4 CSEL	X12, X17, XZR, #10

    (2422) 0x4a74a8 CMP	X17, #0

    (2422) 0x4a74ac B.LE	4a756c

    (2422) 0x4a74b0 ADD	X2, X18, X16,LSL #3

    (2422) 0x4a74b4 ORR	X1, XZR, X20

    (2422) 0x4a74b8 ORR	X5, XZR, X27

    (2422) 0x4a74bc MOVZ	X0, #0

    (2422) 0x4a74c0 MOVZ	X4, #0

      (2423) 0x4a74c4 LDR	D3, [X11]

      (2423) 0x4a74c8 ADD	X4, X4, #1

      (2423) 0x4a74cc LDR	D20, [X13]

      (2423) 0x4a74d0 LDR	D6, [X10]

      (2423) 0x4a74d4 FADD	D1, D3, D3

      (2423) 0x4a74d8 LDR	D5, [X7]

      (2423) 0x4a74dc FADD	D21, D20, D20

      (2423) 0x4a74e0 LDR	D28, [X14]

      (2423) 0x4a74e4 LDR	D0, [X2]

      (2423) 0x4a74e8 FDIV	D2, D1, D6

      (2423) 0x4a74ec LDR	D16, [X1]

      (2423) 0x4a74f0 FADD	D29, D28, D28

      (2423) 0x4a74f4 LDR	D17, [X5]

      (2423) 0x4a74f8 ADD	X5, X5, X22

      (2423) 0x4a74fc LDR	D18, [X9, X0]

      (2423) 0x4a7500 FDIV	D22, D21, D5

      (2423) 0x4a7504 LDR	D7, [X8, X0]

      (2423) 0x4a7508 LDR	D27, [X3]

      (2423) 0x4a750c FDIV	D30, D29, D17

      (2423) 0x4a7510 FMUL	D19, D2, D0

      (2423) 0x4a7514 FMADD	D23, D22, D16, D19

      (2423) 0x4a7518 FADD	D24, D22, D2

      (2423) 0x4a751c FADD	D25, D24, D7

      (2423) 0x4a7520 FADD	D26, D23, D18

      (2423) 0x4a7524 FADD	D31, D25, D30

      (2423) 0x4a7528 FMADD	D7, D30, D27, D26

      (2423) 0x4a752c FDIV	D16, D7, D31

      (2423) 0x4a7530 STR	D16, [X6, X0]

      (2423) 0x4a7534 ADD	X0, X0, X26

      (2423) 0x4a7538 LDR	D0, [X3]

      (2423) 0x4a753c FNMSUB	D17, D16, D4, D0

      (2423) 0x4a7540 STR	D17, [X3]

      (2423) 0x4a7544 LDR	D5, [X1]

      (2423) 0x4a7548 FNMSUB	D6, D16, D4, D5

      (2423) 0x4a754c STR	D6, [X1]

      (2423) 0x4a7550 ADD	X1, X1, X22

      (2423) 0x4a7554 LDR	D3, [X2]

      (2423) 0x4a7558 FNMSUB	D1, D16, D4, D3

      (2423) 0x4a755c STR	D1, [X2]

      (2423) 0x4a7560 ADD	X2, X2, X22

      (2423) 0x4a7564 CMP	X4, X12

      (2423) 0x4a7568 B.LT	4a74c4

    (2422) 0x4a756c ADD	X15, X15, #1

    (2422) 0x4a7570 ADD	X7, X7, X21

    (2422) 0x4a7574 ADD	X9, X9, X28

    (2422) 0x4a7578 ADD	X3, X3, X21

    (2422) 0x4a757c ADD	X16, X16, X25

    (2422) 0x4a7580 ADD	X8, X8, X28

    (2422) 0x4a7584 ADD	X6, X6, X28

    (2422) 0x4a7588 CMP	X15, X19

    (2422) 0x4a758c B.LT	4a74a8

  (2421) 0x4a7590 LDR	X17, [SP, #104]

  (2421) 0x4a7594 LDR	X1, [SP, #128]

  (2421) 0x4a7598 LDR	X12, [SP, #160]

  (2421) 0x4a759c ADD	X20, X17, #1

  (2421) 0x4a75a0 LDR	X4, [SP, #208]

  (2421) 0x4a75a4 STR	X20, [SP, #104]

  (2421) 0x4a75a8 LDR	X5, [SP, #400]

  (2421) 0x4a75ac ADD	X10, X10, X12

  (2421) 0x4a75b0 LDR	X0, [SP, #408]

  (2421) 0x4a75b4 ADD	X23, X23, X4

  (2421) 0x4a75b8 ADD	X24, X24, X5

  (2421) 0x4a75bc ADD	X30, X30, X0

  (2421) 0x4a75c0 CMP	X20, X1

  (2421) 0x4a75c4 B.LT	4a7448

(2420) 0x4a75c8 LDR	X14, [SP, #112]

(2420) 0x4a75cc LDR	X13, [SP, #512]

(2420) 0x4a75d0 CMP	X14, X13

(2420) 0x4a75d4 B.EQ	4a7234

(2420) 0x4a75d8 LDR	X11, [SP, #168]

(2420) 0x4a75dc LDR	X19, [SP, #200]

(2420) 0x4a75e0 ADD	X18, X11, #1

(2420) 0x4a75e4 STR	X18, [SP, #168]

(2420) 0x4a75e8 CMP	X19, X18

(2420) 0x4a75ec B.LE	4a7600

(2420) 0x4a75f0 LDR	X7, [SP, #112]

(2420) 0x4a75f4 ADD	X9, X7, #1

(2420) 0x4a75f8 STR	X9, [SP, #112]

(2420) 0x4a75fc B	4a732c

(2420) 0x4a7600 LDR	X2, [SP, #176]

(2420) 0x4a7604 ADD	X15, X2, #1

(2420) 0x4a7608 STP	XZR, X15, [SP, #168]

(2420) 0x4a760c B	4a75f0

Coverage (%)	Name	Source Location	Module
►98.43+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	GOMP_parallel		libgomp.so.1.0.0
○	void Kripke::DispatchHelper<Kr[...]	plugins.hpp:66	exec
○	Kripke::Kernel::sweepSubdomain[...]	ArchLayout.h:155	exec
○	Kripke::SweepSolver(Kripke::Co[...]	SweepSolver.cpp:78	exec
○	Kripke::SteadyStateSolver(Krip[...]	stl_vector.h:680	exec
○	main	new_allocator.h:79	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	iostream:74	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_9

Source file and lines	Collapse.hpp:129-129
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:187
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:88-106
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:369
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/TypedViewBase.hpp:216
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:291,373-377

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 60.00 to 30.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 60.00 to 39.33 cycles (1.53x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	206
nb uops	206
loop length	824
used w registers	0
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	76

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.75 cycles
front end	25.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	19.75	19.75	19.75	19.75	0.50	0.50	0.50	0.50	39.33	39.33	39.33	32.00	32.00
cycles	4.50	4.50	19.75	19.75	19.75	19.75	0.50	0.50	0.50	0.50	39.33	39.33	39.33	32.00	32.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

15.00-60.00

Cycles summary

Front-end	25.75
Dispatch	39.33
DIV/SQRT	15.00-60.00
Overall L1	39.33-60.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	28%
load	28%
store	28%
mul	25%
add-sub	25%
fma	25%
other	29%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	27%
load	28%
store	28%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 60.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4a6b80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4a7240 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x6c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4a7240 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x6c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL X22, X21, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
BL 4101e0 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV X9, X22, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
MSUB X2, X9, X19, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 4a7254 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X4, X9, X1, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X3, X9, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 4a7240 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x6c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X12, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UDIV X8, X4, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X5, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X6, X14, [X12, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MSUB X11, X8, X7, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X10, X15, [X12, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X11, X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X13, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X12, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X12, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X24, [X12, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X16, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X25, [X12, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X18, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X26, [X12, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X24, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X12, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X25, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X12, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X26, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X12, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X23, [X12, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X27, [X12, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X5, X28, [X12, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X20, [X12, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X22, [X12, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [X12, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X21, X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X13, [X12, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SDIV X7, X21, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
STR X22, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X12, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [X12, #616]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X24, [X12, #624]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X16, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X25, [X12, #712]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X18, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X26, [X12, #752]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB X11, X7, X17, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR X24, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X12, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X25, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X27, [X12, #760]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X26, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X12, #848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X17, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X12, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X27, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [X12, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X20, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X12, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X3, [X12, #640]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CCMP X10, #1, #0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X4, [X12, #776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X21, [X12, #888]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X12, #896]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X12, #912]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X21, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X22, [X12, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X17, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [X12, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X12, #1056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X22, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #1088]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X12, #1096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X2, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.NE 4a7270 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x6f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X11, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X17, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X27, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D4, #2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X21, X1, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X12, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X10, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC X22, X7, X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X27, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X13, X22, XZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X24, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MUL X26, X11, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
SUB X20, X14, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X19, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X13, X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MUL X19, X30, X4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
SUB X27, X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X28, X6, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
MUL X6, X6, X18	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X4, X0, X4, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X2, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR XZR, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X11, X23, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X16, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X22, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X23, X0, X5, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X19, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X5, X30, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X21, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X0, X0, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X20, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X3, X30, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X23, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X30, X18, X25, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X0, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X30, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD SP, SP, #528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4a6bd4 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
MUL X25, X6, X18	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X21, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X6, X6, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FMOV D4, #2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MUL X17, X30, X4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X22, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X4, X0, X4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
CSINC X7, X7, X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X1, X1, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSEL X2, X7, XZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR XZR, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X11, X14, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X14, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X26, X24, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X19, X19, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X28, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X17, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X20, X0, X5, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STR X7, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X5, X30, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X19, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X27, X23, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X15, X15, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X23, X14, X8	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X4, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X8, X8, X10	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X10, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X5, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X0, X0, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X15, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X30, X30, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X10, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X3, X18, X24	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X26, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X23, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X30, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X20, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_9

Source file and lines	Collapse.hpp:129-129
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:187
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:88-106
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:369
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/TypedViewBase.hpp:216
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:291,373-377

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 60.00 to 39.33 cycles (1.53x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129
- /home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:129

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	206
nb uops	206
loop length	824
used w registers	0
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	76

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.75 cycles
front end	25.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	19.75	19.75	19.75	19.75	0.50	0.50	0.50	0.50	39.33	39.33	39.33	32.00	32.00
cycles	4.50	4.50	19.75	19.75	19.75	19.75	0.50	0.50	0.50	0.50	39.33	39.33	39.33	32.00	32.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

15.00-60.00

Cycles summary

Front-end	25.75
Dispatch	39.33
DIV/SQRT	15.00-60.00
Overall L1	39.33-60.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	28%
load	28%
store	28%
mul	25%
add-sub	25%
fma	25%
other	29%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	27%
load	28%
store	28%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 60.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4a6b80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4a7240 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x6c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4a7240 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x6c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL X22, X21, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
BL 4101e0 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV X9, X22, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
MSUB X2, X9, X19, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 4a7254 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X4, X9, X1, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X3, X9, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 4a7240 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x6c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X12, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UDIV X8, X4, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X5, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X6, X14, [X12, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MSUB X11, X8, X7, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X10, X15, [X12, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X11, X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X13, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X12, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X12, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X24, [X12, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X16, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X25, [X12, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X18, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X26, [X12, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X24, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X12, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X25, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X12, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X26, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X12, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X23, [X12, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X27, [X12, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X5, X28, [X12, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X20, [X12, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X22, [X12, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [X12, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X21, X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X13, [X12, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SDIV X7, X21, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
STR X22, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X12, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [X12, #616]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X24, [X12, #624]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X16, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X25, [X12, #712]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X18, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X26, [X12, #752]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB X11, X7, X17, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR X24, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X12, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X25, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X27, [X12, #760]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X26, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X12, #848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X17, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X12, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X27, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [X12, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X20, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X12, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X3, [X12, #640]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CCMP X10, #1, #0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X4, [X12, #776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X21, [X12, #888]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X12, #896]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X12, #912]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X21, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X22, [X12, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X17, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [X12, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X12, #1056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X22, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #1088]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X12, #1096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X2, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.NE 4a7270 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x6f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X11, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X17, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X27, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D4, #2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X21, X1, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X12, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X10, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC X22, X7, X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X27, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X13, X22, XZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X24, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MUL X26, X11, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
SUB X20, X14, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X19, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X13, X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MUL X19, X30, X4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
SUB X27, X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X28, X6, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
MUL X6, X6, X18	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X4, X0, X4, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X2, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR XZR, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X11, X23, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X16, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X22, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X23, X0, X5, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X19, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X5, X30, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X21, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X0, X0, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X20, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X3, X30, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X23, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X30, X18, X25, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X0, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X30, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD SP, SP, #528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4a6bd4 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
MUL X25, X6, X18	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X21, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X6, X6, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FMOV D4, #2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MUL X17, X30, X4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X22, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X4, X0, X4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
CSINC X7, X7, X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X1, X1, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSEL X2, X7, XZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR XZR, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X11, X14, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X14, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X26, X24, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X19, X19, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X28, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X17, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X20, X0, X5, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STR X7, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X5, X30, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X19, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X27, X23, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X15, X15, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X23, X14, X8	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X4, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X8, X8, X10	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X10, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X5, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X0, X0, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X15, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X30, X30, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X10, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X3, X18, X24	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X26, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X23, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X30, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X20, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)

Name	Coverage (%)	Time (s)
▼std::enable_if–	1.60	0.98
▼Loop 2420 - For.hpp:142-142 - exec–	0.00	0.00
▼Loop 2421 - For.hpp:142-142 - exec–	0.00	0.00
▼Loop 2422 - For.hpp:142-142 - exec–	0.00	0.00
○Loop 2423 - For.hpp:142-142 - exec	0.79	0.47
▼Loop 2424 - For.hpp:142-142 - exec–	0.00	0.00
▼Loop 2425 - For.hpp:142-142 - exec–	0.00	0.00
▼Loop 2426 - For.hpp:142-142 - exec–	0.03	0.02
○Loop 2427 - For.hpp:142-142 - exec	0.77	0.46

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code