| Loop Id: 2423 | Module: exec | Source: For.hpp:142-142 [...] | Coverage: 0.79% |
|---|
| Loop Id: 2423 | Module: exec | Source: For.hpp:142-142 [...] | Coverage: 0.79% |
|---|
0x4a74c4 LDR D3, [X11] [3] |
0x4a74c8 ADD X4, X4, #1 |
0x4a74cc LDR D20, [X13] [4] |
0x4a74d0 LDR D6, [X10] [2] |
0x4a74d4 FADD D1, D3, D3 |
0x4a74d8 LDR D5, [X7] [10] |
0x4a74dc FADD D21, D20, D20 |
0x4a74e0 LDR D28, [X14] [1] |
0x4a74e4 LDR D0, [X2] [6] |
0x4a74e8 FDIV D2, D1, D6 |
0x4a74ec LDR D16, [X1] [5] |
0x4a74f0 FADD D29, D28, D28 |
0x4a74f4 LDR D17, [X5] [8] |
0x4a74f8 ADD X5, X5, X22 |
0x4a74fc LDR D18, [X9, X0] [12] |
0x4a7500 FDIV D22, D21, D5 |
0x4a7504 LDR D7, [X8, X0] [11] |
0x4a7508 LDR D27, [X3] [7] |
0x4a750c FDIV D30, D29, D17 |
0x4a7510 FMUL D19, D2, D0 |
0x4a7514 FMADD D23, D22, D16, D19 |
0x4a7518 FADD D24, D22, D2 |
0x4a751c FADD D25, D24, D7 |
0x4a7520 FADD D26, D23, D18 |
0x4a7524 FADD D31, D25, D30 |
0x4a7528 FMADD D7, D30, D27, D26 |
0x4a752c FDIV D16, D7, D31 |
0x4a7530 STR D16, [X6, X0] [9] |
0x4a7534 ADD X0, X0, X26 |
0x4a7538 LDR D0, [X3] [7] |
0x4a753c FNMSUB D17, D16, D4, D0 |
0x4a7540 STR D17, [X3] [7] |
0x4a7544 LDR D5, [X1] [5] |
0x4a7548 FNMSUB D6, D16, D4, D5 |
0x4a754c STR D6, [X1] [5] |
0x4a7550 ADD X1, X1, X22 |
0x4a7554 LDR D3, [X2] [6] |
0x4a7558 FNMSUB D1, D16, D4, D3 |
0x4a755c STR D1, [X2] [6] |
0x4a7560 ADD X2, X2, X22 |
0x4a7564 CMP X4, X12 |
0x4a7568 B.LT 4a74c4 |
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp: 142 - 142 |
-------------------------------------------------------------------------------- |
142: for (decltype(distance_it) i = 0; i < distance_it; ++i) |
/home/eoseret/qaas/qaas_runs/178-172-5489/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp: 88 - 106 |
-------------------------------------------------------------------------------- |
88: double xcos_dxi = 2.0 * xcos(d) / dx(i); |
89: double ycos_dyj = 2.0 * ycos(d) / dy(j); |
90: double zcos_dzk = 2.0 * zcos(d) / dz(k); |
91: |
92: Zone z(zone_layout(*k, *j, *i)); |
93: |
94: /* Calculate new zonal flux */ |
95: double psi_d_g_z = (rhs(d,g,z) |
96: + psi_lf(d, g, j, k) * xcos_dxi |
97: + psi_fr(d, g, i, k) * ycos_dyj |
98: + psi_bo(d, g, i, j) * zcos_dzk) |
99: / (xcos_dxi + ycos_dyj + zcos_dzk + sigt(g, z)); |
100: |
101: psi(d, g, z) = psi_d_g_z; |
102: |
103: /* Apply diamond-difference relationships */ |
104: psi_lf(d, g, j, k) = 2.0 * psi_d_g_z - psi_lf(d, g, j, k); |
105: psi_fr(d, g, i, k) = 2.0 * psi_d_g_z - psi_fr(d, g, i, k); |
106: psi_bo(d, g, i, j) = 2.0 * psi_d_g_z - psi_bo(d, g, i, j); |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►98.37+ | omp_fulfill_event | libgomp.so.1.0.0 | |
| ○ | start_thread | libc.so.6 | |
| ○ | thread_start | libc.so.6 | |
| ►1.63+ | GOMP_parallel | libgomp.so.1.0.0 | |
| ○ | void Kripke::DispatchHelper<Kr[...] | plugins.hpp:66 | exec |
| ○ | Kripke::Kernel::sweepSubdomain[...] | ArchLayout.h:155 | exec |
| ○ | Kripke::SweepSolver(Kripke::Co[...] | SweepSolver.cpp:78 | exec |
| ○ | Kripke::SteadyStateSolver(Krip[...] | stl_vector.h:680 | exec |
| ○ | main | new_allocator.h:79 | exec |
| ○ | __libc_start_call_main | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | iostream:74 | exec |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.17 - 2.33 |
| CQA speedup if FP arith vectorized | 2.00 |
| CQA speedup if fully vectorized | 2.00 - 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.17 - 2.33 |
| Bottlenecks | P6, P8, |
| Function | std::enable_if |
| Source | For.hpp:142-142,SweepSubdomain.cpp:88-106 |
| Source loop unroll info | unrolled by 2 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | 1 |
| CQA cycles | 7.01 - 13.99 |
| CQA cycles if no scalar integer | 6.00 |
| CQA cycles if FP arith vectorized | 6.00 - 6.99 |
| CQA cycles if fully vectorized | 3.50 - 6.99 |
| Front-end cycles | 5.25 |
| P0 cycles | 0.50 |
| P1 cycles | 0.50 |
| P2 cycles | 1.50 |
| P3 cycles | 1.50 |
| P4 cycles | 1.50 |
| P5 cycles | 1.50 |
| P6 cycles | 5.25 |
| P7 cycles | 5.25 |
| P8 cycles | 5.25 |
| P9 cycles | 5.25 |
| P10 cycles | 6.00 |
| P11 cycles | 6.00 |
| P12 cycles | 6.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 7.01 - 13.99 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 42.00 |
| Nb uops | 42.00 |
| Nb loads | NA |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 3.14 - 1.57 |
| Nb FLOP add-sub | 7.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 5.00 |
| Nb FLOP div | 4.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 0.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 0.00 |
| Bytes stored | 0.00 |
| Stride 0 | 6.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 6.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 25.00 |
| Vector-efficiency ratio load | 25.00 |
| Vector-efficiency ratio store | 25.00 |
| Vector-efficiency ratio mul | 25.00 |
| Vector-efficiency ratio add_sub | 25.00 |
| Vector-efficiency ratio fma | 25.00 |
| Vector-efficiency ratio div_sqrt | 25.00 |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.17 - 2.33 |
| CQA speedup if FP arith vectorized | 2.00 |
| CQA speedup if fully vectorized | 2.00 - 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.17 - 2.33 |
| Bottlenecks | P6, P8, |
| Function | std::enable_if |
| Source | For.hpp:142-142,SweepSubdomain.cpp:88-106 |
| Source loop unroll info | unrolled by 2 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | 1 |
| CQA cycles | 7.01 - 13.99 |
| CQA cycles if no scalar integer | 6.00 |
| CQA cycles if FP arith vectorized | 6.00 - 6.99 |
| CQA cycles if fully vectorized | 3.50 - 6.99 |
| Front-end cycles | 5.25 |
| P0 cycles | 0.50 |
| P1 cycles | 0.50 |
| P2 cycles | 1.50 |
| P3 cycles | 1.50 |
| P4 cycles | 1.50 |
| P5 cycles | 1.50 |
| P6 cycles | 5.25 |
| P7 cycles | 5.25 |
| P8 cycles | 5.25 |
| P9 cycles | 5.25 |
| P10 cycles | 6.00 |
| P11 cycles | 6.00 |
| P12 cycles | 6.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 7.01 - 13.99 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 42.00 |
| Nb uops | 42.00 |
| Nb loads | NA |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 3.14 - 1.57 |
| Nb FLOP add-sub | 7.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 5.00 |
| Nb FLOP div | 4.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 0.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 0.00 |
| Bytes stored | 0.00 |
| Stride 0 | 6.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 6.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 25.00 |
| Vector-efficiency ratio load | 25.00 |
| Vector-efficiency ratio store | 25.00 |
| Vector-efficiency ratio mul | 25.00 |
| Vector-efficiency ratio add_sub | 25.00 |
| Vector-efficiency ratio fma | 25.00 |
| Vector-efficiency ratio div_sqrt | 25.00 |
| Vector-efficiency ratio other | NA |
| Path / |
| nb instructions | 42 |
| nb uops | 42 |
| loop length | 168 |
| used w registers | 0 |
| used x registers | 17 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 24 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 0 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 7.00 |
| micro-operation queue | 5.25 cycles |
| front end | 5.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 1.50 | 1.50 | 1.50 | 1.50 | 5.25 | 5.25 | 5.25 | 5.25 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 |
| cycles | 0.50 | 0.50 | 1.50 | 1.50 | 1.50 | 1.50 | 5.25 | 5.25 | 5.25 | 5.25 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | 7.01-13.99 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 5.25 |
| Dispatch | 6.00 |
| DIV/SQRT | 7.01-13.99 |
| Data deps. | 1.00 |
| Overall L1 | 7.01-13.99 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 25% |
| load | 25% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 25% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 25% |
| add-sub | 25% |
| fma | 25% |
| div/sqrt | 25% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 25% |
| load | 25% |
| store | 25% |
| mul | 25% |
| add-sub | 25% |
| fma | 25% |
| div/sqrt | 25% |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDR D3, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD X4, X4, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR D20, [X13] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| LDR D6, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FADD D1, D3, D3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| LDR D5, [X7] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FADD D21, D20, D20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| LDR D28, [X14] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| LDR D0, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FDIV D2, D1, D6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 1.75-3.50 | scal (25.0%) |
| LDR D16, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FADD D29, D28, D28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| LDR D17, [X5] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD X5, X5, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR D18, [X9, X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FDIV D22, D21, D5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 1.75-3.50 | scal (25.0%) |
| LDR D7, [X8, X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| LDR D27, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FDIV D30, D29, D17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 1.75-3.50 | scal (25.0%) |
| FMUL D19, D2, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FMADD D23, D22, D16, D19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| FADD D24, D22, D2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FADD D25, D24, D7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FADD D26, D23, D18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FADD D31, D25, D30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FMADD D7, D30, D27, D26 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| FDIV D16, D7, D31 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 1.75-3.50 | scal (25.0%) |
| STR D16, [X6, X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADD X0, X0, X26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR D0, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNMSUB D17, D16, D4, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| STR D17, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| LDR D5, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNMSUB D6, D16, D4, D5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| STR D6, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADD X1, X1, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR D3, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNMSUB D1, D16, D4, D3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| STR D1, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADD X2, X2, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X4, X12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| B.LT 4a74c4 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x944> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| nb instructions | 42 |
| nb uops | 42 |
| loop length | 168 |
| used w registers | 0 |
| used x registers | 17 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 24 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 0 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 7.00 |
| micro-operation queue | 5.25 cycles |
| front end | 5.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 1.50 | 1.50 | 1.50 | 1.50 | 5.25 | 5.25 | 5.25 | 5.25 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 |
| cycles | 0.50 | 0.50 | 1.50 | 1.50 | 1.50 | 1.50 | 5.25 | 5.25 | 5.25 | 5.25 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | 7.01-13.99 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 5.25 |
| Dispatch | 6.00 |
| DIV/SQRT | 7.01-13.99 |
| Data deps. | 1.00 |
| Overall L1 | 7.01-13.99 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 25% |
| load | 25% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 25% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 25% |
| add-sub | 25% |
| fma | 25% |
| div/sqrt | 25% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 25% |
| load | 25% |
| store | 25% |
| mul | 25% |
| add-sub | 25% |
| fma | 25% |
| div/sqrt | 25% |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDR D3, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD X4, X4, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR D20, [X13] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| LDR D6, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FADD D1, D3, D3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| LDR D5, [X7] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FADD D21, D20, D20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| LDR D28, [X14] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| LDR D0, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FDIV D2, D1, D6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 1.75-3.50 | scal (25.0%) |
| LDR D16, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FADD D29, D28, D28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| LDR D17, [X5] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD X5, X5, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR D18, [X9, X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FDIV D22, D21, D5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 1.75-3.50 | scal (25.0%) |
| LDR D7, [X8, X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| LDR D27, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FDIV D30, D29, D17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 1.75-3.50 | scal (25.0%) |
| FMUL D19, D2, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FMADD D23, D22, D16, D19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| FADD D24, D22, D2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FADD D25, D24, D7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FADD D26, D23, D18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FADD D31, D25, D30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FMADD D7, D30, D27, D26 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| FDIV D16, D7, D31 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 1.75-3.50 | scal (25.0%) |
| STR D16, [X6, X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADD X0, X0, X26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR D0, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNMSUB D17, D16, D4, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| STR D17, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| LDR D5, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNMSUB D6, D16, D4, D5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| STR D6, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADD X1, X1, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR D3, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNMSUB D1, D16, D4, D3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| STR D1, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADD X2, X2, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X4, X12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| B.LT 4a74c4 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEENSt9enable_ifIXsrNS5_8concepts6all_ofIJNS1Z_7metalib8negate_tINS0_22loop_data_has_reducersINS5_4type2cv5rem_sINS24_3ref5rem_sIS1Q_E4typeEE4typeEEEEEEEE5valueEvE4typeEOS1Q_._omp_fn.0+0x944> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
