OV - exec - Function miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::recompute(qmcplusplus::ParticleSet&)

	Function: miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::recompute(qmcpl ...	Module: exec	Source: TwoBodyJastrowRef.h:268-402 [...]	Coverage (incl. loops): 0.07% \| (excl. loops): 0.03%

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 249

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223:     return X[i];

[...]

229:     return X[i];

[...]

249:   inline const_pointer data() const { return X; }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 244 - 273

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244:         *(_base + M * i) = rhs[i];

[...]

263:   inline Accessor operator()(size_t i) { return Accessor(myData + i, nGhosts); }

[...]

271:   inline T* restrict data(size_t i) { return myData + i * nGhosts; }

272:   ///return the const pointer of the i-th components

273:   inline const T* restrict data(size_t i) const { return myData + i * nGhosts; }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 268 - 402

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268:   const int igt = P.GroupID[iat] * NumGroups;

269:   for (int jg = 0; jg < NumGroups; ++jg)

270:   {

271:     const FuncType& f2(*F[igt + jg]);

272:     int iStart = P.first(jg);

273:     int iEnd   = std::min(jelmax, P.last(jg));

274:     f2.evaluateVGL(iat, iStart, iEnd, dist, u, du, d2u, DistCompressed.data(), DistIndice.data());

[...]

359: {

360:   const auto& d_table = P.getDistTableAA(myTableID);

361:   for (int ig = 0; ig < NumGroups; ++ig)

362:   {

363:     const int igt = ig * NumGroups;

364:     for (int iat = P.first(ig), last = P.last(ig); iat < last; ++iat)

365:     {

366:       computeU3(P, iat, d_table.getDistRow(iat).data(), cur_u.data(), cur_du.data(), cur_d2u.data(), true);

367:       Uat[iat] = std::accumulate(cur_u.begin(), cur_u.begin() + iat, valT());

[...]

375:       for (int jat = 0; jat < iat; ++jat)

376:         lap += d2u[jat] + lapfac * du[jat];

377:       for (int idim = 0; idim < OHMMS_DIM; ++idim)

378:       {

379:         const valT* restrict dX = displ.data(idim);

380:         valT s                  = valT();

381:         for (int jat = 0; jat < iat; ++jat)

382:           s += du[jat] * dX[jat];

383:         grad[idim] = s;

384:       }

385:       dUat(iat)  = grad;

386:       d2Uat[iat] = -lap;

387:       // add the contribution from the upper triangle

388:       for (int jat = 0; jat < iat; jat++)

389:       {

390:         Uat[jat] += u[jat];

391:         d2Uat[jat] -= d2u[jat] + lapfac * du[jat];

[...]

397:         for (int jat = 0; jat < iat; jat++)

398:           save_g[jat] -= du[jat] * dX[jat];

399:       }

400:     }

401:   }

402: }

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/shared_ptr_base.h: 1667 - 1667

--------------------------------------------------------------------------------

1667:       { return _M_ptr; }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 313 - 313

--------------------------------------------------------------------------------

313:   inline int first(int igroup) const { return (*group_offsets_)[igroup]; }

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h: 1131 - 1263

--------------------------------------------------------------------------------

1131: 	return *(this->_M_impl._M_start + __n);

[...]

1150: 	return *(this->_M_impl._M_start + __n);

[...]

1263:       { return _M_data_ptr(this->_M_impl._M_start); }

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_numeric.h: 140 - 141

--------------------------------------------------------------------------------

140:       for (; __first != __last; ++__first)

141: 	__init = _GLIBCXX_MOVE_IF_20(__init) + *__first;

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_algobase.h: 952 - 1146

--------------------------------------------------------------------------------

952: 	*__first = __tmp;

[...]

1146:       if (__n <= 0)

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_iterator.h: 1068 - 1068

--------------------------------------------------------------------------------

1068:       : _M_current(__i) { }

0x425800 SUB	SP, SP, #224

0x425804 STR	D8, [SP, #112]

0x425808 STP	X29, X30, [SP, #128]

0x42580c STP	X28, X27, [SP, #144]

0x425810 STP	X26, X25, [SP, #160]

0x425814 STP	X24, X23, [SP, #176]

0x425818 STP	X22, X21, [SP, #192]

0x42581c STP	X20, X19, [SP, #208]

0x425820 ADD	X29, SP, #128

0x425824 ORR	X19, XZR, X1

0x425828 LDR	W1, [X0, #584]

0x42582c ORR	X20, XZR, X0

0x425830 ORR	X0, XZR, X19

0x425834 BL	452b70

0x425838 LDR	X21, [X20, #160]

0x42583c CBZ	X21, 4264b4

0x425840 CNTW	X23, ALL

0x425844 FDUP	Z17.D, #0

0x425848 FMOV	D8, #-2.0000000

0x42584c FDUP	Z18.D, #128

0x425850 ORR	X2, XZR, X19

0x425854 ORR	X30, XZR, X0

0x425858 ORR	X9, XZR, XZR

0x42585c SUB	X8, XZR, X23

0x425860 PTRUE	P1.D, ALL

0x425864 RDVL	X26, #2

0x425868 STP	X19, X0, [SP, #24]

0x42586c STP	X8, X21, [X29, #976]

0x425870 PTRUE	P2.B, ALL

0x425874 B	425898

0x425878 HINT	#0

0x42587c HINT	#0

      (330) 0x425880 LDUR	X8, [X29, #472]

      (330) 0x425884 LDR	X9, [SP, #16]

      (330) 0x425888 STUR	X8, [X29, #472]

      (330) 0x42588c ADD	X9, X9, #1

      (330) 0x425890 CMP	X8, X9

      (330) 0x425894 B.LS	4264b4

      (330) 0x425898 LDR	X8, [X2, #616]

      (330) 0x42589c STR	X9, [SP, #16]

      (330) 0x4258a0 LDR	X8, [X8, #24]

      (330) 0x4258a4 ADD	X8, X8, X9,LSL #2

      (330) 0x4258a8 LDP	W6, W8, [X8]

      (330) 0x4258ac STR	W8, [SP, #52]

      (330) 0x4258b0 CMP	W6, W8

      (330) 0x4258b4 B.GE	425880

    (332) 0x4258b8 LDR	X5, [X20, #320]

    (332) 0x4258bc LDR	X24, [X20, #344]

    (332) 0x4258c0 LDR	X25, [X20, #368]

    (332) 0x4258c4 SBFM	X22, X6, #0, #31

    (332) 0x4258c8 MOVN	X8, #57344

    (332) 0x4258cc ORR	W9, WZR, W6

    (332) 0x4258d0 ADD	X8, X22, X8

    (332) 0x4258d4 STUR	XZR, [X29, #504]

    (332) 0x4258d8 STUR	WZR, [X29, #492]

    (332) 0x4258dc STR	X6, [SP, #64]

    (332) 0x4258e0 STR	X8, [SP, #40]

    (332) 0x4258e4 B	425918

    (332) 0x4258e8 LDUR	W9, [X29, #492]

    (332) 0x4258ec LDR	W8, [SP, #52]

    (332) 0x4258f0 ADD	X22, X22, #1

    (332) 0x4258f4 ADD	W9, W9, #1

    (332) 0x4258f8 CMP	W8, W22

    (332) 0x4258fc ORR	X8, XZR, X21

    (332) 0x425900 STUR	W9, [X29, #492]

    (332) 0x425904 LDUR	X9, [X29, #504]

    (332) 0x425908 ADD	X9, X9, #1

    (332) 0x42590c STUR	X9, [X29, #504]

    (332) 0x425910 ADD	W9, W7, #1

    (332) 0x425914 B.EQ	425884

    (332) 0x425918 LDR	X8, [X30, #72]

    (332) 0x42591c STUR	W9, [X29, #456]

    (332) 0x425920 MOVZ	W9, #40

    (332) 0x425924 CMP	X22, #1

    (332) 0x425928 UBFM	X28, X22, #61, #60

    (332) 0x42592c STUR	X25, [X29, #480]

    (332) 0x425930 ORR	X25, XZR, X5

    (332) 0x425934 MADD	X8, X22, X9, X8

    (332) 0x425938 LDR	X27, [X8, #24]

    (332) 0x42593c B.LT	425994

    (332) 0x425940 ORR	X0, XZR, X5

    (332) 0x425944 ORR	W1, WZR, WZR

    (332) 0x425948 ORR	X2, XZR, X28

    (332) 0x42594c ORR	X19, XZR, X30

    (332) 0x425950 BL	4101f0

    (332) 0x425954 ORR	X0, XZR, X24

    (332) 0x425958 ORR	W1, WZR, WZR

    (332) 0x42595c ORR	X2, XZR, X28

    (332) 0x425960 BL	4101f0

    (332) 0x425964 LDUR	X0, [X29, #480]

    (332) 0x425968 ORR	W1, WZR, WZR

    (332) 0x42596c ORR	X2, XZR, X28

    (332) 0x425970 BL	4101f0

    (332) 0x425974 LDR	X2, [SP, #24]

    (332) 0x425978 LDR	X6, [SP, #64]

    (332) 0x42597c PTRUE	P2.B, ALL

    (332) 0x425980 FDUP	Z18.D, #128

    (332) 0x425984 FDUP	Z17.D, #0

    (332) 0x425988 ORR	X30, XZR, X19

    (332) 0x42598c ORR	X5, XZR, X25

    (332) 0x425990 PTRUE	P1.D, ALL

    (332) 0x425994 LDUR	X9, [X29, #472]

    (332) 0x425998 CBZ	X9, 425ae0

    (332) 0x42599c LDR	X8, [X2, #24]

    (332) 0x4259a0 LDUR	X26, [X29, #480]

    (332) 0x4259a4 STR	X28, [SP, #56]

    (332) 0x4259a8 ORR	X19, XZR, XZR

    (332) 0x4259ac ORR	X23, XZR, X2

    (332) 0x4259b0 LDR	W8, [X8, X22,LSL #2]

    (332) 0x4259b4 MUL	W8, W8, W9

    (332) 0x4259b8 SBFM	X28, X8, #61, #31

    (332) 0x4259bc HINT	#0

      (345) 0x4259c0 LDR	X8, [X20, #512]

      (345) 0x4259c4 LDR	X9, [X20, #488]

      (345) 0x4259c8 ORR	W1, WZR, W22

      (345) 0x4259cc ORR	X4, XZR, X27

      (345) 0x4259d0 ORR	X5, XZR, X25

      (345) 0x4259d4 ORR	X6, XZR, X24

      (345) 0x4259d8 ORR	X7, XZR, X26

      (345) 0x4259dc ADD	X8, X8, X28

      (345) 0x4259e0 LDR	X0, [X8, X19,LSL #3]

      (345) 0x4259e4 LDR	X8, [X23, #616]

      (345) 0x4259e8 LDR	X8, [X8, #24]

      (345) 0x4259ec ADD	X8, X8, X19,LSL #2

      (345) 0x4259f0 LDP	W2, W8, [X8]

      (345) 0x4259f4 CMP	W8, W22

      (345) 0x4259f8 CSEL	W3, W8, W22, #11

      (345) 0x4259fc LDR	X8, [X20, #464]

      (345) 0x425a00 STP	X8, X9, [SP]

      (345) 0x425a04 BL	422660

      (345) 0x425a08 LDR	X21, [X20, #160]

      (345) 0x425a0c ADD	X19, X19, #1

      (345) 0x425a10 CMP	X21, X19

      (345) 0x425a14 B.HI	4259c0

    (332) 0x425a18 LDR	X5, [X20, #320]

    (332) 0x425a1c LDR	X30, [SP, #32]

    (332) 0x425a20 LDP	X28, X6, [SP, #56]

    (332) 0x425a24 ORR	X2, XZR, X23

    (332) 0x425a28 CNTW	X23, ALL

    (332) 0x425a2c PTRUE	P1.D, ALL

    (332) 0x425a30 FDUP	Z17.D, #0

    (332) 0x425a34 FDUP	Z18.D, #128

    (332) 0x425a38 PTRUE	P2.B, ALL

    (332) 0x425a3c RDVL	X26, #2

    (332) 0x425a40 CNTD	X27, ALL

    (332) 0x425a44 STUR	X21, [X29, #472]

    (332) 0x425a48 CBZ	X22, 425aec

    (332) 0x425a4c LDUR	X8, [X29, #504]

    (332) 0x425a50 LDR	X9, [SP, #40]

    (332) 0x425a54 MOVI	D0, #0

    (332) 0x425a58 ADD	X8, X8, X9

    (332) 0x425a5c AND	X8, X8, #0x55

    (332) 0x425a60 ADD	X9, X8, #1

    (332) 0x425a64 ORR	X8, XZR, X5

    (332) 0x425a68 CMP	X9, X23

    (332) 0x425a6c B.CC	425ab8

    (332) 0x425a70 LDUR	X11, [X29, #464]

    (332) 0x425a74 MOVI	V0.2D, #0

    (332) 0x425a78 MOVI	V1.2D, #0

    (332) 0x425a7c ORR	X12, XZR, X5

    (332) 0x425a80 AND	X10, X9, X11

    (332) 0x425a84 AND	X11, X9, X11

    (332) 0x425a88 ADD	X8, X5, X10,LSL #3

      (344) 0x425a8c LDR	Z2, [X12, MUL VL]

      (344) 0x425a90 LDR	Z3, [X12, #1, MUL VL]

      (344) 0x425a94 ADD	X12, X12, X26

      (344) 0x425a98 SUBS	X11, X11, X23

      (344) 0x425a9c FADD	Z0.D, Z2.D, Z0.D

      (344) 0x425aa0 FADD	Z1.D, Z3.D, Z1.D

      (344) 0x425aa4 B.NE	425a8c

    (332) 0x425aa8 FADD	Z0.D, Z1.D, Z0.D

    (332) 0x425aac CMP	X9, X10

    (332) 0x425ab0 FADDV	D0, P1, Z0.D

    (332) 0x425ab4 B.EQ	425af0

    (332) 0x425ab8 ADD	X9, X5, X22,LSL #3

    (332) 0x425abc HINT	#0

      (331) 0x425ac0 LDR	D1, [X8], #8

      (331) 0x425ac4 CMP	X8, X9

      (331) 0x425ac8 FADD	D0, D1, D0

      (331) 0x425acc B.NE	425ac0

    (332) 0x425ad0 B	425af0

0x425ad4 HINT	#0

0x425ad8 HINT	#0

0x425adc HINT	#0

    (332) 0x425ae0 CNTD	X27, ALL

    (332) 0x425ae4 STUR	XZR, [X29, #472]

    (332) 0x425ae8 CBNZ	X22, 425a4c

    (332) 0x425aec MOVI	D0, #0

    (332) 0x425af0 LDR	X10, [X30, #96]

    (332) 0x425af4 LDUR	W9, [X29, #492]

    (332) 0x425af8 LDUR	W8, [X29, #456]

    (332) 0x425afc MOVZ	W11, #40

    (332) 0x425b00 CMP	X22, #1

    (332) 0x425b04 MADD	X11, X22, X11, X10

    (332) 0x425b08 LDR	X15, [X20, #216]

    (332) 0x425b0c LDR	X24, [X20, #344]

    (332) 0x425b10 LDR	X25, [X20, #368]

    (332) 0x425b14 ADD	W0, W6, W9

    (332) 0x425b18 ORR	W7, WZR, W8

    (332) 0x425b1c STR	D0, [X15, X22,LSL #3]

    (332) 0x425b20 B.LT	425b40

    (332) 0x425b24 CMP	X23, X0

    (332) 0x425b28 B.LS	425b60

    (332) 0x425b2c ORR	X10, XZR, XZR

    (332) 0x425b30 MOVI	D0, #0

    (332) 0x425b34 B	425bc0

0x425b38 HINT	#0

0x425b3c HINT	#0

    (332) 0x425b40 LDR	X10, [X11, #24]

    (332) 0x425b44 LDR	X9, [X11, #8]

    (332) 0x425b48 MOVI	D0, #0

    (332) 0x425b4c MOVI	D1, #0

    (332) 0x425b50 MOVI	D2, #0

    (332) 0x425b54 MOVI	D3, #0

    (332) 0x425b58 B	425dc4

0x425b5c HINT	#0

    (332) 0x425b60 LDUR	X14, [X29, #464]

    (332) 0x425b64 MOVI	V0.2D, #0

    (332) 0x425b68 MOVI	V1.2D, #0

    (332) 0x425b6c ORR	X12, XZR, X25

    (332) 0x425b70 ORR	X13, XZR, X24

    (332) 0x425b74 AND	X10, X14, X0

    (332) 0x425b78 AND	X14, X14, X0

    (332) 0x425b7c HINT	#0

      (336) 0x425b80 LDR	Z2, [X12, MUL VL]

      (336) 0x425b84 LDR	Z3, [X12, #1, MUL VL]

      (336) 0x425b88 SUBS	X14, X14, X23

      (336) 0x425b8c ADD	X12, X12, X26

      (336) 0x425b90 FADD	Z0.D, Z2.D, Z0.D

      (336) 0x425b94 LDR	Z4, [X13, MUL VL]

      (336) 0x425b98 LDR	Z5, [X13, #1, MUL VL]

      (336) 0x425b9c FADD	Z1.D, Z3.D, Z1.D

      (336) 0x425ba0 ADD	X13, X13, X26

      (336) 0x425ba4 FMLA	Z0.D, P1/M, Z4.D, Z17.D

      (336) 0x425ba8 FMLA	Z1.D, P1/M, Z5.D, Z17.D

      (336) 0x425bac B.NE	425b80

    (332) 0x425bb0 FADD	Z0.D, Z1.D, Z0.D

    (332) 0x425bb4 CMP	X10, X0

    (332) 0x425bb8 FADDV	D0, P1, Z0.D

    (332) 0x425bbc B.EQ	425be8

    (332) 0x425bc0 ADD	X12, X24, X10,LSL #3

    (332) 0x425bc4 ADD	X13, X25, X10,LSL #3

    (332) 0x425bc8 SUB	X10, X7, X10

      (343) 0x425bcc LDR	D1, [X13], #8

      (343) 0x425bd0 LDR	D2, [X12], #8

      (343) 0x425bd4 SUBS	X10, X10, #1

      (343) 0x425bd8 FADD	D2, D2, D2

      (343) 0x425bdc FADD	D0, D1, D0

      (343) 0x425be0 FADD	D0, D0, D2

      (343) 0x425be4 B.NE	425bcc

    (332) 0x425be8 LDR	X10, [X11, #24]

    (332) 0x425bec CMP	X23, X0

    (332) 0x425bf0 B.LS	425c00

    (332) 0x425bf4 ORR	X12, XZR, XZR

    (332) 0x425bf8 MOVI	D1, #0

    (332) 0x425bfc B	425c58

    (332) 0x425c00 LDUR	X16, [X29, #464]

    (332) 0x425c04 MOVI	V1.2D, #0

    (332) 0x425c08 MOVI	V2.2D, #0

    (332) 0x425c0c ORR	X13, XZR, X24

    (332) 0x425c10 ORR	X14, XZR, X10

    (332) 0x425c14 AND	X12, X16, X0

    (332) 0x425c18 AND	X16, X16, X0

    (332) 0x425c1c HINT	#0

      (337) 0x425c20 LDR	Z3, [X13, MUL VL]

      (337) 0x425c24 LDR	Z4, [X13, #1, MUL VL]

      (337) 0x425c28 SUBS	X16, X16, X23

      (337) 0x425c2c ADD	X13, X13, X26

      (337) 0x425c30 LDR	Z5, [X14, MUL VL]

      (337) 0x425c34 FMLA	Z1.D, P1/M, Z5.D, Z3.D

      (337) 0x425c38 LDR	Z6, [X14, #1, MUL VL]

      (337) 0x425c3c FMLA	Z2.D, P1/M, Z6.D, Z4.D

      (337) 0x425c40 ADD	X14, X14, X26

      (337) 0x425c44 B.NE	425c20

    (332) 0x425c48 FADD	Z1.D, Z2.D, Z1.D

    (332) 0x425c4c CMP	X12, X0

    (332) 0x425c50 FADDV	D1, P1, Z1.D

    (332) 0x425c54 B.EQ	425c78

    (332) 0x425c58 ADD	X13, X24, X12,LSL #3

    (332) 0x425c5c ADD	X14, X10, X12,LSL #3

    (332) 0x425c60 SUB	X12, X7, X12

      (342) 0x425c64 LDR	D2, [X13], #8

      (342) 0x425c68 LDR	D3, [X14], #8

      (342) 0x425c6c SUBS	X12, X12, #1

      (342) 0x425c70 FMADD	D1, D3, D2, D1

      (342) 0x425c74 B.NE	425c64

    (332) 0x425c78 LDR	X9, [X11, #8]

    (332) 0x425c7c CMP	X23, X0

    (332) 0x425c80 B.LS	425ca0

    (332) 0x425c84 ORR	X12, XZR, XZR

    (332) 0x425c88 MOVI	D2, #0

    (332) 0x425c8c B	425cfc

0x425c90 HINT	#0

0x425c94 HINT	#0

0x425c98 HINT	#0

0x425c9c HINT	#0

    (332) 0x425ca0 LDUR	X12, [X29, #464]

    (332) 0x425ca4 RDVL	X16, #1

    (332) 0x425ca8 ADD	X14, X10, X9,LSL #3

    (332) 0x425cac MOVI	V2.2D, #0

    (332) 0x425cb0 MOVI	V3.2D, #0

    (332) 0x425cb4 ORR	X13, XZR, XZR

    (332) 0x425cb8 ORR	X17, XZR, X24

    (332) 0x425cbc ADD	X16, X14, X16

    (332) 0x425cc0 AND	X12, X12, X0

      (338) 0x425cc4 LDR	Z4, [X17, MUL VL]

      (338) 0x425cc8 LDR	Z5, [X17, #1, MUL VL]

      (338) 0x425ccc ADD	X17, X17, X26

      (338) 0x425cd0 LD1D	{Z6.D}, P1/Z, [X14, X13,LSL #3]

      (338) 0x425cd4 FMLA	Z2.D, P1/M, Z6.D, Z4.D

      (338) 0x425cd8 LD1D	{Z7.D}, P1/Z, [X16, X13,LSL #3]

      (338) 0x425cdc FMLA	Z3.D, P1/M, Z7.D, Z5.D

      (338) 0x425ce0 ADD	X13, X13, X23

      (338) 0x425ce4 CMP	X12, X13

      (338) 0x425ce8 B.NE	425cc4

    (332) 0x425cec FADD	Z2.D, Z3.D, Z2.D

    (332) 0x425cf0 CMP	X12, X0

    (332) 0x425cf4 FADDV	D2, P1, Z2.D

    (332) 0x425cf8 B.EQ	425d34

    (332) 0x425cfc UBFM	X14, X12, #61, #60

    (332) 0x425d00 SUB	X13, X7, X12

    (332) 0x425d04 ADD	X12, X24, X12,LSL #3

    (332) 0x425d08 ADD	X14, X14, X9,LSL #3

    (332) 0x425d0c ADD	X14, X10, X14

    (332) 0x425d10 HINT	#0

    (332) 0x425d14 HINT	#0

    (332) 0x425d18 HINT	#0

    (332) 0x425d1c HINT	#0

      (341) 0x425d20 LDR	D3, [X12], #8

      (341) 0x425d24 LDR	D4, [X14], #8

      (341) 0x425d28 SUBS	X13, X13, #1

      (341) 0x425d2c FMADD	D2, D4, D3, D2

      (341) 0x425d30 B.NE	425d20

    (332) 0x425d34 CMP	X23, X0

    (332) 0x425d38 B.LS	425d48

    (332) 0x425d3c ORR	X12, XZR, XZR

    (332) 0x425d40 MOVI	D3, #0

    (332) 0x425d44 B	425d9c

    (332) 0x425d48 LDUR	X16, [X29, #464]

    (332) 0x425d4c MOVI	V3.2D, #0

    (332) 0x425d50 MOVI	V4.2D, #0

    (332) 0x425d54 ADD	X13, X10, X9,LSL #4

    (332) 0x425d58 ORR	X14, XZR, X24

    (332) 0x425d5c AND	X12, X16, X0

    (332) 0x425d60 AND	X16, X16, X0

      (339) 0x425d64 LDR	Z5, [X14, MUL VL]

      (339) 0x425d68 LDR	Z6, [X14, #1, MUL VL]

      (339) 0x425d6c SUBS	X16, X16, X23

      (339) 0x425d70 ADD	X14, X14, X26

      (339) 0x425d74 LDR	Z7, [X13, MUL VL]

      (339) 0x425d78 FMLA	Z3.D, P1/M, Z7.D, Z5.D

      (339) 0x425d7c LDR	Z16, [X13, #1, MUL VL]

      (339) 0x425d80 FMLA	Z4.D, P1/M, Z16.D, Z6.D

      (339) 0x425d84 ADD	X13, X13, X26

      (339) 0x425d88 B.NE	425d64

    (332) 0x425d8c FADD	Z3.D, Z4.D, Z3.D

    (332) 0x425d90 CMP	X12, X0

    (332) 0x425d94 FADDV	D3, P1, Z3.D

    (332) 0x425d98 B.EQ	425dc4

    (332) 0x425d9c UBFM	X14, X9, #60, #59

    (332) 0x425da0 SUB	X13, X7, X12

    (332) 0x425da4 ADD	X14, X14, X12,LSL #3

    (332) 0x425da8 ADD	X12, X24, X12,LSL #3

      (340) 0x425dac LDR	D4, [X12], #8

      (340) 0x425db0 LDR	D5, [X10, X14]

      (340) 0x425db4 SUBS	X13, X13, #1

      (340) 0x425db8 ADD	X14, X14, #8

      (340) 0x425dbc FMADD	D3, D5, D4, D3

      (340) 0x425dc0 B.NE	425dac

    (332) 0x425dc4 LDR	X12, [X20, #256]

    (332) 0x425dc8 LDR	X16, [X20, #240]

    (332) 0x425dcc LDR	X18, [X20, #296]

    (332) 0x425dd0 FNEG	D0, D0

    (332) 0x425dd4 CMP	X22, #1

    (332) 0x425dd8 ADD	X14, X12, X22,LSL #3

    (332) 0x425ddc UBFM	X8, X16, #60, #59

    (332) 0x425de0 STR	D1, [X14]

    (332) 0x425de4 STR	D2, [X14, X16,LSL #3]

    (332) 0x425de8 STR	D3, [X14, X8]

    (332) 0x425dec STR	D0, [X18, X28]

    (332) 0x425df0 B.LT	4258e8

  (335) 0x425df4 LDUR	X14, [X29, #504]

  (335) 0x425df8 UBFM	X17, X0, #61, #31

  (335) 0x425dfc ORR	X13, XZR, X6

  (335) 0x425e00 STUR	X0, [X29, #480]

  (335) 0x425e04 STUR	X9, [X29, #456]

  (335) 0x425e08 ORR	X9, XZR, X7

  (335) 0x425e0c ADD	X3, X5, X17

  (335) 0x425e10 ADD	X4, X25, X17

  (335) 0x425e14 ADD	X28, X24, X17

  (335) 0x425e18 ORR	X19, XZR, X2

  (335) 0x425e1c ADD	X7, X18, X17

  (335) 0x425e20 ORR	X26, XZR, X25

  (335) 0x425e24 CMP	X15, X3

  (335) 0x425e28 ADD	W11, W6, W14

  (335) 0x425e2c ADD	X6, X15, X17

  (335) 0x425e30 ORR	X14, XZR, X5

  (335) 0x425e34 CCMP	X5, X6, #2, #3

  (335) 0x425e38 CSINC	W0, WZR, WZR, #2

  (335) 0x425e3c CMP	X15, X4

  (335) 0x425e40 CCMP	X25, X6, #2, #3

  (335) 0x425e44 CSINC	W1, WZR, WZR, #2

  (335) 0x425e48 CMP	X15, X28

  (335) 0x425e4c CCMP	X24, X6, #2, #3

  (335) 0x425e50 CSINC	W2, WZR, WZR, #2

  (335) 0x425e54 CMP	X18, X3

  (335) 0x425e58 CCMP	X5, X7, #2, #3

  (335) 0x425e5c CSINC	W3, WZR, WZR, #2

  (335) 0x425e60 CMP	X18, X4

  (335) 0x425e64 CCMP	X25, X7, #2, #3

  (335) 0x425e68 CSINC	W4, WZR, WZR, #2

  (335) 0x425e6c CMP	X18, X28

  (335) 0x425e70 CCMP	X24, X7, #2, #3

  (335) 0x425e74 CSINC	W5, WZR, WZR, #2

  (335) 0x425e78 CMP	X18, X6

  (335) 0x425e7c CCMP	X15, X7, #2, #3

  (335) 0x425e80 B.CC	425f20

  (335) 0x425e84 TBNZ	W0, #0, 425f20

  (335) 0x425e88 TBNZ	W1, #0, 425f20

  (335) 0x425e8c TBNZ	W2, #0, 425f20

  (335) 0x425e90 TBNZ	W3, #0, 425f20

  (335) 0x425e94 TBNZ	W4, #0, 425f20

  (335) 0x425e98 CBNZ	W5, 425f20

  (335) 0x425e9c LDUR	X4, [X29, #480]

  (335) 0x425ea0 ORR	X7, XZR, X9

  (335) 0x425ea4 LDUR	X9, [X29, #456]

  (335) 0x425ea8 ORR	X25, XZR, X26

  (335) 0x425eac RDVL	X26, #2

  (335) 0x425eb0 ORR	X0, XZR, XZR

  (335) 0x425eb4 ORR	X5, XZR, X14

  (335) 0x425eb8 ORR	X6, XZR, X13

  (335) 0x425ebc ORR	X13, XZR, X8

  (335) 0x425ec0 ORR	X14, XZR, X11

  (335) 0x425ec4 SUBS	X1, X4, X27

  (335) 0x425ec8 CSEL	X1, XZR, X1, #3

  (335) 0x425ecc WHILELO	P0.D, XZR, X4

  (335) 0x425ed0 HINT	#0

  (335) 0x425ed4 HINT	#0

  (335) 0x425ed8 HINT	#0

  (335) 0x425edc HINT	#0

    (334) 0x425ee0 LD1D	{Z0.D}, P0/Z, [X5, X0,LSL #3]

    (334) 0x425ee4 LD1D	{Z1.D}, P0/Z, [X15, X0,LSL #3]

    (334) 0x425ee8 FADD	Z0.D, Z1.D, Z0.D

    (334) 0x425eec LD1D	{Z1.D}, P0/Z, [X24, X0,LSL #3]

    (334) 0x425ef0 LD1D	{Z2.D}, P0/Z, [X18, X0,LSL #3]

    (334) 0x425ef4 ST1D	{Z0.D}, P0, [X15, X0,LSL #3]

    (334) 0x425ef8 LD1D	{Z0.D}, P0/Z, [X25, X0,LSL #3]

    (334) 0x425efc FNMLS	Z0.D, P1/M, Z1.D, Z18.D

    (334) 0x425f00 FADD	Z0.D, Z0.D, Z2.D

    (334) 0x425f04 ST1D	{Z0.D}, P0, [X18, X0,LSL #3]

    (334) 0x425f08 ADD	X0, X0, X27

    (334) 0x425f0c SUB	X2, X0, X27

    (334) 0x425f10 WHILELO	P0.D, X2, X1

    (334) 0x425f14 B.MI	425ee0

  (335) 0x425f18 B	42602c

0x425f1c HINT	#0

(333) 0x425f20 CMP	W11, #1

(333) 0x425f24 B.NE	425f54

(333) 0x425f28 ORR	X7, XZR, X9

(333) 0x425f2c LDUR	X4, [X29, #480]

(333) 0x425f30 LDUR	X9, [X29, #456]

(333) 0x425f34 ORR	X0, XZR, XZR

(333) 0x425f38 ORR	X5, XZR, X14

(333) 0x425f3c ORR	X6, XZR, X13

(333) 0x425f40 ORR	X25, XZR, X26

(333) 0x425f44 RDVL	X26, #2

(333) 0x425f48 ORR	X13, XZR, X8

(333) 0x425f4c ORR	X14, XZR, X11

(333) 0x425f50 B	426004

(333) 0x425f54 AND	X1, X9, #0x0

(333) 0x425f58 ADD	X2, X15, #8

(333) 0x425f5c ADD	X3, X14, #8

(333) 0x425f60 ADD	X4, X26, #8

(333) 0x425f64 ORR	X0, XZR, XZR

(333) 0x425f68 ORR	X7, XZR, X9

(333) 0x425f6c ADD	X5, X18, #8

(333) 0x425f70 ADD	X6, X24, #8

(333) 0x425f74 SUB	X1, XZR, X1

(333) 0x425f78 HINT	#0

(333) 0x425f7c HINT	#0

  (329) 0x425f80 LDUR	D0, [X3, #504]

  (329) 0x425f84 LDUR	D1, [X2, #504]

  (329) 0x425f88 SUB	X0, X0, #2

  (329) 0x425f8c CMP	X1, X0

  (329) 0x425f90 FADD	D0, D1, D0

  (329) 0x425f94 STUR	D0, [X2, #504]

  (329) 0x425f98 LDUR	D0, [X4, #504]

  (329) 0x425f9c LDUR	D1, [X6, #504]

  (329) 0x425fa0 LDUR	D2, [X5, #504]

  (329) 0x425fa4 FNMSUB	D0, D1, D8, D0

  (329) 0x425fa8 FADD	D0, D0, D2

  (329) 0x425fac STUR	D0, [X5, #504]

  (329) 0x425fb0 LDR	D0, [X3], #16

  (329) 0x425fb4 LDR	D1, [X2]

  (329) 0x425fb8 FADD	D0, D1, D0

  (329) 0x425fbc STR	D0, [X2], #16

  (329) 0x425fc0 LDR	D0, [X4], #16

  (329) 0x425fc4 LDR	D2, [X5]

  (329) 0x425fc8 LDR	D1, [X6], #16

  (329) 0x425fcc FNMSUB	D0, D1, D8, D0

  (329) 0x425fd0 FADD	D0, D0, D2

  (329) 0x425fd4 STR	D0, [X5], #16

  (329) 0x425fd8 B.NE	425f80

(333) 0x425fdc LDUR	X4, [X29, #480]

(333) 0x425fe0 LDUR	X9, [X29, #456]

(333) 0x425fe4 ORR	X25, XZR, X26

(333) 0x425fe8 RDVL	X26, #2

(333) 0x425fec ORR	X5, XZR, X14

(333) 0x425ff0 ORR	X6, XZR, X13

(333) 0x425ff4 ORR	X13, XZR, X8

(333) 0x425ff8 ORR	X14, XZR, X11

(333) 0x425ffc TBZ	W14, #0, 42602c

(333) 0x426000 SUB	X0, XZR, X0

(333) 0x426004 LDR	D0, [X5, X0,LSL #3]

(333) 0x426008 LDR	D1, [X15, X0,LSL #3]

(333) 0x42600c FADD	D0, D1, D0

(333) 0x426010 STR	D0, [X15, X0,LSL #3]

(333) 0x426014 LDR	D0, [X25, X0,LSL #3]

(333) 0x426018 LDR	D1, [X24, X0,LSL #3]

(333) 0x42601c LDR	D2, [X18, X0,LSL #3]

(333) 0x426020 FNMSUB	D0, D1, D8, D0

(333) 0x426024 FADD	D0, D0, D2

(333) 0x426028 STR	D0, [X18, X0,LSL #3]

  (335) 0x42602c CMP	X23, X4

  (335) 0x426030 B.LS	426108

  (335) 0x426034 ORR	X15, XZR, XZR

  (335) 0x426038 SUB	W18, W14, W15

  (335) 0x42603c ORR	X1, XZR, X15

  (335) 0x426040 ANDS	XZR, X18, #0x3

  (335) 0x426044 B.EQ	426080

  (335) 0x426048 SUB	W18, W7, W15

  (335) 0x42604c ORR	X1, XZR, X15

  (335) 0x426050 AND	X18, X18, #0x3

  (335) 0x426054 HINT	#0

  (335) 0x426058 HINT	#0

  (335) 0x42605c HINT	#0

    (353) 0x426060 LDR	D0, [X24, X1,LSL #3]

    (353) 0x426064 LDR	D1, [X10, X1,LSL #3]

    (353) 0x426068 LDR	D2, [X12, X1,LSL #3]

    (353) 0x42606c SUBS	X18, X18, #1

    (353) 0x426070 FMSUB	D0, D1, D0, D2

    (353) 0x426074 STR	D0, [X12, X1,LSL #3]

    (353) 0x426078 ADD	X1, X1, #1

    (353) 0x42607c B.NE	426060

  (335) 0x426080 SUB	X15, X15, X14

  (335) 0x426084 CMN	X15, #4

  (335) 0x426088 B.HI	42618c

  (335) 0x42608c SUB	X15, X7, X1

  (335) 0x426090 ADD	X18, X12, X1,LSL #3

  (335) 0x426094 ADD	X0, X10, X1,LSL #3

  (335) 0x426098 ADD	X1, X24, X1,LSL #3

  (335) 0x42609c ADD	X18, X18, #16

  (335) 0x4260a0 ADD	X0, X0, #16

  (335) 0x4260a4 ADD	X1, X1, #16

    (352) 0x4260a8 LDUR	D0, [X1, #496]

    (352) 0x4260ac LDUR	D1, [X0, #496]

    (352) 0x4260b0 LDP	D2, D3, [X18, #1008]

    (352) 0x4260b4 SUBS	X15, X15, #4

    (352) 0x4260b8 FMSUB	D0, D1, D0, D2

    (352) 0x4260bc STUR	D0, [X18, #496]

    (352) 0x4260c0 LDUR	D0, [X1, #504]

    (352) 0x4260c4 LDUR	D1, [X0, #504]

    (352) 0x4260c8 FMSUB	D0, D1, D0, D3

    (352) 0x4260cc LDP	D2, D3, [X18]

    (352) 0x4260d0 STUR	D0, [X18, #504]

    (352) 0x4260d4 LDR	D0, [X1]

    (352) 0x4260d8 LDR	D1, [X0]

    (352) 0x4260dc FMSUB	D0, D1, D0, D2

    (352) 0x4260e0 STR	D0, [X18]

    (352) 0x4260e4 LDR	D0, [X1, #8]

    (352) 0x4260e8 LDR	D1, [X0, #8]

    (352) 0x4260ec ADD	X0, X0, #32

    (352) 0x4260f0 ADD	X1, X1, #32

    (352) 0x4260f4 FMSUB	D0, D1, D0, D3

    (352) 0x4260f8 STR	D0, [X18, #8]

    (352) 0x4260fc ADD	X18, X18, #32

    (352) 0x426100 B.NE	4260a8

  (335) 0x426104 B	42618c

  (335) 0x426108 ADD	X18, X10, X17

  (335) 0x42610c ADD	X0, X12, X17

  (335) 0x426110 ADD	X1, X24, X17

  (335) 0x426114 ORR	X15, XZR, XZR

  (335) 0x426118 CMP	X12, X18

  (335) 0x42611c CCMP	X10, X0, #2, #3

  (335) 0x426120 CSINC	W18, WZR, WZR, #2

  (335) 0x426124 CMP	X24, X0

  (335) 0x426128 CCMP	X12, X1, #2, #3

  (335) 0x42612c B.CC	426038

  (335) 0x426130 TBNZ	W18, #0, 426038

  (335) 0x426134 LDUR	X0, [X29, #464]

  (335) 0x426138 ORR	X18, XZR, XZR

  (335) 0x42613c AND	X15, X0, X4

  (335) 0x426140 AND	X0, X0, X4

    (354) 0x426144 ADD	X1, X24, X18

    (354) 0x426148 LD1B	{Z0.B}, P2/Z, [X24, X18]

    (354) 0x42614c LD1B	{Z2.B}, P2/Z, [X10, X18]

    (354) 0x426150 SUBS	X0, X0, X23

    (354) 0x426154 LD1B	{Z4.B}, P2/Z, [X12, X18]

    (354) 0x426158 FMSB	Z0.D, P1/M, Z2.D, Z4.D

    (354) 0x42615c LDR	Z1, [X1, #1, MUL VL]

    (354) 0x426160 ADD	X1, X10, X18

    (354) 0x426164 LDR	Z3, [X1, #1, MUL VL]

    (354) 0x426168 ADD	X1, X12, X18

    (354) 0x42616c LDR	Z5, [X1, #1, MUL VL]

    (354) 0x426170 FMSB	Z1.D, P1/M, Z3.D, Z5.D

    (354) 0x426174 ST1B	{Z0.B}, P2, [X12, X18]

    (354) 0x426178 ADD	X18, X18, X26

    (354) 0x42617c STR	Z1, [X1, #1, MUL VL]

    (354) 0x426180 B.NE	426144

  (335) 0x426184 CMP	X15, X4

  (335) 0x426188 B.NE	426038

  (335) 0x42618c ADD	X15, X12, X16,LSL #3

  (335) 0x426190 ADD	X18, X10, X9,LSL #3

  (335) 0x426194 CMP	X23, X4

  (335) 0x426198 B.LS	426280

  (335) 0x42619c ORR	X0, XZR, XZR

  (335) 0x4261a0 SUB	W1, W14, W0

  (335) 0x4261a4 ANDS	XZR, X1, #0x3

  (335) 0x4261a8 ORR	X1, XZR, X0

  (335) 0x4261ac B.EQ	4261e0

  (335) 0x4261b0 SUB	W1, W7, W0

  (335) 0x4261b4 AND	X2, X1, #0x3

  (335) 0x4261b8 ORR	X1, XZR, X0

  (335) 0x4261bc HINT	#0

    (350) 0x4261c0 LDR	D0, [X24, X1,LSL #3]

    (350) 0x4261c4 LDR	D1, [X18, X1,LSL #3]

    (350) 0x4261c8 LDR	D2, [X15, X1,LSL #3]

    (350) 0x4261cc SUBS	X2, X2, #1

    (350) 0x4261d0 FMSUB	D0, D1, D0, D2

    (350) 0x4261d4 STR	D0, [X15, X1,LSL #3]

    (350) 0x4261d8 ADD	X1, X1, #1

    (350) 0x4261dc B.NE	4261c0

  (335) 0x4261e0 SUB	X15, X0, X14

  (335) 0x4261e4 CMN	X15, #4

  (335) 0x4261e8 B.HI	426328

  (335) 0x4261ec UBFM	X18, X1, #61, #60

  (335) 0x4261f0 UBFM	X0, X9, #61, #60

  (335) 0x4261f4 SUB	X15, X7, X1

  (335) 0x4261f8 ADD	X18, X18, X16,LSL #3

  (335) 0x4261fc ADD	X0, X0, X1,LSL #3

  (335) 0x426200 ADD	X1, X24, X1,LSL #3

  (335) 0x426204 ADD	X18, X12, X18

  (335) 0x426208 ADD	X0, X10, X0

  (335) 0x42620c ADD	X1, X1, #16

  (335) 0x426210 ADD	X18, X18, #16

  (335) 0x426214 ADD	X0, X0, #16

  (335) 0x426218 HINT	#0

  (335) 0x42621c HINT	#0

    (349) 0x426220 LDUR	D0, [X1, #496]

    (349) 0x426224 LDUR	D1, [X0, #496]

    (349) 0x426228 LDP	D2, D3, [X18, #1008]

    (349) 0x42622c SUBS	X15, X15, #4

    (349) 0x426230 FMSUB	D0, D1, D0, D2

    (349) 0x426234 STUR	D0, [X18, #496]

    (349) 0x426238 LDUR	D0, [X1, #504]

    (349) 0x42623c LDUR	D1, [X0, #504]

    (349) 0x426240 FMSUB	D0, D1, D0, D3

    (349) 0x426244 LDP	D2, D3, [X18]

    (349) 0x426248 STUR	D0, [X18, #504]

    (349) 0x42624c LDR	D0, [X1]

    (349) 0x426250 LDR	D1, [X0]

    (349) 0x426254 FMSUB	D0, D1, D0, D2

    (349) 0x426258 STR	D0, [X18]

    (349) 0x42625c LDR	D0, [X1, #8]

    (349) 0x426260 LDR	D1, [X0, #8]

    (349) 0x426264 ADD	X0, X0, #32

    (349) 0x426268 ADD	X1, X1, #32

    (349) 0x42626c FMSUB	D0, D1, D0, D3

    (349) 0x426270 STR	D0, [X18, #8]

    (349) 0x426274 ADD	X18, X18, #32

    (349) 0x426278 B.NE	426220

  (335) 0x42627c B	426328

  (335) 0x426280 ADD	X1, X16, X4

  (335) 0x426284 ADD	X3, X24, X17

  (335) 0x426288 ORR	X0, XZR, XZR

  (335) 0x42628c ADD	X2, X12, X1,LSL #3

  (335) 0x426290 ADD	X1, X9, X4

  (335) 0x426294 ADD	X1, X10, X1,LSL #3

  (335) 0x426298 CMP	X15, X1

  (335) 0x42629c CCMP	X18, X2, #2, #3

  (335) 0x4262a0 CSINC	W1, WZR, WZR, #2

  (335) 0x4262a4 CMP	X24, X2

  (335) 0x4262a8 CCMP	X15, X3, #2, #3

  (335) 0x4262ac B.CC	4261a0

  (335) 0x4262b0 TBNZ	W1, #0, 4261a0

  (335) 0x4262b4 ORR	X8, XZR, X4

  (335) 0x4262b8 LDUR	X4, [X29, #464]

  (335) 0x4262bc ADD	X2, X10, X9,LSL #3

  (335) 0x4262c0 ADD	X3, X12, X16,LSL #3

  (335) 0x4262c4 ORR	X1, XZR, X24

  (335) 0x4262c8 AND	X0, X4, X8

  (335) 0x4262cc AND	X4, X4, X8

  (335) 0x4262d0 HINT	#0

  (335) 0x4262d4 HINT	#0

  (335) 0x4262d8 HINT	#0

  (335) 0x4262dc HINT	#0

    (351) 0x4262e0 LDR	Z0, [X1, MUL VL]

    (351) 0x4262e4 LDR	Z1, [X1, #1, MUL VL]

    (351) 0x4262e8 SUBS	X4, X4, X23

    (351) 0x4262ec ADD	X1, X1, X26

    (351) 0x4262f0 LDR	Z2, [X2, MUL VL]

    (351) 0x4262f4 LDR	Z3, [X2, #1, MUL VL]

    (351) 0x4262f8 ADD	X2, X2, X26

    (351) 0x4262fc LDR	Z4, [X3, MUL VL]

    (351) 0x426300 FMSB	Z0.D, P1/M, Z2.D, Z4.D

    (351) 0x426304 LDR	Z5, [X3, #1, MUL VL]

    (351) 0x426308 FMSB	Z1.D, P1/M, Z3.D, Z5.D

    (351) 0x42630c STR	Z0, [X3, MUL VL]

    (351) 0x426310 STR	Z1, [X3, #1, MUL VL]

    (351) 0x426314 ADD	X3, X3, X26

    (351) 0x426318 B.NE	4262e0

  (335) 0x42631c LDUR	X4, [X29, #480]

  (335) 0x426320 CMP	X0, X4

  (335) 0x426324 B.NE	4261a0

  (335) 0x426328 ADD	X16, X12, X16,LSL #4

  (335) 0x42632c UBFM	X15, X9, #60, #59

  (335) 0x426330 ADD	X11, X10, X9,LSL #4

  (335) 0x426334 CMP	X23, X4

  (335) 0x426338 B.LS	426420

  (335) 0x42633c ORR	X18, XZR, XZR

  (335) 0x426340 ORR	X2, XZR, X19

  (335) 0x426344 SUB	W9, W14, W18

  (335) 0x426348 ORR	X17, XZR, X18

  (335) 0x42634c ANDS	XZR, X9, #0x3

  (335) 0x426350 B.EQ	426380

  (335) 0x426354 SUB	W9, W7, W18

  (335) 0x426358 ORR	X17, XZR, X18

  (335) 0x42635c AND	X9, X9, #0x3

    (347) 0x426360 LDR	D0, [X24, X17,LSL #3]

    (347) 0x426364 LDR	D1, [X11, X17,LSL #3]

    (347) 0x426368 LDR	D2, [X16, X17,LSL #3]

    (347) 0x42636c SUBS	X9, X9, #1

    (347) 0x426370 FMSUB	D0, D1, D0, D2

    (347) 0x426374 STR	D0, [X16, X17,LSL #3]

    (347) 0x426378 ADD	X17, X17, #1

    (347) 0x42637c B.NE	426360

  (335) 0x426380 SUB	X9, X18, X14

  (335) 0x426384 CMN	X9, #4

  (335) 0x426388 B.HI	4258e8

  (335) 0x42638c ADD	X11, X13, X17,LSL #3

  (335) 0x426390 SUB	X9, X7, X17

  (335) 0x426394 ADD	X11, X12, X11

  (335) 0x426398 ADD	X12, X15, X17,LSL #3

  (335) 0x42639c ADD	X10, X10, X12

  (335) 0x4263a0 ADD	X12, X24, X17,LSL #3

  (335) 0x4263a4 ADD	X11, X11, #16

  (335) 0x4263a8 ADD	X10, X10, #16

  (335) 0x4263ac ADD	X12, X12, #16

  (335) 0x4263b0 HINT	#0

  (335) 0x4263b4 HINT	#0

  (335) 0x4263b8 HINT	#0

  (335) 0x4263bc HINT	#0

    (346) 0x4263c0 LDUR	D0, [X12, #496]

    (346) 0x4263c4 LDUR	D1, [X10, #496]

    (346) 0x4263c8 LDP	D2, D3, [X11, #1008]

    (346) 0x4263cc SUBS	X9, X9, #4

    (346) 0x4263d0 FMSUB	D0, D1, D0, D2

    (346) 0x4263d4 STUR	D0, [X11, #496]

    (346) 0x4263d8 LDUR	D0, [X12, #504]

    (346) 0x4263dc LDUR	D1, [X10, #504]

    (346) 0x4263e0 FMSUB	D0, D1, D0, D3

    (346) 0x4263e4 LDP	D2, D3, [X11]

    (346) 0x4263e8 STUR	D0, [X11, #504]

    (346) 0x4263ec LDR	D0, [X12]

    (346) 0x4263f0 LDR	D1, [X10]

    (346) 0x4263f4 FMSUB	D0, D1, D0, D2

    (346) 0x4263f8 STR	D0, [X11]

    (346) 0x4263fc LDR	D0, [X12, #8]

    (346) 0x426400 LDR	D1, [X10, #8]

    (346) 0x426404 ADD	X10, X10, #32

    (346) 0x426408 ADD	X12, X12, #32

    (346) 0x42640c FMSUB	D0, D1, D0, D3

    (346) 0x426410 STR	D0, [X11, #8]

    (346) 0x426414 ADD	X11, X11, #32

    (346) 0x426418 B.NE	4263c0

  (335) 0x42641c B	4258e8

  (335) 0x426420 ADD	X0, X12, X13

  (335) 0x426424 ADD	X2, X10, X15

  (335) 0x426428 ADD	X1, X24, X17

  (335) 0x42642c ORR	X18, XZR, XZR

  (335) 0x426430 ADD	X0, X0, X17

  (335) 0x426434 ADD	X17, X2, X17

  (335) 0x426438 ORR	X2, XZR, X19

  (335) 0x42643c CMP	X16, X17

  (335) 0x426440 CCMP	X11, X0, #2, #3

  (335) 0x426444 CSINC	W17, WZR, WZR, #2

  (335) 0x426448 CMP	X24, X0

  (335) 0x42644c CCMP	X16, X1, #2, #3

  (335) 0x426450 B.CC	426344

  (335) 0x426454 TBNZ	W17, #0, 426344

  (335) 0x426458 LDUR	X0, [X29, #464]

  (335) 0x42645c ORR	X17, XZR, XZR

  (335) 0x426460 AND	X18, X0, X4

  (335) 0x426464 AND	X0, X0, X4

    (348) 0x426468 ADD	X1, X24, X17

    (348) 0x42646c LD1B	{Z0.B}, P2/Z, [X24, X17]

    (348) 0x426470 LD1B	{Z2.B}, P2/Z, [X11, X17]

    (348) 0x426474 SUBS	X0, X0, X23

    (348) 0x426478 LD1B	{Z4.B}, P2/Z, [X16, X17]

    (348) 0x42647c FMSB	Z0.D, P1/M, Z2.D, Z4.D

    (348) 0x426480 LDR	Z1, [X1, #1, MUL VL]

    (348) 0x426484 ADD	X1, X11, X17

    (348) 0x426488 LDR	Z3, [X1, #1, MUL VL]

    (348) 0x42648c ADD	X1, X16, X17

    (348) 0x426490 LDR	Z5, [X1, #1, MUL VL]

    (348) 0x426494 FMSB	Z1.D, P1/M, Z3.D, Z5.D

    (348) 0x426498 ST1B	{Z0.B}, P2, [X16, X17]

    (348) 0x42649c ADD	X17, X17, X26

    (348) 0x4264a0 STR	Z1, [X1, #1, MUL VL]

    (348) 0x4264a4 B.NE	426468

  (335) 0x4264a8 CMP	X18, X4

  (335) 0x4264ac B.EQ	4258e8

  (335) 0x4264b0 B	426344

0x4264b4 LDR	D8, [SP, #112]

0x4264b8 LDP	X20, X19, [SP, #208]

0x4264bc LDP	X22, X21, [SP, #192]

0x4264c0 LDP	X24, X23, [SP, #176]

0x4264c4 LDP	X26, X25, [SP, #160]

0x4264c8 LDP	X28, X27, [SP, #144]

0x4264cc LDP	X29, X30, [SP, #128]

0x4264d0 ADD	SP, SP, #224

0x4264d4 RET

0x4264d8 HINT	#0

0x4264dc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.28+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.72+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	stl_vector.h:1131	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:172	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run orig_0

Source file and lines	TwoBodyJastrowRef.h:268-402
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229,249
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:244,263,271-273
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:268-274,359-367,375-391,397-402
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/shared_ptr_base.h:1667
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h:1131,1150,1263
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_numeric.h:140-141
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_algobase.h:952,1146
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_iterator.h:1068

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.17 to 2.00 cycles (3.08x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 39% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 6.17 to 3.40 cycles (1.81x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

qmcplusplus::ParticleSet::getDistTableAA(int) const: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:360

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	54
nb uops	39
loop length	216
used w registers	1
used x registers	18
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	2
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.88 cycles
front end	4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.75	3.75	4.00	3.50	1.50	1.50	0.50	0.50	6.17	5.83	6.00	4.00	4.00
cycles	2.00	2.00	3.75	3.75	4.00	3.50	1.50	1.50	0.50	0.50	6.17	5.83	6.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.88
Dispatch	6.17
Overall L1	6.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	42%
load	37%
store	47%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	43%

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

INT+FP

all	39%
load	37%
store	47%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	34%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.17 cycles. At this rate:

0% of peak load performance is reached (0.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 425800

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D8, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STP X29, X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W1, [X0, #584]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 452b70 <_ZNK11qmcplusplus11ParticleSet14getDistTableAAEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [X20, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBZ X21, 4264b4 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE+0xcb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTW X23, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FDUP Z17.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
FMOV D8, #-2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FDUP Z18.D, #128	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X30, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
RDVL X26, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STP X19, X0, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X21, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
PTRUE P2.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
B 425898 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE+0x98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR D8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X20, X19, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run orig_0

Source file and lines	TwoBodyJastrowRef.h:268-402
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229,249
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:244,263,271-273
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:268-274,359-367,375-391,397-402
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/shared_ptr_base.h:1667
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h:1131,1150,1263
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_numeric.h:140-141
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_algobase.h:952,1146
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_iterator.h:1068

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.17 to 2.00 cycles (3.08x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

qmcplusplus::ParticleSet::getDistTableAA(int) const: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:360

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	54
nb uops	39
loop length	216
used w registers	1
used x registers	18
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	2
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.88 cycles
front end	4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.75	3.75	4.00	3.50	1.50	1.50	0.50	0.50	6.17	5.83	6.00	4.00	4.00
cycles	2.00	2.00	3.75	3.75	4.00	3.50	1.50	1.50	0.50	0.50	6.17	5.83	6.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.88
Dispatch	6.17
Overall L1	6.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	42%
load	37%
store	47%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	43%

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

INT+FP

all	39%
load	37%
store	47%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	34%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.17 cycles. At this rate:

0% of peak load performance is reached (0.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 425800

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D8, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STP X29, X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W1, [X0, #584]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 452b70 <_ZNK11qmcplusplus11ParticleSet14getDistTableAAEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [X20, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBZ X21, 4264b4 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE+0xcb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTW X23, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FDUP Z17.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
FMOV D8, #-2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FDUP Z18.D, #128	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X30, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
RDVL X26, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STP X19, X0, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X21, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
PTRUE P2.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
B 425898 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE+0x98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR D8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X20, X19, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::TwoBodyJastrowRef >::recompute(qmcplusplus::ParticleSet&)–	0.07	0.10
▼Loop 333 - TwoBodyJastrowRef.h:268-398 - exec–	0.00	0.00
▼Loop 335 - TwoBodyJastrowRef.h:268-398 - exec–	0.00	0.00
○Loop 334 - TwoBodyJastrowRef.h:388-391 - exec	0.01	0.02
○Loop 351 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.02
○Loop 354 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.02
○Loop 348 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.02
○Loop 350 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
○Loop 347 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
○Loop 346 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
○Loop 352 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
○Loop 349 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
▼Loop 332 - TwoBodyJastrowRef.h:268-388 - exec–	0.00	0.00
○Loop 339 - TwoBodyJastrowRef.h:381-382 - exec	0.01	0.03
○Loop 337 - TwoBodyJastrowRef.h:381-382 - exec	0.01	0.02
○Loop 338 - TwoBodyJastrowRef.h:381-382 - exec	0.01	0.02
○Loop 336 - TwoBodyJastrowRef.h:375-376 - exec	0.00	0.02
○Loop 340 - TwoBodyJastrowRef.h:381-382 - exec	0.00	0.00
○Loop 343 - TwoBodyJastrowRef.h:375-376 - exec	0.00	0.00
○Loop 344 - stl_numeric.h:140-141 - exec	0.00	0.00
○Loop 331 - stl_numeric.h:140-141 - exec	0.00	0.00
○Loop 342 - TwoBodyJastrowRef.h:381-382 - exec	0.00	0.00
○Loop 341 - TwoBodyJastrowRef.h:381-382 - exec	0.00	0.00
○Loop 345 - TwoBodyJastrowRef.h:269-274 - exec	0.00	0.00
○Loop 330 - TwoBodyJastrowRef.h:361-364 - exec	0.00	0.00
○Loop 353 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
○Loop 329 - TwoBodyJastrowRef.h:388-391 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code