OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib<qmcplusplus::TinyVector<double, 3u>, std::allocator<qmcplusplus::TinyVector<double, 3u> > >&, qmcplusplus::ParticleAttrib<double, std::allocator<double> >&)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evalua ...	Module: exec	Source: DiracDeterminantRef.cpp:235-255 [...]	Coverage (incl. loops): 0.08% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 63 - 94

--------------------------------------------------------------------------------

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 223

--------------------------------------------------------------------------------

223:     return X[i];

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 82 - 155

--------------------------------------------------------------------------------

82:   for (int i = 0; i < n; i++)

83:     res += a[i] * b[i];

[...]

155:   for (int i = 0; i < n; i++)

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 235 - 255

--------------------------------------------------------------------------------

235: {

236:   recompute(P);

237:

238:   if (NumPtcls == 1)

239:   {

240:     ValueType y = psiM(0, 0);

241:     GradType rv = y * dpsiM(0, 0);

242:     G[FirstIndex] += rv;

243:     L[FirstIndex] += y * d2psiM(0, 0) - dot(rv, rv);

244:   }

245:   else

246:   {

247:     for (int i = 0, iat = FirstIndex; i < NumPtcls; i++, iat++)

248:     {

249:       mGradType rv   = simd::dot(psiM[i], dpsiM[i], NumOrbitals);

250:       mValueType lap = simd::dot(psiM[i], d2psiM[i], NumOrbitals);

251:       G[iat] += rv;

252:       L[iat] += lap - dot(rv, rv);

253:     }

254:   }

255:   return LogValue;

0x443ba0 STP	X29, X30, [SP, #976]!

0x443ba4 STP	X22, X21, [SP, #16]

0x443ba8 STP	X20, X19, [SP, #32]

0x443bac ADD	X29, SP, #0

0x443bb0 ORR	X20, XZR, X3

0x443bb4 ORR	X21, XZR, X2

0x443bb8 ORR	X19, XZR, X0

0x443bbc BL	445260

0x443bc0 LDR	W8, [X19, #1156]

0x443bc4 CMP	W8, #1

0x443bc8 B.NE	443c3c

0x443bcc LDR	X8, [X19, #256]

0x443bd0 LDRSW	X9, [X19, #1144]

0x443bd4 LDR	X10, [X21, #24]

0x443bd8 MOVZ	W11, #24

0x443bdc SMADDL	X10, W9, W11, X10

0x443be0 LDR	D0, [X8]

0x443be4 LDR	X8, [X19, #320]

0x443be8 LDR	Q3, [X10]

0x443bec LDR	Q2, [X8]

0x443bf0 LDR	D1, [X8, #16]

0x443bf4 LDR	X8, [X19, #384]

0x443bf8 FMUL	V2.2D, V2.2D, V0.D[0]

0x443bfc FMUL	D1, D1, D0

0x443c00 FADD	V3.2D, V3.2D, V2.2D

0x443c04 FMUL	V2.2D, V2.2D, V2.2D

0x443c08 FADDP	D2, V2.2D

0x443c0c STR	Q3, [X10]

0x443c10 LDR	D3, [X10, #16]

0x443c14 FADD	D3, D3, D1

0x443c18 FMADD	D1, D1, D1, D2

0x443c1c STR	D3, [X10, #16]

0x443c20 LDR	D3, [X8]

0x443c24 LDR	X8, [X20, #24]

0x443c28 LDR	D4, [X8, X9,LSL #3]

0x443c2c FNMSUB	D0, D3, D0, D1

0x443c30 FADD	D0, D0, D4

0x443c34 STR	D0, [X8, X9,LSL #3]

0x443c38 B	443e7c

0x443c3c CMP	W8, #1

0x443c40 B.LT	443e7c

0x443c44 LDR	W9, [X19, #1152]

0x443c48 CMP	W9, #1

0x443c4c B.LT	443e7c

0x443c50 LDR	X1, [X19, #280]

0x443c54 LDR	X11, [X19, #256]

0x443c58 LDR	X3, [X19, #216]

0x443c5c CNTW	X16, ALL

0x443c60 PTRUE	P0.B, ALL

0x443c64 LDR	X4, [X19, #344]

0x443c68 LDR	X12, [X19, #320]

0x443c6c LDR	X13, [X19, #384]

0x443c70 LDR	X14, [X21, #24]

0x443c74 PTRUE	P1.D, ALL

0x443c78 LDR	X15, [X20, #24]

0x443c7c LDRSW	X18, [X19, #1144]

0x443c80 AND	X17, X9, #0x0

0x443c84 MOVZ	W5, #24

0x443c88 ORR	X10, XZR, XZR

0x443c8c SUB	X0, XZR, X16

0x443c90 AND	X0, X0, X9

0x443c94 RDVL	X6, #2

0x443c98 ADD	X1, X1, X1,LSL #1

0x443c9c ADD	X2, X11, #16

0x443ca0 UBFM	X3, X3, #61, #60

0x443ca4 UBFM	X4, X4, #61, #60

0x443ca8 UBFM	X1, X1, #61, #60

0x443cac B	443d1c

0x443cb0 HINT	#0

0x443cb4 HINT	#0

0x443cb8 HINT	#0

0x443cbc HINT	#0

  (908) 0x443cc0 MADD	X7, X18, X5, X14

  (908) 0x443cc4 FMUL	D4, D2, D2

  (908) 0x443cc8 ADD	X10, X10, #1

  (908) 0x443ccc ADD	X12, X12, X1

  (908) 0x443cd0 ADD	X2, X2, X3

  (908) 0x443cd4 ADD	X11, X11, X3

  (908) 0x443cd8 FMADD	D4, D1, D1, D4

  (908) 0x443cdc ADD	X13, X13, X4

  (908) 0x443ce0 CMP	X10, X8

  (908) 0x443ce4 LDP	D5, D6, [X7]

  (908) 0x443ce8 FADD	D1, D6, D1

  (908) 0x443cec LDR	D6, [X7, #16]

  (908) 0x443cf0 FADD	D2, D6, D2

  (908) 0x443cf4 FADD	D5, D5, D0

  (908) 0x443cf8 FMADD	D0, D0, D0, D4

  (908) 0x443cfc FSUB	D0, D3, S0

  (908) 0x443d00 STP	D5, D1, [X7]

  (908) 0x443d04 STR	D2, [X7, #16]

  (908) 0x443d08 LDR	D1, [X15, X18,LSL #3]

  (908) 0x443d0c FADD	D0, D0, D1

  (908) 0x443d10 STR	D0, [X15, X18,LSL #3]

  (908) 0x443d14 ADD	X18, X18, #1

  (908) 0x443d18 B.EQ	443e7c

  (908) 0x443d1c CMP	W9, #4

  (908) 0x443d20 B.CS	443d40

  (908) 0x443d24 ORR	X21, XZR, XZR

  (908) 0x443d28 MOVI	D0, #0

  (908) 0x443d2c MOVI	D1, #0

  (908) 0x443d30 MOVI	D2, #0

  (908) 0x443d34 B	443dc0

0x443d38 HINT	#0

0x443d3c HINT	#0

(906) 0x443d40 MOVI	V0.2D, #0

(906) 0x443d44 MOVI	V3.2D, #0

(906) 0x443d48 MOVI	V1.2D, #0

(906) 0x443d4c MOVI	V4.2D, #0

(906) 0x443d50 AND	X20, X9, #0x0

(906) 0x443d54 ORR	X7, XZR, X2

(906) 0x443d58 ORR	X21, XZR, X12

(906) 0x443d5c MOVI	V2.2D, #0

(906) 0x443d60 MOVI	V5.2D, #0

  (904) 0x443d64 LDP	Q6, Q7, [X7, #2032]

  (904) 0x443d68 ORR	X22, XZR, X21

  (904) 0x443d6c ADD	X21, X21, #96

  (904) 0x443d70 SUBS	X20, X20, #4

  (904) 0x443d74 ADD	X7, X7, #32

  (904) 0x443d78 LD3	{V16.2D, V17.2D, V18.2D}, [X22], #80

  (904) 0x443d7c FMLA	V0.2D, V16.2D, V6.2D

  (904) 0x443d80 LD3	{V19.2D, V20.2D, V21.2D}, [X22]

  (904) 0x443d84 FMLA	V1.2D, V17.2D, V6.2D

  (904) 0x443d88 FMLA	V2.2D, V18.2D, V6.2D

  (904) 0x443d8c FMLA	V3.2D, V19.2D, V7.2D

  (904) 0x443d90 FMLA	V4.2D, V20.2D, V7.2D

  (904) 0x443d94 FMLA	V5.2D, V21.2D, V7.2D

  (904) 0x443d98 B.NE	443d64

(906) 0x443d9c FADD	V0.2D, V3.2D, V0.2D

(906) 0x443da0 FADD	V1.2D, V4.2D, V1.2D

(906) 0x443da4 FADD	V2.2D, V5.2D, V2.2D

(906) 0x443da8 CMP	X17, X9

(906) 0x443dac AND	X21, X9, #0x0

(906) 0x443db0 FADDP	D0, V0.2D

(906) 0x443db4 FADDP	D1, V1.2D

(906) 0x443db8 FADDP	D2, V2.2D

(906) 0x443dbc B.EQ	443df0

  (908) 0x443dc0 SUB	X7, X9, X21

  (908) 0x443dc4 ADD	X20, X11, X21,LSL #3

  (908) 0x443dc8 UMADDL	X21, W21, W5, X12

    (907) 0x443dcc LDR	D3, [X20], #8

    (907) 0x443dd0 LDP	D4, D5, [X21]

    (907) 0x443dd4 LDR	D6, [X21, #16]

    (907) 0x443dd8 SUBS	X7, X7, #1

    (907) 0x443ddc ADD	X21, X21, #24

    (907) 0x443de0 FMADD	D0, D4, D3, D0

    (907) 0x443de4 FMADD	D1, D5, D3, D1

    (907) 0x443de8 FMADD	D2, D6, D3, D2

    (907) 0x443dec B.NE	443dcc

  (908) 0x443df0 CMP	X16, X9

  (908) 0x443df4 B.LS	443e04

  (908) 0x443df8 ORR	X7, XZR, XZR

  (908) 0x443dfc MOVI	D3, #0

  (908) 0x443e00 B	443e60

  (908) 0x443e04 MOVI	V3.2D, #0

  (908) 0x443e08 MOVI	V4.2D, #0

  (908) 0x443e0c ORR	X7, XZR, XZR

  (908) 0x443e10 ORR	X20, XZR, X0

  (908) 0x443e14 HINT	#0

  (908) 0x443e18 HINT	#0

  (908) 0x443e1c HINT	#0

    (905) 0x443e20 ADD	X21, X11, X7

    (905) 0x443e24 LD1B	{Z5.B}, P0/Z, [X11, X7]

    (905) 0x443e28 LD1B	{Z7.B}, P0/Z, [X13, X7]

    (905) 0x443e2c SUBS	X20, X20, X16

    (905) 0x443e30 FMLA	Z3.D, P1/M, Z7.D, Z5.D

    (905) 0x443e34 LDR	Z6, [X21, #1, MUL VL]

    (905) 0x443e38 ADD	X21, X13, X7

    (905) 0x443e3c LDR	Z16, [X21, #1, MUL VL]

    (905) 0x443e40 ADD	X7, X7, X6

    (905) 0x443e44 FMLA	Z4.D, P1/M, Z16.D, Z6.D

    (905) 0x443e48 B.NE	443e20

  (908) 0x443e4c FADD	Z3.D, Z4.D, Z3.D

  (908) 0x443e50 CMP	X0, X9

  (908) 0x443e54 ORR	X7, XZR, X0

  (908) 0x443e58 FADDV	D3, P1, Z3.D

  (908) 0x443e5c B.EQ	443cc0

    (909) 0x443e60 LDR	D4, [X11, X7,LSL #3]

    (909) 0x443e64 LDR	D5, [X13, X7,LSL #3]

    (909) 0x443e68 ADD	X7, X7, #1

    (909) 0x443e6c CMP	X9, X7

    (909) 0x443e70 FMADD	D3, D5, D4, D3

    (909) 0x443e74 B.NE	443e60

  (908) 0x443e78 B	443cc0

0x443e7c LDR	D0, [X19, #16]

0x443e80 LDP	X20, X19, [SP, #32]

0x443e84 LDP	X22, X21, [SP, #16]

0x443e88 LDP	X29, X30, [SP], #48

0x443e8c RET

0x443e90 HINT	#0

0x443e94 HINT	#0

0x443e98 HINT	#0

0x443e9c HINT	#0

Coverage (%)	Name	Source Location	Module
►59.78+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►39.20+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	DiracDeterminantRef.cpp:235-255
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:235-255

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.33 to 4.17 cycles (2.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 32% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 11.33 to 6.12 cycles (1.85x speedup).

Details

12% of VPU instructions are used in vector version (process two or more data elements in vector registers):

11% of VPU loads are used in vector version.
16% of VPU stores are used in vector version.
14% of VPU addition or subtraction instructions are used in vector version.
66% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

miniqmcreference::DiracDeterminantRef
>::recompute(qmcplusplus::ParticleSet&): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:236

Matching between your function (in the source code) and the binary function

The binary function is composed of 14 FP arithmetical operations:

7: addition or subtraction (2 inside FMA instructions)
7: multiply (2 inside FMA instructions)

The binary function is loading 12 bytes.

Arithmetic intensity

Arithmetic intensity is 1.17 FP operations per loaded or stored byte.

General properties

nb instructions	83
nb uops	73
loop length	332
used w registers	4
used x registers	24
used b registers	0
used h registers	0
used s registers	1
used d registers	5
used q registers	2
used v registers	3
used z registers	0
nb stack references	6
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.13 cycles
front end	9.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	6.25	6.25	6.25	6.25	3.00	3.00	3.00	3.00	11.33	11.33	11.33	1.50	1.50
cycles	3.50	3.50	6.25	6.25	6.25	6.25	3.00	3.00	3.00	3.00	11.33	11.33	11.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.13
Dispatch	11.33
Overall L1	11.33

Vectorization ratios

INT

all	7%
load	11%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	25%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	11%
store	16%
mul	66%
add-sub	14%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	31%
load	28%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	32%

all	36%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	41%
add-sub	37%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	32%
load	28%
store	41%
mul	41%
add-sub	32%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.33 cycles. At this rate:

1% of peak load performance is reached (1.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 443ba0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 445260 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9recomputeERNS1_11ParticleSetE>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [X19, #1156]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 443c3c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDRSW X9, [X19, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W11, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SMADDL X10, W9, W11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X8, [X19, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR Q3, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR D1, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X8, [X19, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL V2.2D, V2.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL D1, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD V3.2D, V3.2D, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V2.2D, V2.2D, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FADDP D2, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR Q3, [X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR D3, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D3, D3, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMADD D1, D1, D1, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D3, [X10, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D3, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X8, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FNMSUB D0, D3, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FADD D0, D0, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 443e7c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 443e7c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W9, [X19, #1152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 443e7c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X19, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X19, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTW X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X4, [X19, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [X19, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X19, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X15, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDRSW X18, [X19, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
AND X17, X9, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W5, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X0, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X0, X0, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
RDVL X6, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X1, X1, X1,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X3, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X4, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X1, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 443d1c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x17c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR D0, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	DiracDeterminantRef.cpp:235-255
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:235-255

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.33 to 4.17 cycles (2.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

12% of VPU instructions are used in vector version (process two or more data elements in vector registers):

11% of VPU loads are used in vector version.
16% of VPU stores are used in vector version.
14% of VPU addition or subtraction instructions are used in vector version.
66% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

miniqmcreference::DiracDeterminantRef
>::recompute(qmcplusplus::ParticleSet&): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:236

Matching between your function (in the source code) and the binary function

The binary function is composed of 14 FP arithmetical operations:

7: addition or subtraction (2 inside FMA instructions)
7: multiply (2 inside FMA instructions)

The binary function is loading 12 bytes.

Arithmetic intensity

Arithmetic intensity is 1.17 FP operations per loaded or stored byte.

General properties

nb instructions	83
nb uops	73
loop length	332
used w registers	4
used x registers	24
used b registers	0
used h registers	0
used s registers	1
used d registers	5
used q registers	2
used v registers	3
used z registers	0
nb stack references	6
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.13 cycles
front end	9.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	6.25	6.25	6.25	6.25	3.00	3.00	3.00	3.00	11.33	11.33	11.33	1.50	1.50
cycles	3.50	3.50	6.25	6.25	6.25	6.25	3.00	3.00	3.00	3.00	11.33	11.33	11.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.13
Dispatch	11.33
Overall L1	11.33

Vectorization ratios

INT

all	7%
load	11%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	25%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	11%
store	16%
mul	66%
add-sub	14%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	31%
load	28%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	32%

all	36%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	41%
add-sub	37%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	32%
load	28%
store	41%
mul	41%
add-sub	32%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.33 cycles. At this rate:

1% of peak load performance is reached (1.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 443ba0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 445260 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9recomputeERNS1_11ParticleSetE>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [X19, #1156]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 443c3c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDRSW X9, [X19, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W11, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SMADDL X10, W9, W11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X8, [X19, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR Q3, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR D1, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X8, [X19, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL V2.2D, V2.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL D1, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD V3.2D, V3.2D, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V2.2D, V2.2D, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FADDP D2, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR Q3, [X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR D3, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D3, D3, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMADD D1, D1, D1, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D3, [X10, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D3, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X8, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FNMSUB D0, D3, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FADD D0, D0, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 443e7c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 443e7c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W9, [X19, #1152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 443e7c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X19, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X19, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTW X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X4, [X19, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [X19, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X19, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X15, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDRSW X18, [X19, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
AND X17, X9, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W5, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X0, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X0, X0, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
RDVL X6, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X1, X1, X1,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X3, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X4, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X1, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 443d1c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x17c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR D0, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus...–	0.08	0.12
▼Loop 906 - inner_product.hpp:82-155 - exec–	0.00	0.00
○Loop 904 - inner_product.hpp:155-155 - exec	0.06	0.09
▼Loop 908 - inner_product.hpp:82-155 - exec–	0.00	0.00
○Loop 905 - inner_product.hpp:82-83 - exec	0.02	0.03
○Loop 907 - inner_product.hpp:155-155 - exec	0.00	0.00
○Loop 909 - inner_product.hpp:82-83 - exec	0.00	0.00

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