OV - exec - Loop 2055

	Loop Id: 2055	Module: exec	Source: ParticleBConds3DSoa.h:280-298	Coverage: 4.14%

0x4a7424 LD1D	{Z7.D}, P1/Z, [X0, X18,LSL #3]    [7]

0x4a7428 SUB	X11, X29, #64

0x4a742c LD1D	{Z16.D}, P1/Z, [X9, X18,LSL #3]    [2]

0x4a7430 FSUB	Z7.D, Z7.D, Z6.D

0x4a7434 LDR	Z18, [X11, #510, MUL VL]    [1]

0x4a7438 LDR	Z19, [X11, #508, MUL VL]    [1]

0x4a743c FSUB	Z16.D, Z16.D, Z5.D

0x4a7440 LD1D	{Z17.D}, P1/Z, [X2, X18,LSL #3]    [8]

0x4a7444 FSUB	Z17.D, Z17.D, Z4.D

0x4a7448 LDR	Z30, [X11, #501, MUL VL]    [1]

0x4a744c FMUL	Z18.D, Z18.D, Z7.D

0x4a7450 FMLA	Z18.D, P0/M, Z19.D, Z16.D

0x4a7454 LDR	Z19, [X11, #503, MUL VL]    [1]

0x4a7458 FMLA	Z18.D, P0/M, Z19.D, Z17.D

0x4a745c LDR	Z19, [X11, #502, MUL VL]    [1]

0x4a7460 FMUL	Z19.D, Z19.D, Z7.D

0x4a7464 FMLA	Z19.D, P0/M, Z30.D, Z16.D

0x4a7468 LDR	Z30, [X11, #500, MUL VL]    [1]

0x4a746c FMLA	Z19.D, P0/M, Z30.D, Z17.D

0x4a7470 LDR	Z30, [X11, #499, MUL VL]    [1]

0x4a7474 FMUL	Z7.D, Z30.D, Z7.D

0x4a7478 FMLA	Z7.D, P0/M, Z31.D, Z16.D

0x4a747c MOVPRFX	Z16, Z18

0x4a7480 FRINTA	Z16.D, P0/M, Z18.D

0x4a7484 FMLA	Z7.D, P0/M, Z8.D, Z17.D

0x4a7488 MOVPRFX	Z17, Z19

0x4a748c FRINTA	Z17.D, P0/M, Z19.D

0x4a7490 FSUB	Z16.D, Z18.D, Z16.D

0x4a7494 FSUB	Z17.D, Z19.D, Z17.D

0x4a7498 MOVPRFX	Z18, Z7

0x4a749c FRINTA	Z18.D, P0/M, Z7.D

0x4a74a0 FSUB	Z7.D, Z7.D, Z18.D

0x4a74a4 FMUL	Z18.D, Z9.D, Z16.D

0x4a74a8 FMLA	Z18.D, P0/M, Z10.D, Z17.D

0x4a74ac FMLA	Z18.D, P0/M, Z7.D, Z11.D

0x4a74b0 ST1D	{Z18.D}, P1, [X12, X18,LSL #3]    [5]

0x4a74b4 FMUL	Z18.D, Z14.D, Z16.D

0x4a74b8 FMUL	Z16.D, Z1.D, Z16.D

0x4a74bc FMLA	Z16.D, P0/M, Z2.D, Z17.D

0x4a74c0 FMLA	Z18.D, P0/M, Z15.D, Z17.D

0x4a74c4 FMLA	Z18.D, P0/M, Z0.D, Z7.D

0x4a74c8 FMAD	Z7.D, P0/M, Z3.D, Z16.D

0x4a74cc LD1D	{Z16.D}, P1/Z, [X12, X18,LSL #3]    [5]

0x4a74d0 ST1D	{Z18.D}, P1, [X21, X18,LSL #3]    [4]

0x4a74d4 LD1D	{Z17.D}, P1/Z, [X21, X18,LSL #3]    [4]

0x4a74d8 ST1D	{Z7.D}, P1, [X13, X18,LSL #3]    [6]

0x4a74dc FMUL	Z16.D, Z16.D, Z16.D

0x4a74e0 FMAD	Z7.D, P0/M, Z7.D, Z16.D

0x4a74e4 FMLA	Z7.D, P0/M, Z17.D, Z17.D

0x4a74e8 FSQRT	Z7.D, P0/M, Z7.D

0x4a74ec ST1D	{Z7.D}, P1, [X20, X18,LSL #3]    [3]

0x4a74f0 ADD	X18, X18, X10

0x4a74f4 WHILELO	P1.D, X18, X8

0x4a74f8 B.MI	4a7424

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 280 - 298

--------------------------------------------------------------------------------

280:     T displ_0 = px[iat] - x0;

281:     T displ_1 = py[iat] - y0;

282:     T displ_2 = pz[iat] - z0;

283:

284:     T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

285:     T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

286:     T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

287:

288:     //put them in the box

289:     ar_0 -= round(ar_0);

290:     ar_1 -= round(ar_1);

291:     ar_2 -= round(ar_2);

292:

293:     //unit2cart

294:     dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

295:     dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

296:     dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

297:

298:     temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

Coverage (%)	Name	Source Location	Module
►98.09+	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:993	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.omp_outlined.62	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.56+	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:993	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.omp_outlined.62	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:409	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:172	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source	ParticleBConds3DSoa.h:280-298
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	17.00
Front-end cycles	6.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	1.00
P5 cycles	0.50
P6 cycles	17.00
P7 cycles	17.00
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	6.99 - 14.08
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	54.00
Nb uops	54.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	9.88
Nb FLOP add-sub	24.00
Nb FLOP mul	28.00
Nb FLOP fma	56.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.12
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	94.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source	ParticleBConds3DSoa.h:280-298
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	17.00
Front-end cycles	6.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	1.00
P5 cycles	0.50
P6 cycles	17.00
P7 cycles	17.00
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	6.99 - 14.08
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	54.00
Nb uops	54.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	9.88
Nb FLOP add-sub	24.00
Nb FLOP mul	28.00
Nb FLOP fma	56.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.12
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	94.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source file and lines	ParticleBConds3DSoa.h:280-298
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 56 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 168 FP arithmetical operations:

80: addition or subtraction (56 inside FMA instructions)
84: multiply (56 inside FMA instructions)
4: square root

The binary loop is loading 384 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.33 FP operations per loaded or stored byte.

General properties

nb instructions	54
nb uops	54
loop length	216
used w registers	0
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	20
nb stack references	0
ADD-SUB / MUL ratio	0.86

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.75 cycles
front end	6.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	1.00	0.50	17.00	17.00	2.00	2.00	8.00	8.00	0.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	1.00	0.50	17.00	17.00	13.50	13.50	8.00	8.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.75
Dispatch	17.00
DIV/SQRT	6.99-14.08
Data deps.	1.00
Overall L1	17.00

Vectorization ratios

INT

all	84%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

Vector efficiency ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

23% of peak load performance is reached (22.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4a7424

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z7.D}, P1/Z, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUB X11, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z16.D}, P1/Z, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z7.D, Z7.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LDR Z18, [X11, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z19, [X11, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z16.D, Z16.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z17.D}, P1/Z, [X2, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z17.D, Z17.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LDR Z30, [X11, #501, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z18.D, Z18.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z18.D, P0/M, Z19.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z19, [X11, #503, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z18.D, P0/M, Z19.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z19, [X11, #502, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z19.D, Z19.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z19.D, P0/M, Z30.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z30, [X11, #500, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z19.D, P0/M, Z30.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z30, [X11, #499, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z7.D, Z30.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z7.D, P0/M, Z31.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z16, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FRINTA Z16.D, P0/M, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FMLA Z7.D, P0/M, Z8.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z17, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FRINTA Z17.D, P0/M, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FSUB Z16.D, Z18.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z17.D, Z19.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z18, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FRINTA Z18.D, P0/M, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FSUB Z7.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z18.D, Z9.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z18.D, P0/M, Z10.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z18.D, P0/M, Z7.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z18.D}, P1, [X12, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FMUL Z18.D, Z14.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z16.D, Z1.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z16.D, P0/M, Z2.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z18.D, P0/M, Z15.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z18.D, P0/M, Z0.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z7.D, P0/M, Z3.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z16.D}, P1/Z, [X12, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ST1D {Z18.D}, P1, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z17.D}, P1/Z, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ST1D {Z7.D}, P1, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FMUL Z16.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z7.D, P0/M, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z7.D, P0/M, Z17.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FSQRT Z7.D, P0/M, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
ST1D {Z7.D}, P1, [X20, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X18, X18, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P1.D, X18, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 4a7424 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x664>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source file and lines	ParticleBConds3DSoa.h:280-298
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 56 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 168 FP arithmetical operations:

80: addition or subtraction (56 inside FMA instructions)
84: multiply (56 inside FMA instructions)
4: square root

The binary loop is loading 384 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.33 FP operations per loaded or stored byte.

General properties

nb instructions	54
nb uops	54
loop length	216
used w registers	0
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	20
nb stack references	0
ADD-SUB / MUL ratio	0.86

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.75 cycles
front end	6.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	1.00	0.50	17.00	17.00	2.00	2.00	8.00	8.00	0.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	1.00	0.50	17.00	17.00	13.50	13.50	8.00	8.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.75
Dispatch	17.00
DIV/SQRT	6.99-14.08
Data deps.	1.00
Overall L1	17.00

Vectorization ratios

INT

all	84%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

Vector efficiency ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

23% of peak load performance is reached (22.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4a7424

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z7.D}, P1/Z, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUB X11, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z16.D}, P1/Z, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z7.D, Z7.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LDR Z18, [X11, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z19, [X11, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z16.D, Z16.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z17.D}, P1/Z, [X2, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z17.D, Z17.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LDR Z30, [X11, #501, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z18.D, Z18.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z18.D, P0/M, Z19.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z19, [X11, #503, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z18.D, P0/M, Z19.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z19, [X11, #502, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z19.D, Z19.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z19.D, P0/M, Z30.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z30, [X11, #500, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z19.D, P0/M, Z30.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z30, [X11, #499, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z7.D, Z30.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z7.D, P0/M, Z31.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z16, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FRINTA Z16.D, P0/M, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FMLA Z7.D, P0/M, Z8.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z17, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FRINTA Z17.D, P0/M, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FSUB Z16.D, Z18.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z17.D, Z19.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z18, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FRINTA Z18.D, P0/M, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FSUB Z7.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z18.D, Z9.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z18.D, P0/M, Z10.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z18.D, P0/M, Z7.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z18.D}, P1, [X12, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FMUL Z18.D, Z14.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z16.D, Z1.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z16.D, P0/M, Z2.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z18.D, P0/M, Z15.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z18.D, P0/M, Z0.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z7.D, P0/M, Z3.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z16.D}, P1/Z, [X12, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ST1D {Z18.D}, P1, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z17.D}, P1/Z, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ST1D {Z7.D}, P1, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FMUL Z16.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z7.D, P0/M, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z7.D, P0/M, Z17.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FSQRT Z7.D, P0/M, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
ST1D {Z7.D}, P1, [X20, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X18, X18, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P1.D, X18, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 4a7424 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x664>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code