OV - exec - Loop 271

	Loop Id: 271	Module: exec	Source: BsplineFunctor.h:303-336 [...]	Coverage: 0.04%

0x422840 LD1D	{Z16.D}, P0/Z, [X9, X13,LSL #3]    [4]

0x422844 DUP	Z20.D, X14

0x422848 LDR	Z24, [SP, #14, MUL VL]    [5]

0x42284c LDR	Z27, [SP, #4, MUL VL]    [5]

0x422850 FMUL	Z18.D, Z16.D, Z6.D

0x422854 MOVPRFX	Z17, Z18

0x422858 FCVTZS	Z17.D, P1/M, Z18.D

0x42285c MOVPRFX	Z19, Z17

0x422860 SCVTF	Z19.D, P1/M, Z17.D

0x422864 ADR	Z20.D, [Z20, Z17.D,LSL #3]    [2]

0x422868 LD1D	{Z17.D}, P0/Z, [X14, Z17.D,LSL #3]    [9]

0x42286c LD1D	{Z21.D}, P0/Z, [V20, #1.D]    [1]

0x422870 LD1D	{Z22.D}, P0/Z, [V20, #2.D]    [1]

0x422874 LD1D	{Z20.D}, P0/Z, [V20, #3.D]    [1]

0x422878 FSUB	Z25.D, Z18.D, Z19.D

0x42287c LDR	Z18, [SP, #17, MUL VL]    [5]

0x422880 LDR	Z19, [SP, #16, MUL VL]    [5]

0x422884 FMUL	Z26.D, Z25.D, Z25.D

0x422888 FMUL	Z23.D, Z26.D, Z25.D

0x42288c FMAD	Z18.D, P1/M, Z25.D, Z19.D

0x422890 LDR	Z19, [SP, #15, MUL VL]    [5]

0x422894 FMUL	Z18.D, Z18.D, Z17.D

0x422898 FMLA	Z24.D, P1/M, Z19.D, Z25.D

0x42289c LDR	Z19, [SP, #9, MUL VL]    [5]

0x4228a0 FMLA	Z18.D, P1/M, Z24.D, Z21.D

0x4228a4 LDR	Z24, [SP, #7, MUL VL]    [5]

0x4228a8 FMLA	Z24.D, P1/M, Z19.D, Z26.D

0x4228ac LDR	Z19, [SP, #8, MUL VL]    [5]

0x4228b0 FMLA	Z24.D, P1/M, Z19.D, Z25.D

0x4228b4 LDR	Z19, [SP, #6, MUL VL]    [5]

0x4228b8 FMUL	Z24.D, Z24.D, Z17.D

0x4228bc FMAD	Z19.D, P1/M, Z26.D, Z27.D

0x4228c0 LDR	Z27, [SP, #5, MUL VL]    [5]

0x4228c4 FMLA	Z19.D, P1/M, Z27.D, Z25.D

0x4228c8 FMAD	Z19.D, P1/M, Z21.D, Z24.D

0x4228cc MOVPRFX	Z24, Z9

0x4228d0 FMLA	Z24.D, P1/M, Z30.D, Z23.D

0x4228d4 FMLA	Z24.D, P1/M, Z31.D, Z26.D

0x4228d8 FMLA	Z24.D, P1/M, Z8.D, Z25.D

0x4228dc FMUL	Z17.D, Z24.D, Z17.D

0x4228e0 MOVPRFX	Z24, Z13

0x4228e4 FMLA	Z24.D, P1/M, Z10.D, Z23.D

0x4228e8 FMLA	Z24.D, P1/M, Z11.D, Z26.D

0x4228ec FMLA	Z24.D, P1/M, Z12.D, Z25.D

0x4228f0 FMLA	Z17.D, P1/M, Z24.D, Z21.D

0x4228f4 LDR	Z21, [SP, #13, MUL VL]    [5]

0x4228f8 LDR	Z24, [SP, #12, MUL VL]    [5]

0x4228fc FMAD	Z21.D, P1/M, Z25.D, Z24.D

0x422900 LDR	Z24, [SP, #1, MUL VL]    [5]

0x422904 FMLA	Z18.D, P1/M, Z21.D, Z22.D

0x422908 LDR	Z21, [SP, #3, MUL VL]    [5]

0x42290c FMAD	Z21.D, P1/M, Z26.D, Z24.D

0x422910 LDR	Z24, [SP, #2, MUL VL]    [5]

0x422914 FMLA	Z21.D, P1/M, Z24.D, Z25.D

0x422918 FMLA	Z19.D, P1/M, Z21.D, Z22.D

0x42291c MOVPRFX	Z21, Z1

0x422920 FMLA	Z21.D, P1/M, Z14.D, Z23.D

0x422924 FMAD	Z23.D, P1/M, Z2.D, Z5.D

0x422928 FMLA	Z21.D, P1/M, Z15.D, Z26.D

0x42292c FMLA	Z23.D, P1/M, Z3.D, Z26.D

0x422930 FMLA	Z21.D, P1/M, Z0.D, Z25.D

0x422934 FMLA	Z23.D, P1/M, Z4.D, Z25.D

0x422938 FMLA	Z17.D, P1/M, Z21.D, Z22.D

0x42293c LDR	Z21, [SP, #11, MUL VL]    [5]

0x422940 LDR	Z22, [SP, #10, MUL VL]    [5]

0x422944 FMLA	Z17.D, P1/M, Z23.D, Z20.D

0x422948 FMAD	Z21.D, P1/M, Z25.D, Z22.D

0x42294c FMLA	Z18.D, P1/M, Z21.D, Z20.D

0x422950 LDR	Z21, [SP, MUL VL]    [5]

0x422954 FMUL	Z18.D, Z7.D, Z18.D

0x422958 FMAD	Z21.D, P1/M, Z26.D, Z29.D

0x42295c FMLA	Z21.D, P1/M, Z28.D, Z25.D

0x422960 FMLA	Z19.D, P1/M, Z21.D, Z20.D

0x422964 LD1SW	{Z20.D}, P0/Z, [X8, X13,LSL #2]    [3]

0x422968 ADD	X13, X13, X16

0x42296c ST1D	{Z18.D}, P0, [X12, Z20.D,LSL #3]    [8]

0x422970 FMUL	Z18.D, Z19.D, Z6.D

0x422974 FDIVR	Z16.D, P1/M, Z16.D, Z18.D

0x422978 ST1D	{Z16.D}, P0, [X11, Z20.D,LSL #3]    [7]

0x42297c ST1D	{Z17.D}, P0, [X10, Z20.D,LSL #3]    [6]

0x422980 WHILELO	P0.D, X13, X15

0x422984 B.MI	422840

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h: 1150 - 1150

--------------------------------------------------------------------------------

1150: 	return *(this->_M_impl._M_start + __n);

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 303 - 336

--------------------------------------------------------------------------------

303:   for (int j = 0; j < iCount; j++)

304:   {

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

Coverage (%)	Name	Source Location	Module
►58.78+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.62	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►31.93+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.62	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►3.69+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►3.31+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:260	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.62	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.15+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.62	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:409	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:172	exec
►1.02+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.62	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:409	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:172	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	P6, P7,
Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source	stl_vector.h:1150-1150,BsplineFunctor.h:303-336
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.50
CQA cycles if no scalar integer	25.50
CQA cycles if FP arith vectorized	25.50
CQA cycles if fully vectorized	25.13
Front-end cycles	10.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	2.00
P5 cycles	0.25
P6 cycles	25.50
P7 cycles	25.50
P8 cycles	21.00
P9 cycles	21.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	3.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	6.99 - 14.08
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	82.00
Nb uops	82.00
Nb loads	NA
Nb stores	3.00
Nb stack references	18.00
FLOP/cycle	11.92
Nb FLOP add-sub	4.00
Nb FLOP mul	32.00
Nb FLOP fma	132.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.89
Bytes prefetched	0.00
Bytes loaded	768.13
Bytes stored	96.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	5.00
Vectorization ratio all	91.14
Vectorization ratio load	96.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	25.00
Vector-efficiency ratio all	98.10
Vector-efficiency ratio load	97.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	90.63

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	P6, P7,
Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source	stl_vector.h:1150-1150,BsplineFunctor.h:303-336
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.50
CQA cycles if no scalar integer	25.50
CQA cycles if FP arith vectorized	25.50
CQA cycles if fully vectorized	25.13
Front-end cycles	10.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	2.00
P5 cycles	0.25
P6 cycles	25.50
P7 cycles	25.50
P8 cycles	21.00
P9 cycles	21.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	3.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	6.99 - 14.08
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	82.00
Nb uops	82.00
Nb loads	NA
Nb stores	3.00
Nb stack references	18.00
FLOP/cycle	11.92
Nb FLOP add-sub	4.00
Nb FLOP mul	32.00
Nb FLOP fma	132.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.89
Bytes prefetched	0.00
Bytes loaded	768.13
Bytes stored	96.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	5.00
Vectorization ratio all	91.14
Vectorization ratio load	96.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	25.00
Vector-efficiency ratio all	98.10
Vector-efficiency ratio load	97.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	90.63

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source file and lines	BsplineFunctor.h:303-336
Module	exec

The loop is defined in:

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h:1150
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303-336

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 25.50 to 25.12 cycles (1.01x speedup).

Details

91% of VPU instructions are used in vector version (process two or more data elements in vector registers):

96% of VPU loads are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
25% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 132 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)
Irregular (variable stride) or indirect: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
SCVTF: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:310

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 304 FP arithmetical operations:

136: addition or subtraction (132 inside FMA instructions)
164: multiply (132 inside FMA instructions)
4: divide

The binary loop is loading 768 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.35 FP operations per loaded or stored byte.

General properties

nb instructions	82
nb uops	82
loop length	328
used w registers	0
used x registers	9
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	1
used z registers	32
nb stack references	18
ADD-SUB / MUL ratio	0.13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.25 cycles
front end	10.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	2.00	0.25	25.50	25.50	3.00	3.00	12.00	12.00	3.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	2.00	0.25	25.50	25.50	21.00	21.00	12.00	12.00	3.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	10.25
Dispatch	25.50
DIV/SQRT	6.99-14.08
Data deps.	1.00
Overall L1	25.50

Vectorization ratios

INT

all	80%
load	96%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	91%
load	96%
store	100%
mul	100%
add-sub	50%
fma	100%
div/sqrt	100%
other	25%

Vector efficiency ratios

INT

all	95%
load	97%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	89%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	98%
load	97%
store	100%
mul	100%
add-sub	62%
fma	100%
div/sqrt	100%
other	90%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.50 cycles. At this rate:

31% of peak load performance is reached (30.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.76 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 422840

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LD1D {Z16.D}, P0/Z, [X9, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
DUP Z20.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDR Z24, [SP, #14, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z27, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z18.D, Z16.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z17, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FCVTZS Z17.D, P1/M, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
MOVPRFX Z19, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SCVTF Z19.D, P1/M, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
ADR Z20.D, [Z20, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z17.D}, P0/Z, [X14, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z21.D}, P0/Z, [V20, #1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z22.D}, P0/Z, [V20, #2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z20.D}, P0/Z, [V20, #3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z25.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z18, [SP, #17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z19, [SP, #16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z26.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z23.D, Z26.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z18.D, P1/M, Z25.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z19, [SP, #15, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z18.D, Z18.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z24.D, P1/M, Z19.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z19, [SP, #9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z18.D, P1/M, Z24.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z24, [SP, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z24.D, P1/M, Z19.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z19, [SP, #8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z24.D, P1/M, Z19.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z19, [SP, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z24.D, Z24.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z19.D, P1/M, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z27, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z19.D, P1/M, Z27.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z19.D, P1/M, Z21.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z24, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z24.D, P1/M, Z30.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z24.D, P1/M, Z31.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z24.D, P1/M, Z8.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z17.D, Z24.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z24, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z24.D, P1/M, Z10.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z24.D, P1/M, Z11.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z24.D, P1/M, Z12.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z17.D, P1/M, Z24.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z21, [SP, #13, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z24, [SP, #12, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMAD Z21.D, P1/M, Z25.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z24, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z18.D, P1/M, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z21, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMAD Z21.D, P1/M, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z24, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z21.D, P1/M, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z19.D, P1/M, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z21, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z21.D, P1/M, Z14.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z23.D, P1/M, Z2.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z21.D, P1/M, Z15.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z23.D, P1/M, Z3.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z21.D, P1/M, Z0.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z23.D, P1/M, Z4.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z17.D, P1/M, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z21, [SP, #11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z22, [SP, #10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z17.D, P1/M, Z23.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z21.D, P1/M, Z25.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z18.D, P1/M, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z21, [SP, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z18.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z21.D, P1/M, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z21.D, P1/M, Z28.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z19.D, P1/M, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1SW {Z20.D}, P0/Z, [X8, X13,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD X13, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ST1D {Z18.D}, P0, [X12, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
FMUL Z18.D, Z19.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z16.D, P1/M, Z16.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ST1D {Z16.D}, P0, [X11, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z17.D}, P0, [X10, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
WHILELO P0.D, X13, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 422840 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source file and lines	BsplineFunctor.h:303-336
Module	exec

The loop is defined in:

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h:1150
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303-336

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

91% of VPU instructions are used in vector version (process two or more data elements in vector registers):

96% of VPU loads are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
25% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 132 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)
Irregular (variable stride) or indirect: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
SCVTF: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:310

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 304 FP arithmetical operations:

136: addition or subtraction (132 inside FMA instructions)
164: multiply (132 inside FMA instructions)
4: divide

The binary loop is loading 768 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.35 FP operations per loaded or stored byte.

General properties

nb instructions	82
nb uops	82
loop length	328
used w registers	0
used x registers	9
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	1
used z registers	32
nb stack references	18
ADD-SUB / MUL ratio	0.13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.25 cycles
front end	10.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	2.00	0.25	25.50	25.50	3.00	3.00	12.00	12.00	3.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	2.00	0.25	25.50	25.50	21.00	21.00	12.00	12.00	3.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	10.25
Dispatch	25.50
DIV/SQRT	6.99-14.08
Data deps.	1.00
Overall L1	25.50

Vectorization ratios

INT

all	80%
load	96%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	91%
load	96%
store	100%
mul	100%
add-sub	50%
fma	100%
div/sqrt	100%
other	25%

Vector efficiency ratios

INT

all	95%
load	97%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	89%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	98%
load	97%
store	100%
mul	100%
add-sub	62%
fma	100%
div/sqrt	100%
other	90%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.50 cycles. At this rate:

31% of peak load performance is reached (30.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.76 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 422840

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LD1D {Z16.D}, P0/Z, [X9, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
DUP Z20.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDR Z24, [SP, #14, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z27, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z18.D, Z16.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z17, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FCVTZS Z17.D, P1/M, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
MOVPRFX Z19, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SCVTF Z19.D, P1/M, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
ADR Z20.D, [Z20, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z17.D}, P0/Z, [X14, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z21.D}, P0/Z, [V20, #1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z22.D}, P0/Z, [V20, #2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z20.D}, P0/Z, [V20, #3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z25.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z18, [SP, #17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z19, [SP, #16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z26.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z23.D, Z26.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z18.D, P1/M, Z25.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z19, [SP, #15, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z18.D, Z18.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z24.D, P1/M, Z19.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z19, [SP, #9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z18.D, P1/M, Z24.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z24, [SP, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z24.D, P1/M, Z19.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z19, [SP, #8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z24.D, P1/M, Z19.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z19, [SP, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z24.D, Z24.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z19.D, P1/M, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z27, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z19.D, P1/M, Z27.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z19.D, P1/M, Z21.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z24, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z24.D, P1/M, Z30.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z24.D, P1/M, Z31.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z24.D, P1/M, Z8.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z17.D, Z24.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z24, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z24.D, P1/M, Z10.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z24.D, P1/M, Z11.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z24.D, P1/M, Z12.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z17.D, P1/M, Z24.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z21, [SP, #13, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z24, [SP, #12, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMAD Z21.D, P1/M, Z25.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z24, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z18.D, P1/M, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z21, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMAD Z21.D, P1/M, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z24, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z21.D, P1/M, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z19.D, P1/M, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z21, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z21.D, P1/M, Z14.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z23.D, P1/M, Z2.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z21.D, P1/M, Z15.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z23.D, P1/M, Z3.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z21.D, P1/M, Z0.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z23.D, P1/M, Z4.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z17.D, P1/M, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z21, [SP, #11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z22, [SP, #10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z17.D, P1/M, Z23.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z21.D, P1/M, Z25.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z18.D, P1/M, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z21, [SP, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z18.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z21.D, P1/M, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z21.D, P1/M, Z28.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z19.D, P1/M, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1SW {Z20.D}, P0/Z, [X8, X13,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD X13, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ST1D {Z18.D}, P0, [X12, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
FMUL Z18.D, Z19.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z16.D, P1/M, Z16.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ST1D {Z16.D}, P0, [X11, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z17.D}, P0, [X10, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
WHILELO P0.D, X13, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 422840 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code