OV - exec - Loop 323

        (321) 0x4253a0 MOVI	D25, #0

        (321) 0x4253a4 LDR	D0, [SP]

        (321) 0x4253a8 FSUB	D0, D0, S25

        (321) 0x4253ac BL	4100f0

        (321) 0x4253b0 LDP	X8, X9, [X19]

        (321) 0x4253b4 STR	D0, [X8, X22,LSL #3]

        (321) 0x4253b8 ADD	X22, X22, #1

        (321) 0x4253bc SUB	X8, X9, X8

        (321) 0x4253c0 CMP	X22, X8,ASR #3

        (321) 0x4253c4 B.CS	425748

        (321) 0x4253c8 LDRB	W8, [X20, #664]

        (321) 0x4253cc TBZ	W8, #0, 42577c

        (321) 0x4253d0 LDRSW	X26, [X20, #672]

        (321) 0x4253d4 LDR	X8, [X21, #216]

        (321) 0x4253d8 LDR	W1, [X21, #584]

        (321) 0x4253dc ORR	X0, XZR, X20

        (321) 0x4253e0 LDR	X27, [X20, #656]

        (321) 0x4253e4 LDR	D0, [X8, X26,LSL #3]

        (321) 0x4253e8 STR	D0, [SP]

        (321) 0x4253ec BL	452bb0

        (321) 0x4253f0 LDR	X8, [X21, #160]

        (321) 0x4253f4 CBZ	X8, 4253a0

      (322) 0x4253f8 LDR	X11, [X27, #24]

      (322) 0x4253fc LDR	X12, [X21, #512]

      (322) 0x425400 LDR	X10, [X0, #72]

      (322) 0x425404 MOVI	D25, #0

      (322) 0x425408 PTRUE	P0.D, ALL

      (322) 0x42540c ORR	X9, XZR, XZR

      (322) 0x425410 MADD	X10, X22, X25, X10

      (322) 0x425414 LDR	W11, [X11, X26,LSL #2]

      (322) 0x425418 LDR	X13, [X21, #464]

      (322) 0x42541c LDR	X10, [X10, #24]

      (322) 0x425420 MUL	W11, W11, W8

      (322) 0x425424 ADD	X11, X12, W11,SXTW #3

      (322) 0x425428 LDR	X12, [X27, #616]

      (322) 0x42542c ADD	X14, X10, #8

      (322) 0x425430 LDR	X12, [X12, #24]

      (322) 0x425434 B	425450

    (325) 0x425440 FADD	D25, D18, D25

      (322) 0x425444 ADD	X9, X9, #1

      (322) 0x425448 CMP	X9, X8

      (322) 0x42544c B.EQ	4253a4

      (322) 0x425450 ADD	X16, X12, X9,LSL #2

      (322) 0x425454 LDP	W15, W16, [X16]

      (322) 0x425458 SBFM	X15, X15, #0, #31

      (322) 0x42545c SUB	W0, W16, W15

      (322) 0x425460 CMP	W0, #1

      (322) 0x425464 B.LT	425444

    (325) 0x425468 LDR	X16, [X11, X9,LSL #3]

    (325) 0x42546c CMP	W0, #1

    (325) 0x425470 LDR	D1, [X16, #8]

    (325) 0x425474 B.NE	425484

    (325) 0x425478 ORR	X18, XZR, XZR

    (325) 0x42547c ORR	W17, WZR, WZR

    (325) 0x425480 B	425508

  (324) 0x425484 AND	X1, X0, #0x0

  (324) 0x425488 SUB	W2, W26, W15

  (324) 0x42548c ADD	X3, X14, X15,LSL #3

  (324) 0x425490 ORR	X18, XZR, XZR

  (324) 0x425494 ORR	W17, WZR, WZR

  (324) 0x425498 B	4254b4

  (324) 0x4254a0 ADD	X3, X3, #16

  (324) 0x4254a4 ADD	X18, X18, #2

  (324) 0x4254a8 SUB	X1, X1, #2

  (324) 0x4254ac SUB	W2, W2, #2

  (324) 0x4254b0 CBZ	X1, 425504

  (324) 0x4254b4 LDUR	D2, [X3, #504]

  (324) 0x4254b8 FCMP	D2, D1

  (324) 0x4254bc CCMP	W2, #0, #4, #11

  (324) 0x4254c0 B.NE	4254e0

  (324) 0x4254c4 LDR	D2, [X3]

  (324) 0x4254c8 FCMP	D2, D1

  (324) 0x4254cc CCMP	W2, #1, #4, #11

  (324) 0x4254d0 B.EQ	4254a0

  (324) 0x4254d4 B	4254f8

0x4254e0 STR	D2, [X13, W17,SXTW #3]

0x4254e4 ADD	W17, W17, #1

0x4254e8 LDR	D2, [X3]

0x4254ec FCMP	D2, D1

0x4254f0 CCMP	W2, #1, #4, #11

0x4254f4 B.EQ	4254a0

  (324) 0x4254f8 STR	D2, [X13, W17,SXTW #3]

  (324) 0x4254fc ADD	W17, W17, #1

  (324) 0x425500 B	4254a0

  (324) 0x425504 TBZ	W0, #0, 425528

    (325) 0x425508 ADD	X0, X10, X15,LSL #3

    (325) 0x42550c ADD	W15, W15, W18

    (325) 0x425510 LDR	D2, [X0, X18,LSL #3]

    (325) 0x425514 FCMP	D2, D1

    (325) 0x425518 CCMP	W15, W26, #4, #11

    (325) 0x42551c B.EQ	425528

    (325) 0x425520 STR	D2, [X13, W17,SXTW #3]

    (325) 0x425524 ADD	W17, W17, #1

    (325) 0x425528 CMP	W17, #1

    (325) 0x42552c B.LT	425444

    (325) 0x425530 LDR	D1, [X16, #568]

    (325) 0x425534 LDUR	Q0, [X16, #136]

    (325) 0x425538 LDUR	Q5, [X16, #120]

    (325) 0x42553c ORR	W17, WZR, W17

    (325) 0x425540 CMP	X23, X17

    (325) 0x425544 LDUR	Q2, [X16, #104]

    (325) 0x425548 LDUR	Q7, [X16, #88]

    (325) 0x42554c LDUR	Q3, [X16, #72]

    (325) 0x425550 LDUR	Q16, [X16, #56]

    (325) 0x425554 LDUR	Q4, [X16, #40]

    (325) 0x425558 LDUR	Q17, [X16, #24]

    (325) 0x42555c LDR	X15, [X16, #536]

    (325) 0x425560 B.LS	425570

    (325) 0x425564 ORR	X16, XZR, XZR

    (325) 0x425568 MOVI	D18, #0

    (325) 0x42556c B	4256c0

    (325) 0x425570 LDR	D21, [X16, #32]

    (325) 0x425574 LDR	D22, [X16, #48]

    (325) 0x425578 LDR	D24, [X16, #64]

    (325) 0x42557c SUB	X27, X29, #64

    (325) 0x425580 DUP	Z18.D, Z1.D[0]

    (325) 0x425584 DUP	Z19.D, Z17.D[0]

    (325) 0x425588 DUP	Z20.D, Z4.D[0]

    (325) 0x42558c LDR	D26, [X16, #80]

    (325) 0x425590 LDR	D28, [X16, #96]

    (325) 0x425594 LDR	D30, [X16, #112]

    (325) 0x425598 DUP	Z23.D, Z16.D[0]

    (325) 0x42559c DUP	Z27.D, Z7.D[0]

    (325) 0x4255a0 LDR	D9, [X16, #128]

    (325) 0x4255a4 LDR	D12, [X16, #144]

    (325) 0x4255a8 DUP	Z6.D, Z2.D[0]

    (325) 0x4255ac MOVI	V11.2D, #0

    (325) 0x4255b0 STR	Z4, [X27, #507, MUL VL]

    (325) 0x4255b4 AND	X16, X24, X17

    (325) 0x4255b8 ORR	X18, XZR, XZR

    (325) 0x4255bc STR	Z3, [X27, #509, MUL VL]

    (325) 0x4255c0 DUP	Z4.D, Z3.D[0]

    (325) 0x4255c4 DUP	Z31.D, Z5.D[0]

    (325) 0x4255c8 STR	Z2, [X27, #510, MUL VL]

    (325) 0x4255cc STR	Z5, [X27, #508, MUL VL]

    (325) 0x4255d0 STR	Z0, [X27, #511, MUL VL]

    (325) 0x4255d4 DUP	Z10.D, Z0.D[0]

    (325) 0x4255d8 DUP	Z21.D, Z21.D[0]

    (325) 0x4255dc DUP	Z22.D, Z22.D[0]

    (325) 0x4255e0 DUP	Z24.D, Z24.D[0]

    (325) 0x4255e4 DUP	Z26.D, Z26.D[0]

    (325) 0x4255e8 DUP	Z28.D, Z28.D[0]

    (325) 0x4255ec DUP	Z30.D, Z30.D[0]

    (325) 0x4255f0 DUP	Z9.D, Z9.D[0]

    (325) 0x4255f4 DUP	Z12.D, Z12.D[0]

    (325) 0x4255f8 STR	D25, [SP, #8]

    (325) 0x4255fc HINT	#0

      (326) 0x425600 LD1D	{Z13.D}, P0/Z, [X13, X18,LSL #3]

      (326) 0x425604 DUP	Z2.D, X15

      (326) 0x425608 ADD	X18, X18, X23

      (326) 0x42560c CMP	X16, X18

      (326) 0x425610 FMUL	Z13.D, Z13.D, Z18.D

      (326) 0x425614 MOVPRFX	Z14, Z13

      (326) 0x425618 FCVTZS	Z14.D, P0/M, Z13.D

      (326) 0x42561c MOVPRFX	Z15, Z14

      (326) 0x425620 SCVTF	Z15.D, P0/M, Z14.D

      (326) 0x425624 ADR	Z2.D, [Z2, Z14.D,LSL #3]

      (326) 0x425628 LD1D	{Z0.D}, P0/Z, [X15, Z14.D,LSL #3]

      (326) 0x42562c LD1D	{Z3.D}, P0/Z, [V2, #1.D]

      (326) 0x425630 LD1D	{Z5.D}, P0/Z, [V2, #2.D]

      (326) 0x425634 LD1D	{Z2.D}, P0/Z, [V2, #3.D]

      (326) 0x425638 FSUB	Z13.D, Z13.D, Z15.D

      (326) 0x42563c FMUL	Z15.D, Z13.D, Z13.D

      (326) 0x425640 MOVPRFX	Z14, Z22

      (326) 0x425644 FMLA	Z14.D, P0/M, Z13.D, Z20.D

      (326) 0x425648 MOVPRFX	Z25, Z26

      (326) 0x42564c FMLA	Z25.D, P0/M, Z13.D, Z4.D

      (326) 0x425650 MOVPRFX	Z29, Z30

      (326) 0x425654 FMLA	Z29.D, P0/M, Z13.D, Z6.D

      (326) 0x425658 FMUL	Z8.D, Z15.D, Z13.D

      (326) 0x42565c FMLA	Z14.D, P0/M, Z15.D, Z21.D

      (326) 0x425660 FMLA	Z25.D, P0/M, Z15.D, Z24.D

      (326) 0x425664 FMLA	Z29.D, P0/M, Z15.D, Z28.D

      (326) 0x425668 FMAD	Z13.D, P0/M, Z10.D, Z12.D

      (326) 0x42566c FMLA	Z13.D, P0/M, Z15.D, Z9.D

      (326) 0x425670 FMLA	Z14.D, P0/M, Z8.D, Z19.D

      (326) 0x425674 FMLA	Z25.D, P0/M, Z8.D, Z23.D

      (326) 0x425678 FMLA	Z29.D, P0/M, Z8.D, Z27.D

      (326) 0x42567c FMAD	Z8.D, P0/M, Z31.D, Z13.D

      (326) 0x425680 FMAD	Z0.D, P0/M, Z14.D, Z11.D

      (326) 0x425684 FMLA	Z0.D, P0/M, Z25.D, Z3.D

      (326) 0x425688 FMLA	Z0.D, P0/M, Z29.D, Z5.D

      (326) 0x42568c MOVPRFX	Z11, Z0

      (326) 0x425690 FMLA	Z11.D, P0/M, Z8.D, Z2.D

      (326) 0x425694 B.NE	425600

    (325) 0x425698 FADDV	D18, P0, Z11.D

    (325) 0x42569c SUB	X18, X29, #64

    (325) 0x4256a0 LDR	D25, [SP, #8]

    (325) 0x4256a4 CMP	X16, X17

    (325) 0x4256a8 LDR	Z0, [X18, #511, MUL VL]

    (325) 0x4256ac LDR	Z2, [X18, #510, MUL VL]

    (325) 0x4256b0 LDR	Z3, [X18, #509, MUL VL]

    (325) 0x4256b4 LDR	Z5, [X18, #508, MUL VL]

    (325) 0x4256b8 LDR	Z4, [X18, #507, MUL VL]

    (325) 0x4256bc B.EQ	425440

    (325) 0x4256c0 ZIP1	V19.2D, V17.2D, V16.2D

    (325) 0x4256c4 ZIP1	V20.2D, V7.2D, V5.2D

    (325) 0x4256c8 ZIP2	V16.2D, V17.2D, V16.2D

    (325) 0x4256cc ZIP2	V5.2D, V7.2D, V5.2D

    (325) 0x4256d0 SUB	X17, X17, X16

    (325) 0x4256d4 ADD	X16, X13, X16,LSL #3

    (325) 0x4256d8 ZIP1	V7.2D, V4.2D, V3.2D

    (325) 0x4256dc ZIP1	V17.2D, V2.2D, V0.2D

    (325) 0x4256e0 ZIP2	V4.2D, V4.2D, V3.2D

    (325) 0x4256e4 ZIP2	V2.2D, V2.2D, V0.2D

      (327) 0x4256e8 LDR	D0, [X16], #8

      (327) 0x4256ec ORR	V24.16B, V2.16B, V2.16B

      (327) 0x4256f0 ORR	V23.16B, V4.16B, V4.16B

      (327) 0x4256f4 SUBS	X17, X17, #1

      (327) 0x4256f8 FMUL	D0, D0, D1

      (327) 0x4256fc FRINTZ	D3, D0

      (327) 0x425700 FCVTZS	W18, D0

      (327) 0x425704 FSUB	D0, D0, S3

      (327) 0x425708 ADD	X18, X15, W18,SXTW #3

      (327) 0x42570c FMUL	D3, D0, D0

      (327) 0x425710 FMLA	V24.2D, V17.2D, V0.D[0]

      (327) 0x425714 FMLA	V23.2D, V7.2D, V0.D[0]

      (327) 0x425718 LDP	Q21, Q22, [X18]

      (327) 0x42571c FMUL	D6, D3, D0

      (327) 0x425720 FMLA	V24.2D, V5.2D, V3.D[0]

      (327) 0x425724 FMLA	V23.2D, V16.2D, V3.D[0]

      (327) 0x425728 FMLA	V24.2D, V20.2D, V6.D[0]

      (327) 0x42572c FMLA	V23.2D, V19.2D, V6.D[0]

      (327) 0x425730 FMUL	V0.2D, V24.2D, V22.2D

      (327) 0x425734 FMLA	V0.2D, V23.2D, V21.2D

      (327) 0x425738 FADDP	D0, V0.2D

      (327) 0x42573c FADD	D18, D18, D0

      (327) 0x425740 B.NE	4256e8

    (325) 0x425744 B	425440

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 229

--------------------------------------------------------------------------------

223:     return X[i];

[...]

229:     return X[i];

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 107 - 132

--------------------------------------------------------------------------------

107:     for (int k = 0; k < ratios.size(); ++k)

108:       ratios[k] = std::exp(Uat[VP.refPtcl] - computeU(VP.getRefPS(), VP.refPtcl, VP.getDistTableAB(myTableID).getDistRow(k).data()));

[...]

126:     const int igt = P.GroupID[iat] * NumGroups;

127:     for (int jg = 0; jg < NumGroups; ++jg)

128:     {

129:       const FuncType& f2(*F[igt + jg]);

130:       int iStart = P.first(jg);

131:       int iEnd   = P.last(jg);

132:       curUat += f2.evaluateV(iat, iStart, iEnd, dist, DistCompressed.data());

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/refwrap.h: 351 - 351

--------------------------------------------------------------------------------

351:       { return *_M_data; }

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/optional: 469 - 991

--------------------------------------------------------------------------------

469:       { return static_cast<const _Dp*>(this)->_M_payload._M_engaged; }

[...]

991: 	if (this->_M_is_engaged())

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 313 - 313

--------------------------------------------------------------------------------

313:   inline int first(int igroup) const { return (*group_offsets_)[igroup]; }

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h: 993 - 1150

--------------------------------------------------------------------------------

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1131: 	return *(this->_M_impl._M_start + __n);

[...]

1150: 	return *(this->_M_impl._M_start + __n);

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 233 - 260

--------------------------------------------------------------------------------

233:   const int iLimit = iEnd - iStart;

234:

235: #pragma vector always

236:   for (int jat = 0; jat < iLimit; jat++)

237:   {

238:     real_type r = distArray[jat];

239:     // pick the distances smaller than the cutoff and avoid the reference atom

240:     if (r < cutoff_radius && iStart + jat != iat)

241:       distArrayCompressed[iCount++] = distArray[jat];

242:   }

243:

244:   real_type d = 0.0;

245:   //#pragma omp simd reduction(+:d)

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

Coverage (%)	Name	Source Location	Module
►98.08+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:272	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:126	exec
○	main.omp_outlined.62	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.92+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:272	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:126	exec
○	main.omp_outlined.62	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:409	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:172	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.20
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	BsplineFunctor.h:238-241
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.00
CQA cycles if no scalar integer	0.83
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.25
Front-end cycles	0.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.83
P11 cycles	0.50
P12 cycles	0.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	6.00
Nb uops	6.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.20
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	BsplineFunctor.h:238-241
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.00
CQA cycles if no scalar integer	0.83
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.25
Front-end cycles	0.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.83
P11 cycles	0.50
P12 cycles	0.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	6.00
Nb uops	6.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	BsplineFunctor.h:233-260
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107-108,126-132
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/refwrap.h:351
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/optional:469,991
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h:993,1131,1150
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:233-260

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:238-241.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.00 to 0.83 cycles (1.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.00 to 0.25 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	6
nb uops	6
loop length	24
used w registers	2
used x registers	2
used b registers	0
used h registers	0
used s registers	0
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	0.75 cycles
front end	0.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	1.00	1.00	0.00	0.00	0.83	0.50	0.67	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	1.00	1.00	0.00	0.00	0.83	0.50	0.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.75
Dispatch	1.00
Overall L1	1.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4254e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
STR D2, [X13, W17,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD W17, W17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D2, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FCMP D2, D1	1	0	0	0	0	0	0	1	0	0	0	0	2	1	scal (25.0%)
CCMP W2, #1, #4, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B.EQ 4254a0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	BsplineFunctor.h:233-260
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:107-108,126-132
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/refwrap.h:351
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/optional:469,991
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h:993,1131,1150
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:233-260

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:238-241.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.00 to 0.83 cycles (1.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.00 to 0.25 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	6
nb uops	6
loop length	24
used w registers	2
used x registers	2
used b registers	0
used h registers	0
used s registers	0
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	0.75 cycles
front end	0.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	1.00	1.00	0.00	0.00	0.83	0.50	0.67	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	1.00	1.00	0.00	0.00	0.83	0.50	0.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.75
Dispatch	1.00
Overall L1	1.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4254e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
STR D2, [X13, W17,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD W17, W17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D2, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FCMP D2, D1	1	0	0	0	0	0	0	1	0	0	0	0	2	1	scal (25.0%)
CCMP W2, #1, #4, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B.EQ 4254a0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code