OV - exec - Loop 326

	Loop Id: 326	Module: exec	Source: BsplineFunctor.h:246-260 [...]	Coverage: 0.03%

0x425600 LD1D	{Z13.D}, P0/Z, [X13, X18,LSL #3]    [1]

0x425604 DUP	Z2.D, X15

0x425608 ADD	X18, X18, X23

0x42560c CMP	X16, X18

0x425610 FMUL	Z13.D, Z13.D, Z18.D

0x425614 MOVPRFX	Z14, Z13

0x425618 FCVTZS	Z14.D, P0/M, Z13.D

0x42561c MOVPRFX	Z15, Z14

0x425620 SCVTF	Z15.D, P0/M, Z14.D

0x425624 ADR	Z2.D, [Z2, Z14.D,LSL #3]    [4]

0x425628 LD1D	{Z0.D}, P0/Z, [X15, Z14.D,LSL #3]    [2]

0x42562c LD1D	{Z3.D}, P0/Z, [V2, #1.D]    [3]

0x425630 LD1D	{Z5.D}, P0/Z, [V2, #2.D]    [3]

0x425634 LD1D	{Z2.D}, P0/Z, [V2, #3.D]    [3]

0x425638 FSUB	Z13.D, Z13.D, Z15.D

0x42563c FMUL	Z15.D, Z13.D, Z13.D

0x425640 MOVPRFX	Z14, Z22

0x425644 FMLA	Z14.D, P0/M, Z13.D, Z20.D

0x425648 MOVPRFX	Z25, Z26

0x42564c FMLA	Z25.D, P0/M, Z13.D, Z4.D

0x425650 MOVPRFX	Z29, Z30

0x425654 FMLA	Z29.D, P0/M, Z13.D, Z6.D

0x425658 FMUL	Z8.D, Z15.D, Z13.D

0x42565c FMLA	Z14.D, P0/M, Z15.D, Z21.D

0x425660 FMLA	Z25.D, P0/M, Z15.D, Z24.D

0x425664 FMLA	Z29.D, P0/M, Z15.D, Z28.D

0x425668 FMAD	Z13.D, P0/M, Z10.D, Z12.D

0x42566c FMLA	Z13.D, P0/M, Z15.D, Z9.D

0x425670 FMLA	Z14.D, P0/M, Z8.D, Z19.D

0x425674 FMLA	Z25.D, P0/M, Z8.D, Z23.D

0x425678 FMLA	Z29.D, P0/M, Z8.D, Z27.D

0x42567c FMAD	Z8.D, P0/M, Z31.D, Z13.D

0x425680 FMAD	Z0.D, P0/M, Z14.D, Z11.D

0x425684 FMLA	Z0.D, P0/M, Z25.D, Z3.D

0x425688 FMLA	Z0.D, P0/M, Z29.D, Z5.D

0x42568c MOVPRFX	Z11, Z0

0x425690 FMLA	Z11.D, P0/M, Z8.D, Z2.D

0x425694 B.NE	425600

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h: 1150 - 1150

--------------------------------------------------------------------------------

1150: 	return *(this->_M_impl._M_start + __n);

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 246 - 260

--------------------------------------------------------------------------------

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

Coverage (%)	Name	Source Location	Module
►98.86+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:272	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:126	exec
○	main.omp_outlined.62	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.14+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:272	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:126	exec
○	main.omp_outlined.62	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:409	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:172	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.03
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	stl_vector.h:1150-1150,BsplineFunctor.h:246-260
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	14.50
CQA cycles if FP arith vectorized	14.50
CQA cycles if fully vectorized	14.13
Front-end cycles	4.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	1.00
P5 cycles	0.50
P6 cycles	14.50
P7 cycles	14.50
P8 cycles	10.00
P9 cycles	10.00
P10 cycles	1.67
P11 cycles	1.67
P12 cycles	1.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	12
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	38.00
Nb uops	38.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.93
Nb FLOP add-sub	4.00
Nb FLOP mul	12.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.04
Bytes prefetched	0.00
Bytes loaded	160.13
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	2.00
Vectorization ratio all	75.00
Vectorization ratio load	83.33
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.00
Vector-efficiency ratio all	93.75
Vector-efficiency ratio load	87.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	85.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.03
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	stl_vector.h:1150-1150,BsplineFunctor.h:246-260
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	14.50
CQA cycles if FP arith vectorized	14.50
CQA cycles if fully vectorized	14.13
Front-end cycles	4.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	1.00
P5 cycles	0.50
P6 cycles	14.50
P7 cycles	14.50
P8 cycles	10.00
P9 cycles	10.00
P10 cycles	1.67
P11 cycles	1.67
P12 cycles	1.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	12
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	38.00
Nb uops	38.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.93
Nb FLOP add-sub	4.00
Nb FLOP mul	12.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.04
Bytes prefetched	0.00
Bytes loaded	160.13
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	2.00
Vectorization ratio all	75.00
Vectorization ratio load	83.33
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.00
Vector-efficiency ratio all	93.75
Vector-efficiency ratio load	87.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	85.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	BsplineFunctor.h:246-260
Module	exec

The loop is defined in:

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h:1150
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:246-260

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 93% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 14.50 to 14.12 cycles (1.03x speedup).

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

83% of VPU loads are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
20% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 64 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250
SCVTF: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:251

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 144 FP arithmetical operations:

68: addition or subtraction (64 inside FMA instructions)
76: multiply (64 inside FMA instructions)

The binary loop is loading 160 bytes.

Arithmetic intensity

Arithmetic intensity is 0.90 FP operations per loaded or stored byte.

General properties

nb instructions	38
nb uops	38
loop length	152
used w registers	0
used x registers	5
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	1
used z registers	28
nb stack references	0
ADD-SUB / MUL ratio	0.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	1.00	0.50	14.50	14.50	1.50	1.50	1.67	1.67	1.67	0.00	0.00
cycles	0.50	0.50	0.75	0.75	1.00	0.50	14.50	14.50	10.00	10.00	1.67	1.67	1.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	12.00

Cycles summary

Front-end	4.75
Dispatch	14.50
Data deps.	12.00
Overall L1	14.50

Vectorization ratios

INT

all	40%
load	83%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	75%
load	83%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	50%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	85%
load	87%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	83%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	93%
load	87%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	62%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

11% of peak load performance is reached (11.04 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 425600

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LD1D {Z13.D}, P0/Z, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
DUP Z2.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADD X18, X18, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FMUL Z13.D, Z13.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z14, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FCVTZS Z14.D, P0/M, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
MOVPRFX Z15, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SCVTF Z15.D, P0/M, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
ADR Z2.D, [Z2, Z14.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z0.D}, P0/Z, [X15, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V2, #1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V2, #2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z2.D}, P0/Z, [V2, #3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z13.D, Z13.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z15.D, Z13.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z14, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z14.D, P0/M, Z13.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z25, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z25.D, P0/M, Z13.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z29, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z29.D, P0/M, Z13.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z8.D, Z15.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z14.D, P0/M, Z15.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z25.D, P0/M, Z15.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z29.D, P0/M, Z15.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z13.D, P0/M, Z10.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z13.D, P0/M, Z15.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z14.D, P0/M, Z8.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z25.D, P0/M, Z8.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z29.D, P0/M, Z8.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z8.D, P0/M, Z31.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z0.D, P0/M, Z14.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z0.D, P0/M, Z25.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z0.D, P0/M, Z29.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z11, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z11.D, P0/M, Z8.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
B.NE 425600 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	BsplineFunctor.h:246-260
Module	exec

The loop is defined in:

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h:1150
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:246-260

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

83% of VPU loads are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
20% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 64 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250
SCVTF: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:251

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 144 FP arithmetical operations:

68: addition or subtraction (64 inside FMA instructions)
76: multiply (64 inside FMA instructions)

The binary loop is loading 160 bytes.

Arithmetic intensity

Arithmetic intensity is 0.90 FP operations per loaded or stored byte.

General properties

nb instructions	38
nb uops	38
loop length	152
used w registers	0
used x registers	5
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	1
used z registers	28
nb stack references	0
ADD-SUB / MUL ratio	0.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	1.00	0.50	14.50	14.50	1.50	1.50	1.67	1.67	1.67	0.00	0.00
cycles	0.50	0.50	0.75	0.75	1.00	0.50	14.50	14.50	10.00	10.00	1.67	1.67	1.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	12.00

Cycles summary

Front-end	4.75
Dispatch	14.50
Data deps.	12.00
Overall L1	14.50

Vectorization ratios

INT

all	40%
load	83%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	75%
load	83%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	50%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	85%
load	87%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	83%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	93%
load	87%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	62%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

11% of peak load performance is reached (11.04 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 425600

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LD1D {Z13.D}, P0/Z, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
DUP Z2.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADD X18, X18, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FMUL Z13.D, Z13.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z14, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FCVTZS Z14.D, P0/M, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
MOVPRFX Z15, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SCVTF Z15.D, P0/M, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
ADR Z2.D, [Z2, Z14.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z0.D}, P0/Z, [X15, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V2, #1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V2, #2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z2.D}, P0/Z, [V2, #3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z13.D, Z13.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z15.D, Z13.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z14, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z14.D, P0/M, Z13.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z25, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z25.D, P0/M, Z13.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z29, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z29.D, P0/M, Z13.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z8.D, Z15.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z14.D, P0/M, Z15.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z25.D, P0/M, Z15.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z29.D, P0/M, Z15.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z13.D, P0/M, Z10.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z13.D, P0/M, Z15.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z14.D, P0/M, Z8.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z25.D, P0/M, Z8.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z29.D, P0/M, Z8.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z8.D, P0/M, Z31.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z0.D, P0/M, Z14.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z0.D, P0/M, Z25.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z0.D, P0/M, Z29.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z11, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z11.D, P0/M, Z8.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
B.NE 425600 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code