OV - exec - Function miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector<double, std::allocator<double> >&)

	Function: miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios( ...	Module: exec	Source: TwoBodyJastrowRef.h:105-132 [...]	Coverage (incl. loops): 1.39% \| (excl. loops): 0.00%

/usr/include/c++/14/bits/refwrap.h: 351 - 351

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351:       { return *_M_data; }

/usr/include/c++/14/bits/stl_vector.h: 993 - 1147

--------------------------------------------------------------------------------

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1147:       operator[](size_type __n) const _GLIBCXX_NOEXCEPT

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 249

--------------------------------------------------------------------------------

223:     return X[i];

[...]

249:   inline const_pointer data() const { return X; }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 105 - 132

--------------------------------------------------------------------------------

105:   void evaluateRatios(VirtualParticleSet& VP, std::vector<ValueType>& ratios)

106:   {

107:     for (int k = 0; k < ratios.size(); ++k)

108:       ratios[k] = std::exp(Uat[VP.refPtcl] - computeU(VP.getRefPS(), VP.refPtcl, VP.getDistTableAB(myTableID).getDistRow(k).data()));

109:   }

[...]

125:     valT curUat(0);

126:     const int igt = P.GroupID[iat] * NumGroups;

127:     for (int jg = 0; jg < NumGroups; ++jg)

128:     {

129:       const FuncType& f2(*F[igt + jg]);

130:       int iStart = P.first(jg);

131:       int iEnd   = P.last(jg);

132:       curUat += f2.evaluateV(iat, iStart, iEnd, dist, DistCompressed.data());

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 313 - 316

--------------------------------------------------------------------------------

313:   inline int first(int igroup) const { return (*group_offsets_)[igroup]; }

314:

315:   ///return the last index of a group i

316:   inline int last(int igroup) const { return (*group_offsets_)[igroup + 1]; }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 231 - 260

--------------------------------------------------------------------------------

231:   ASSUME_ALIGNED(distArrayCompressed);

232:   int iCount       = 0;

233:   const int iLimit = iEnd - iStart;

234:

235: #pragma vector always

236:   for (int jat = 0; jat < iLimit; jat++)

237:   {

238:     real_type r = distArray[jat];

239:     // pick the distances smaller than the cutoff and avoid the reference atom

240:     if (r < cutoff_radius && iStart + jat != iat)

241:       distArrayCompressed[iCount++] = distArray[jat];

242:   }

243:

244:   real_type d = 0.0;

245:   //#pragma omp simd reduction(+:d)

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

/usr/include/c++/14/optional: 991 - 993

--------------------------------------------------------------------------------

991: 	if (this->_M_is_engaged())

992: 	  return this->_M_get();

993: 	__throw_bad_optional_access();

0x42bd20 STP	X29, X30, [SP, #864]!

0x42bd24 ADD	X29, SP, #0

0x42bd28 STP	X21, X22, [SP, #32]

0x42bd2c ORR	X21, XZR, X2

0x42bd30 STP	X25, X26, [SP, #64]

0x42bd34 ORR	X26, XZR, X0

0x42bd38 LDR	X2, [X2]

0x42bd3c LDR	X0, [X21, #8]

0x42bd40 CMP	X2, X0

0x42bd44 B.EQ	42c2b8

0x42bd48 MOVZ	X25, #0

0x42bd4c ADD	X22, X1, #656

0x42bd50 STP	X19, X20, [SP, #16]

0x42bd54 ORR	X19, XZR, X1

0x42bd58 MOVZ	X20, #0

0x42bd5c STP	X23, X24, [SP, #48]

0x42bd60 ADD	X23, X26, #192

0x42bd64 STP	X27, X28, [SP, #80]

0x42bd68 STP	D8, D9, [SP, #96]

0x42bd6c STP	D10, D11, [SP, #112]

0x42bd70 STP	D12, D13, [SP, #128]

0x42bd74 STP	D14, D15, [SP, #144]

0x42bd78 HINT	#0

0x42bd7c HINT	#0

(293) 0x42bd80 LDR	X1, [X23, #24]

(293) 0x42bd84 LDR	W24, [X19, #672]

(293) 0x42bd88 LDRB	W3, [X22, #8]

(293) 0x42bd8c LDR	D15, [X1, W24,SXTW #3]

(293) 0x42bd90 SBFM	X28, X24, #0, #31

(293) 0x42bd94 TBZ	W3, #0, 42c2c8

(293) 0x42bd98 ORR	X0, XZR, X19

(293) 0x42bd9c LDR	X27, [X19, #656]

(293) 0x42bda0 LDR	W1, [X26, #584]

(293) 0x42bda4 BL	48fde0

(293) 0x42bda8 LDR	X5, [X0, #72]

(293) 0x42bdac ADD	X4, X25, X25,LSL #2

(293) 0x42bdb0 LDR	X7, [X27, #24]

(293) 0x42bdb4 LDR	X13, [X26, #160]

(293) 0x42bdb8 ADD	X6, X5, X4

(293) 0x42bdbc LDR	X14, [X6, #24]

(293) 0x42bdc0 LDR	W8, [X7, X28,LSL #2]

(293) 0x42bdc4 MUL	W9, W8, W13

(293) 0x42bdc8 CBZ	X13, 42c278

(293) 0x42bdcc LDR	X11, [X27, #616]

(293) 0x42bdd0 MOVI	D2, #0

(293) 0x42bdd4 MOVZ	X8, #0

(293) 0x42bdd8 CNTW	X7, ALL

(293) 0x42bddc PTRUE	P7.B, ALL

(293) 0x42bde0 LDR	X4, [X26, #464]

(293) 0x42bde4 LDR	X10, [X26, #512]

(293) 0x42bde8 ADD	X12, X10, W9,SXTW #3

(293) 0x42bdec LDR	X11, [X11, #24]

(293) 0x42bdf0 ADDVL	X6, X4, #1

(293) 0x42bdf4 HINT	#0

(293) 0x42bdf8 HINT	#0

(293) 0x42bdfc HINT	#0

  (294) 0x42be00 LDR	X16, [X12, X8,LSL #3]

  (294) 0x42be04 LDR	W17, [X11, X8,LSL #2]

  (294) 0x42be08 ADD	X8, X8, #1

  (294) 0x42be0c LDR	W18, [X11, X8,LSL #2]

  (294) 0x42be10 CMP	W18, W17

  (294) 0x42be14 B.LE	42c26c

  (294) 0x42be18 SUB	W30, W18, W17

  (294) 0x42be1c SBFM	X15, X17, #61, #31

  (294) 0x42be20 LDR	D31, [X16, #8]

  (294) 0x42be24 ANDS	W3, W30, #0x7

  (294) 0x42be28 ADD	X0, X14, X15

  (294) 0x42be2c MOVZ	W2, #0

  (294) 0x42be30 ORR	W30, WZR, W17

  (294) 0x42be34 B.EQ	42bf6c

  (294) 0x42be38 CMP	W3, #1

  (294) 0x42be3c B.EQ	42bf40

  (294) 0x42be40 CMP	W3, #2

  (294) 0x42be44 B.EQ	42bf1c

  (294) 0x42be48 CMP	W3, #3

  (294) 0x42be4c B.EQ	42bef8

  (294) 0x42be50 CMP	W3, #4

  (294) 0x42be54 B.EQ	42bed4

  (294) 0x42be58 CMP	W3, #5

  (294) 0x42be5c B.EQ	42beb0

  (294) 0x42be60 CMP	W3, #6

  (294) 0x42be64 B.EQ	42be8c

  (294) 0x42be68 LDR	D30, [X14, X15]

  (294) 0x42be6c FCMPE	D31, D30

  (294) 0x42be70 B.LS	42be84

  (294) 0x42be74 CMP	W24, W17

  (294) 0x42be78 B.EQ	42be84

  (294) 0x42be7c MOVZ	W2, #1

  (294) 0x42be80 STR	D30, [X4]

  (294) 0x42be84 ADD	X0, X0, #8

  (294) 0x42be88 ADD	W30, W17, #1

  (294) 0x42be8c LDR	D0, [X0]

  (294) 0x42be90 FCMPE	D31, D0

  (294) 0x42be94 B.LS	42bea8

  (294) 0x42be98 CMP	W24, W30

  (294) 0x42be9c B.EQ	42bea8

  (294) 0x42bea0 STR	D0, [X4, W2,UXTW #3]

  (294) 0x42bea4 ADD	W2, W2, #1

  (294) 0x42bea8 ADD	X0, X0, #8

  (294) 0x42beac ADD	W30, W30, #1

  (294) 0x42beb0 LDR	D1, [X0]

  (294) 0x42beb4 FCMPE	D31, D1

  (294) 0x42beb8 B.LS	42becc

  (294) 0x42bebc CMP	W24, W30

  (294) 0x42bec0 B.EQ	42becc

  (294) 0x42bec4 STR	D1, [X4, W2,UXTW #3]

  (294) 0x42bec8 ADD	W2, W2, #1

  (294) 0x42becc ADD	X0, X0, #8

  (294) 0x42bed0 ADD	W30, W30, #1

  (294) 0x42bed4 LDR	D3, [X0]

  (294) 0x42bed8 FCMPE	D31, D3

  (294) 0x42bedc B.LS	42bef0

  (294) 0x42bee0 CMP	W24, W30

  (294) 0x42bee4 B.EQ	42bef0

  (294) 0x42bee8 STR	D3, [X4, W2,UXTW #3]

  (294) 0x42beec ADD	W2, W2, #1

  (294) 0x42bef0 ADD	X0, X0, #8

  (294) 0x42bef4 ADD	W30, W30, #1

  (294) 0x42bef8 LDR	D4, [X0]

  (294) 0x42befc FCMPE	D31, D4

  (294) 0x42bf00 B.LS	42bf14

  (294) 0x42bf04 CMP	W24, W30

  (294) 0x42bf08 B.EQ	42bf14

  (294) 0x42bf0c STR	D4, [X4, W2,UXTW #3]

  (294) 0x42bf10 ADD	W2, W2, #1

  (294) 0x42bf14 ADD	X0, X0, #8

  (294) 0x42bf18 ADD	W30, W30, #1

  (294) 0x42bf1c LDR	D5, [X0]

  (294) 0x42bf20 FCMPE	D31, D5

  (294) 0x42bf24 B.LS	42bf38

  (294) 0x42bf28 CMP	W24, W30

  (294) 0x42bf2c B.EQ	42bf38

  (294) 0x42bf30 STR	D5, [X4, W2,UXTW #3]

  (294) 0x42bf34 ADD	W2, W2, #1

  (294) 0x42bf38 ADD	X0, X0, #8

  (294) 0x42bf3c ADD	W30, W30, #1

  (294) 0x42bf40 LDR	D6, [X0]

  (294) 0x42bf44 FCMPE	D31, D6

  (294) 0x42bf48 B.LS	42bf5c

  (294) 0x42bf4c CMP	W24, W30

  (294) 0x42bf50 B.EQ	42bf5c

  (294) 0x42bf54 STR	D6, [X4, W2,UXTW #3]

  (294) 0x42bf58 ADD	W2, W2, #1

  (294) 0x42bf5c ADD	W30, W30, #1

  (294) 0x42bf60 ADD	X0, X0, #8

  (294) 0x42bf64 CMP	W18, W30

  (294) 0x42bf68 B.EQ	42c07c

    (295) 0x42bf6c LDR	D7, [X0]

    (295) 0x42bf70 FCMPE	D31, D7

    (295) 0x42bf74 B.LS	42bf88

    (295) 0x42bf78 CMP	W24, W30

    (295) 0x42bf7c B.EQ	42bf88

    (295) 0x42bf80 STR	D7, [X4, W2,UXTW #3]

    (295) 0x42bf84 ADD	W2, W2, #1

    (295) 0x42bf88 LDR	D8, [X0, #8]

    (295) 0x42bf8c ADD	W28, W30, #1

    (295) 0x42bf90 ADD	X0, X0, #8

    (295) 0x42bf94 FCMPE	D31, D8

    (295) 0x42bf98 B.LS	42bfac

    (295) 0x42bf9c CMP	W24, W28

    (295) 0x42bfa0 B.EQ	42bfac

    (295) 0x42bfa4 STR	D8, [X4, W2,UXTW #3]

    (295) 0x42bfa8 ADD	W2, W2, #1

    (295) 0x42bfac LDR	D9, [X0, #8]

    (295) 0x42bfb0 ADD	W1, W28, #1

    (295) 0x42bfb4 FCMPE	D31, D9

    (295) 0x42bfb8 B.LS	42bfcc

    (295) 0x42bfbc CMP	W24, W1

    (295) 0x42bfc0 B.EQ	42bfcc

    (295) 0x42bfc4 STR	D9, [X4, W2,UXTW #3]

    (295) 0x42bfc8 ADD	W2, W2, #1

    (295) 0x42bfcc LDR	D10, [X0, #16]

    (295) 0x42bfd0 ADD	W27, W28, #2

    (295) 0x42bfd4 FCMPE	D31, D10

    (295) 0x42bfd8 B.LS	42bfec

    (295) 0x42bfdc CMP	W24, W27

    (295) 0x42bfe0 B.EQ	42bfec

    (295) 0x42bfe4 STR	D10, [X4, W2,UXTW #3]

    (295) 0x42bfe8 ADD	W2, W2, #1

    (295) 0x42bfec LDR	D11, [X0, #24]

    (295) 0x42bff0 ADD	W5, W28, #3

    (295) 0x42bff4 FCMPE	D31, D11

    (295) 0x42bff8 B.LS	42c00c

    (295) 0x42bffc CMP	W24, W5

    (295) 0x42c000 B.EQ	42c00c

    (295) 0x42c004 STR	D11, [X4, W2,UXTW #3]

    (295) 0x42c008 ADD	W2, W2, #1

    (295) 0x42c00c LDR	D12, [X0, #32]

    (295) 0x42c010 ADD	W9, W28, #4

    (295) 0x42c014 FCMPE	D31, D12

    (295) 0x42c018 B.LS	42c02c

    (295) 0x42c01c CMP	W24, W9

    (295) 0x42c020 B.EQ	42c02c

    (295) 0x42c024 STR	D12, [X4, W2,UXTW #3]

    (295) 0x42c028 ADD	W2, W2, #1

    (295) 0x42c02c LDR	D13, [X0, #40]

    (295) 0x42c030 ADD	W10, W28, #5

    (295) 0x42c034 FCMPE	D31, D13

    (295) 0x42c038 B.LS	42c04c

    (295) 0x42c03c CMP	W24, W10

    (295) 0x42c040 B.EQ	42c04c

    (295) 0x42c044 STR	D13, [X4, W2,UXTW #3]

    (295) 0x42c048 ADD	W2, W2, #1

    (295) 0x42c04c LDR	D14, [X0, #48]

    (295) 0x42c050 ADD	W17, W28, #6

    (295) 0x42c054 FCMPE	D31, D14

    (295) 0x42c058 B.LS	42c06c

    (295) 0x42c05c CMP	W24, W17

    (295) 0x42c060 B.EQ	42c06c

    (295) 0x42c064 STR	D14, [X4, W2,UXTW #3]

    (295) 0x42c068 ADD	W2, W2, #1

    (295) 0x42c06c ADD	W30, W28, #7

    (295) 0x42c070 ADD	X0, X0, #56

    (295) 0x42c074 CMP	W18, W30

    (295) 0x42c078 B.NE	42bf6c

  (294) 0x42c07c CBZ	W2, 42c26c

  (294) 0x42c080 ADD	X18, X16, #568

  (294) 0x42c084 LD1RD	{Z4.D}, P7/Z, [X16, #3]

  (294) 0x42c088 LD1RD	{Z5.D}, P7/Z, [X16, #4]

  (294) 0x42c08c LD1RD	{Z6.D}, P7/Z, [X16, #5]

  (294) 0x42c090 LD1RD	{Z7.D}, P7/Z, [X16, #6]

  (294) 0x42c094 LD1RD	{Z16.D}, P7/Z, [X16, #7]

  (294) 0x42c098 LD1RD	{Z17.D}, P7/Z, [X16, #8]

  (294) 0x42c09c LD1RD	{Z18.D}, P7/Z, [X16, #9]

  (294) 0x42c0a0 LD1RD	{Z19.D}, P7/Z, [X16, #10]

  (294) 0x42c0a4 LD1RD	{Z20.D}, P7/Z, [X16, #11]

  (294) 0x42c0a8 LD1RD	{Z21.D}, P7/Z, [X16, #12]

  (294) 0x42c0ac LD1RD	{Z22.D}, P7/Z, [X16, #13]

  (294) 0x42c0b0 LD1RD	{Z23.D}, P7/Z, [X16, #14]

  (294) 0x42c0b4 LD1RD	{Z24.D}, P7/Z, [X16, #15]

  (294) 0x42c0b8 LD1RD	{Z25.D}, P7/Z, [X16, #16]

  (294) 0x42c0bc LD1RD	{Z26.D}, P7/Z, [X16, #17]

  (294) 0x42c0c0 LD1RD	{Z27.D}, P7/Z, [X16, #18]

  (294) 0x42c0c4 LDR	X16, [X16, #536]

  (294) 0x42c0c8 MOVZ	X3, #0

  (294) 0x42c0cc ORR	W15, WZR, W2

  (294) 0x42c0d0 DUP	Z1.D, #0

  (294) 0x42c0d4 UQDECD	W15, ALL

  (294) 0x42c0d8 LD1RD	{Z3.D}, P7/Z, [X18]

  (294) 0x42c0dc WHILELO	P5.D, WZR, W15

  (294) 0x42c0e0 ORR	Z28.D, Z1.D, Z1.D

  (294) 0x42c0e4 WHILELO	P6.D, WZR, W2

    (296) 0x42c0e8 LD1D	{Z29.D}, P5/Z, [X6, X3,LSL #3]

    (296) 0x42c0ec LD1D	{Z30.D}, P6/Z, [X4, X3,LSL #3]

    (296) 0x42c0f0 FMUL	Z31.D, Z3.D, Z29.D

    (296) 0x42c0f4 FMUL	Z13.D, Z3.D, Z30.D

    (296) 0x42c0f8 MOVPRFX	Z8, Z31

    (296) 0x42c0fc FCVTZS	Z8.S, P7/M, Z31.D

    (296) 0x42c100 MOVPRFX	Z9, Z13

    (296) 0x42c104 FCVTZS	Z9.S, P7/M, Z13.D

    (296) 0x42c108 MOVPRFX	Z0, Z31

    (296) 0x42c10c FRINTZ	Z0.D, P7/M, Z31.D

    (296) 0x42c110 UZP1	Z30.S, Z9.S, Z8.S

    (296) 0x42c114 FSUB	Z31.D, Z31.D, Z0.D

    (296) 0x42c118 MOVPRFX	Z12, Z30

    (296) 0x42c11c ADD	Z12.S, Z12.S, #1

    (296) 0x42c120 FMUL	Z29.D, Z31.D, Z31.D

    (296) 0x42c124 SUNPKHI	Z8.D, Z12

    (296) 0x42c128 FMUL	Z14.D, Z29.D, Z31.D

    (296) 0x42c12c LD1D	{Z9.D}, P5/Z, [X16, Z8.D,LSL #3]

    (296) 0x42c130 FMUL	Z10.D, Z17.D, Z29.D

    (296) 0x42c134 FMLA	Z10.D, P7/M, Z16.D, Z14.D

    (296) 0x42c138 MOVPRFX	Z11, Z19

    (296) 0x42c13c FMLA	Z11.D, P7/M, Z18.D, Z31.D

    (296) 0x42c140 FADD	Z0.D, Z10.D, Z11.D

    (296) 0x42c144 FMUL	Z10.D, Z5.D, Z29.D

    (296) 0x42c148 FMUL	Z0.D, Z0.D, Z9.D

    (296) 0x42c14c FMLA	Z10.D, P7/M, Z4.D, Z14.D

    (296) 0x42c150 SUNPKHI	Z9.D, Z30

    (296) 0x42c154 LD1D	{Z8.D}, P5/Z, [X16, Z9.D,LSL #3]

    (296) 0x42c158 MOVPRFX	Z11, Z7

    (296) 0x42c15c FMLA	Z11.D, P7/M, Z6.D, Z31.D

    (296) 0x42c160 FADD	Z11.D, Z11.D, Z10.D

    (296) 0x42c164 FMUL	Z10.D, Z21.D, Z29.D

    (296) 0x42c168 FMAD	Z11.D, P7/M, Z8.D, Z0.D

    (296) 0x42c16c FMLA	Z10.D, P7/M, Z14.D, Z20.D

    (296) 0x42c170 MOVPRFX	Z0, Z23

    (296) 0x42c174 FMLA	Z0.D, P7/M, Z31.D, Z22.D

    (296) 0x42c178 FMUL	Z29.D, Z29.D, Z25.D

    (296) 0x42c17c FADD	Z8.D, Z10.D, Z0.D

    (296) 0x42c180 FMAD	Z14.D, P7/M, Z24.D, Z29.D

    (296) 0x42c184 MOVPRFX	Z10, Z30

    (296) 0x42c188 ADD	Z10.S, Z10.S, #2

    (296) 0x42c18c FADD	Z1.D, P5/M, Z1.D, Z11.D

    (296) 0x42c190 FMAD	Z31.D, P7/M, Z26.D, Z27.D

    (296) 0x42c194 MOVPRFX	Z11, Z30

    (296) 0x42c198 ADD	Z11.S, Z11.S, #3

    (296) 0x42c19c FADD	Z31.D, Z31.D, Z14.D

    (296) 0x42c1a0 SUNPKHI	Z0.D, Z11

    (296) 0x42c1a4 SUNPKHI	Z14.D, Z10

    (296) 0x42c1a8 LD1D	{Z29.D}, P5/Z, [X16, Z0.D,LSL #3]

    (296) 0x42c1ac LD1D	{Z9.D}, P5/Z, [X16, Z14.D,LSL #3]

    (296) 0x42c1b0 SUNPKLO	Z30.D, Z30

    (296) 0x42c1b4 FMLA	Z1.D, P5/M, Z9.D, Z8.D

    (296) 0x42c1b8 SUNPKLO	Z8.D, Z10

    (296) 0x42c1bc FMLA	Z1.D, P5/M, Z29.D, Z31.D

    (296) 0x42c1c0 LD1D	{Z14.D}, P6/Z, [X16, Z8.D,LSL #3]

    (296) 0x42c1c4 SUNPKLO	Z31.D, Z11

    (296) 0x42c1c8 MOVPRFX	Z9, Z13

    (296) 0x42c1cc FRINTZ	Z9.D, P7/M, Z13.D

    (296) 0x42c1d0 LD1D	{Z11.D}, P6/Z, [X16, Z30.D,LSL #3]

    (296) 0x42c1d4 FSUB	Z8.D, Z13.D, Z9.D

    (296) 0x42c1d8 SUNPKLO	Z12.D, Z12

    (296) 0x42c1dc FMUL	Z29.D, Z8.D, Z8.D

    (296) 0x42c1e0 FMUL	Z30.D, Z29.D, Z8.D

    (296) 0x42c1e4 FMUL	Z13.D, Z17.D, Z29.D

    (296) 0x42c1e8 FMLA	Z13.D, P7/M, Z16.D, Z30.D

    (296) 0x42c1ec LD1D	{Z10.D}, P6/Z, [X16, Z12.D,LSL #3]

    (296) 0x42c1f0 ADD	X3, X3, X7

    (296) 0x42c1f4 MOVPRFX	Z12, Z19

    (296) 0x42c1f8 FMLA	Z12.D, P7/M, Z18.D, Z8.D

    (296) 0x42c1fc WHILELO	P5.D, W3, W15

    (296) 0x42c200 FADD	Z9.D, Z12.D, Z13.D

    (296) 0x42c204 MOVPRFX	Z13, Z7

    (296) 0x42c208 FMLA	Z13.D, P7/M, Z6.D, Z8.D

    (296) 0x42c20c LD1D	{Z0.D}, P6/Z, [X16, Z31.D,LSL #3]

    (296) 0x42c210 FMUL	Z12.D, Z9.D, Z10.D

    (296) 0x42c214 FMUL	Z31.D, Z5.D, Z29.D

    (296) 0x42c218 FMUL	Z10.D, Z21.D, Z29.D

    (296) 0x42c21c FMLA	Z31.D, P7/M, Z4.D, Z30.D

    (296) 0x42c220 MOVPRFX	Z9, Z23

    (296) 0x42c224 FMLA	Z9.D, P7/M, Z8.D, Z22.D

    (296) 0x42c228 FADD	Z31.D, Z13.D, Z31.D

    (296) 0x42c22c FMUL	Z29.D, Z29.D, Z25.D

    (296) 0x42c230 FMAD	Z31.D, P7/M, Z11.D, Z12.D

    (296) 0x42c234 FMAD	Z8.D, P7/M, Z26.D, Z27.D

    (296) 0x42c238 MOVPRFX	Z11, Z10

    (296) 0x42c23c FMLA	Z11.D, P7/M, Z30.D, Z20.D

    (296) 0x42c240 FADD	Z28.D, P6/M, Z28.D, Z31.D

    (296) 0x42c244 FMAD	Z30.D, P7/M, Z24.D, Z29.D

    (296) 0x42c248 FADD	Z13.D, Z9.D, Z11.D

    (296) 0x42c24c FMLA	Z28.D, P6/M, Z14.D, Z13.D

    (296) 0x42c250 FADD	Z14.D, Z30.D, Z8.D

    (296) 0x42c254 FMLA	Z28.D, P6/M, Z0.D, Z14.D

    (296) 0x42c258 WHILELO	P6.D, W3, W2

    (296) 0x42c25c B.NE	42c0e8

  (294) 0x42c260 FADD	Z3.D, Z28.D, Z1.D

  (294) 0x42c264 FADDV	D1, P7, Z3.D

  (294) 0x42c268 FADD	D2, D2, D1

  (294) 0x42c26c CMP	X13, X8

  (294) 0x42c270 B.NE	42be00

(293) 0x42c274 FSUB	D15, D15, S2

(293) 0x42c278 FMOV	D0, D15

(293) 0x42c27c ADD	X20, X20, #1

(293) 0x42c280 BL	4100e0

(293) 0x42c284 LDP	X28, X1, [X21]

(293) 0x42c288 SUB	X27, X1, X28

(293) 0x42c28c STR	D0, [X28, X25]

(293) 0x42c290 ADD	X25, X25, #8

(293) 0x42c294 CMP	X20, X27,ASR #3

(293) 0x42c298 B.CC	42bd80

0x42c29c LDP	D8, D9, [SP, #96]

0x42c2a0 LDP	X19, X20, [SP, #16]

0x42c2a4 LDP	X23, X24, [SP, #48]

0x42c2a8 LDP	X27, X28, [SP, #80]

0x42c2ac LDP	D10, D11, [SP, #112]

0x42c2b0 LDP	D12, D13, [SP, #128]

0x42c2b4 LDP	D14, D15, [SP, #144]

0x42c2b8 LDP	X21, X22, [SP, #32]

0x42c2bc LDP	X25, X26, [SP, #64]

0x42c2c0 LDP	X29, X30, [SP], #160

0x42c2c4 RET

0x42c2c8 BL	410880

0x42c2cc HINT	#0

0x42c2d0 HINT	#0

0x42c2d4 HINT	#0

0x42c2d8 HINT	#0

0x42c2dc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.48+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:993	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	TwoBodyJastrowRef.h:105-132
Module	exec

The function is defined in:

/usr/include/c++/14/bits/refwrap.h:351
/usr/include/c++/14/bits/stl_vector.h:993,1147
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,249
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:105-109,125-132
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:231-260
/usr/include/c++/14/optional:991-993

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.33 to 3.33 cycles (2.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 42% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 7.33 to 3.25 cycles (2.26x speedup).

Details

33% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
40% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

std::__throw_bad_optional_access(): 1 occurrences►
- /usr/include/c++/14/optional:993

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	41
nb uops	34
loop length	164
used w registers	0
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	8
used q registers	0
used v registers	0
used z registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.75	2.75	2.75	2.75	2.00	2.00	0.00	0.00	7.33	7.33	7.33	3.00	3.00
cycles	1.50	1.50	2.75	2.75	2.75	2.75	2.00	2.00	0.00	0.00	7.33	7.33	7.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.25
Dispatch	7.33
Overall L1	7.33

Vectorization ratios

all	33%
load	50%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	42%
load	46%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.33 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42bd20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X21, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 42c2b8 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x598>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X22, X1, #656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X23, X26, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
HINT #0																			N/A
HINT #0																			N/A
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #160	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 410880 <_ZSt27__throw_bad_optional_accessv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	TwoBodyJastrowRef.h:105-132
Module	exec

The function is defined in:

/usr/include/c++/14/bits/refwrap.h:351
/usr/include/c++/14/bits/stl_vector.h:993,1147
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,249
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:105-109,125-132
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:231-260
/usr/include/c++/14/optional:991-993

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.33 to 3.33 cycles (2.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

33% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
40% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

std::__throw_bad_optional_access(): 1 occurrences►
- /usr/include/c++/14/optional:993

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	41
nb uops	34
loop length	164
used w registers	0
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	8
used q registers	0
used v registers	0
used z registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.75	2.75	2.75	2.75	2.00	2.00	0.00	0.00	7.33	7.33	7.33	3.00	3.00
cycles	1.50	1.50	2.75	2.75	2.75	2.75	2.00	2.00	0.00	0.00	7.33	7.33	7.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.25
Dispatch	7.33
Overall L1	7.33

Vectorization ratios

all	33%
load	50%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	42%
load	46%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.33 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42bd20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X21, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 42c2b8 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x598>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X22, X1, #656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X23, X26, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
HINT #0																			N/A
HINT #0																			N/A
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #160	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 410880 <_ZSt27__throw_bad_optional_accessv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)–	1.39	2.12
▼Loop 293 - TwoBodyJastrowRef.h:107-132 - exec–	0.02	0.03
▼Loop 294 - TwoBodyJastrowRef.h:127-132 - exec–	0.01	0.03
○Loop 295 - BsplineFunctor.h:236-241 - exec	1.32	2.00
○Loop 296 - BsplineFunctor.h:246-260 - exec	0.03	0.05

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