OV - exec - Function miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector<double, std::allocator<double> >&)

	Function: miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int ...	Module: exec	Source: einspline_spo_ref.hpp:172-189 [...]	Coverage (incl. loops): 23.48% \| (excl. loops): 0.04%

/usr/include/c++/14/bits/stl_algobase.h: 238 - 952

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238:       if (__b < __a)

[...]

413: 	{ *__to = *__from; }

[...]

451: 	  if (__builtin_expect(_Num > 1, true))

452: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

[...]

951:       for (; __first != __last; ++__first)

952: 	*__first = __tmp;

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp: 53 - 63

--------------------------------------------------------------------------------

53:   if (x < 0)

[...]

60:     ind = static_cast<int>(x);

61:     dx = x - ind;

62:     // upper bound

63:     if (ind > nmax)

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 172 - 189

--------------------------------------------------------------------------------

172:     ScopedTimer local_timer(timer);

173:

174:     auto u = Lattice.toUnit_floor(P.activeR(iat));

175:     for (int i = 0; i < nBlocks; ++i)

176:       MultiBsplineEvalRef::evaluate_v(einsplines[i], u[0], u[1], u[2], psi[i].data(), nSplinesPerBlock);

177:   }

178:

179:   inline void evaluate(const ParticleSet& P, int iat, ValueVector_t& psi_v)

180:   {

181:     evaluate_v(P, iat);

182:

183:     for (int i = 0; i < nBlocks; ++i)

184:     {

185:       // in real simulation, phase needs to be applied. Here just fake computation

186:       const int first = i * nBlocks;

187:       std::copy_n(psi[i].data(), std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize) - first, psi_v.data() + first);

188:     }

189:   }

/usr/include/c++/14/bits/stl_algo.h: 683 - 709

--------------------------------------------------------------------------------

683:     { return std::copy(__first, __first + __n, __result); }

[...]

709:       if (__n2 <= 0)

/usr/include/c++/14/bits/stl_vector.h: 1263 - 1263

--------------------------------------------------------------------------------

1263:       { return _M_data_ptr(this->_M_impl._M_start); }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 229 - 229

--------------------------------------------------------------------------------

229:     return X[i];

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 42 - 71

--------------------------------------------------------------------------------

42:   x -= spline_m->x_grid.start;

43:   y -= spline_m->y_grid.start;

44:   z -= spline_m->z_grid.start;

45:   T tx, ty, tz;

46:   int ix, iy, iz;

47:   spline2::getSplineBound(x * spline_m->x_grid.delta_inv, tx, ix, spline_m->x_grid.num - 1);

48:   spline2::getSplineBound(y * spline_m->y_grid.delta_inv, ty, iy, spline_m->y_grid.num - 1);

49:   spline2::getSplineBound(z * spline_m->z_grid.delta_inv, tz, iz, spline_m->z_grid.num - 1);

[...]

57:   const intptr_t ys = spline_m->y_stride;

58:   const intptr_t zs = spline_m->z_stride;

59:

60:   constexpr T zero(0);

61:   std::fill(vals, vals + num_splines, zero);

62:

63:   for (size_t i = 0; i < 4; i++)

64:     for (size_t j = 0; j < 4; j++)

65:     {

66:       const T pre00           = a[i] * b[j];

67:       const T* restrict coefs = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs;

68:       for (size_t n = 0; n < num_splines; n++)

69:         vals[n] += pre00 *

70:             (c[0] * coefs[n] + c[1] * coefs[n + zs] + c[2] * coefs[n + 2 * zs] +

71:              c[3] * coefs[n + 3 * zs]);

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h: 168 - 174

--------------------------------------------------------------------------------

168:     val_dot = toUnit(r);

169:     for (int i = 0; i < D; i++)

170:       if (-std::numeric_limits<T1>::epsilon() < val_dot[i] && val_dot[i] < 0)

171:         val_dot[i] = T1(0.0);

172:       else

173:         val_dot[i] -= std::floor(val_dot[i]);

174:     return val_dot;

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 143 - 143

--------------------------------------------------------------------------------

143:     return (active_ptcl_ == iat) ? active_pos_ : R[iat];

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h: 150 - 152

--------------------------------------------------------------------------------

150:     return TinyVector<Type_t, 3>(lhs[0] * rhs[0] + lhs[1] * rhs[3] + lhs[2] * rhs[6],

151:                                  lhs[0] * rhs[1] + lhs[1] * rhs[4] + lhs[2] * rhs[7],

152:                                  lhs[0] * rhs[2] + lhs[1] * rhs[5] + lhs[2] * rhs[8]);

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp: 54 - 57

--------------------------------------------------------------------------------

54:     a[0] = ((A00 * tx + A01) * tx + A02) * tx + A03;

55:     a[1] = ((A10 * tx + A11) * tx + A12) * tx + A13;

56:     a[2] = ((A20 * tx + A21) * tx + A22) * tx + A23;

57:     a[3] = ((A30 * tx + A31) * tx + A32) * tx + A33;

0x45ccc0 STP	X29, X30, [SP, #704]!

0x45ccc4 ADD	X29, SP, #0

0x45ccc8 STP	X19, X20, [SP, #16]

0x45cccc ORR	X20, XZR, X1

0x45ccd0 ORR	W19, WZR, W2

0x45ccd4 STP	X21, X22, [SP, #32]

0x45ccd8 ORR	X22, XZR, X0

0x45ccdc STP	X25, X26, [SP, #64]

0x45cce0 ORR	X26, XZR, X3

0x45cce4 STP	X27, X28, [SP, #80]

0x45cce8 STP	D8, D9, [SP, #96]

0x45ccec LDR	X27, [X0, #856]

0x45ccf0 ORR	X0, XZR, X27

0x45ccf4 BL	4cf640

0x45ccf8 LDR	W0, [X20, #292]

0x45ccfc ADD	X4, X20, #296

0x45cd00 CMP	W19, W0

0x45cd04 B.EQ	45cd14

0x45cd08 LDR	X2, [X20, #64]

0x45cd0c MOVZ	W1, #24

0x45cd10 SMADDL	X4, W19, W1, X2

0x45cd14 LDP	D28, D27, [X4]

0x45cd18 PTRUE	P7.B, ALL

0x45cd1c MOVZ	W5, #3

0x45cd20 ADD	X21, SP, #288

0x45cd24 WHILELO	P4.D, WZR, W5

0x45cd28 MOVZ	X3, #48304

0x45cd2c LDP	D26, D6, [X22, #232]

0x45cd30 DUP	Z30.D, X3

0x45cd34 CNTD	X6, ALL

0x45cd38 WHILELO	P5.D, W6, W5

0x45cd3c LDP	D4, D2, [X22, #248]

0x45cd40 LDP	D5, D3, [X22, #216]

0x45cd44 FMUL	D0, D27, D6

0x45cd48 LDR	D24, [X4, #16]

0x45cd4c FMUL	D1, D27, D4

0x45cd50 FMUL	D7, D27, D2

0x45cd54 LDR	D22, [X22, #280]

0x45cd58 LDP	D23, D25, [X22, #264]

0x45cd5c FMADD	D16, D28, D5, D0

0x45cd60 FMADD	D8, D28, D3, D1

0x45cd64 FMADD	D9, D28, D26, D7

0x45cd68 FMADD	D17, D24, D23, D16

0x45cd6c FMADD	D18, D24, D25, D8

0x45cd70 FMADD	D19, D24, D22, D9

0x45cd74 STP	D17, D18, [SP, #288]

0x45cd78 STR	D19, [SP, #304]

0x45cd7c LD1D	{Z20.D}, P4/Z, [X21, MUL VL]

0x45cd80 FCMLT	P6.D, P7/Z, Z20.D, #0.0000000

0x45cd84 MOVPRFX	Z21, Z20

0x45cd88 FRINTM	Z21.D, P7/M, Z20.D

0x45cd8c FCMGT	P0.D, P6/Z, Z20.D, Z30.D

0x45cd90 EOR	P1.B, P7/Z, P0.B, P7.B

0x45cd94 MOVPRFX	Z21.D, P1/Z, Z21.D

0x45cd98 FSUBR	Z21.D, P1/M, Z21.D, Z20.D

0x45cd9c ST1D	{Z21.D}, P4, [X21, MUL VL]

0x45cda0 B.EQ	45cdc8

0x45cda4 LD1D	{Z31.D}, P5/Z, [X21, #1, MUL VL]

0x45cda8 FCMLT	P6.D, P7/Z, Z31.D, #0.0000000

0x45cdac MOVPRFX	Z29, Z31

0x45cdb0 FRINTM	Z29.D, P7/M, Z31.D

0x45cdb4 FCMGT	P15.D, P6/Z, Z31.D, Z30.D

0x45cdb8 EOR	P2.B, P7/Z, P15.B, P7.B

0x45cdbc MOVPRFX	Z29.D, P2/Z, Z29.D

0x45cdc0 FSUBR	Z29.D, P2/M, Z29.D, Z31.D

0x45cdc4 ST1D	{Z29.D}, P5, [X21, #1, MUL VL]

0x45cdc8 LDP	X8, X9, [SP, #288]

0x45cdcc LDR	X10, [X21, #16]

0x45cdd0 STP	X8, X9, [SP, #232]

0x45cdd4 LDP	D9, D30, [SP, #232]

0x45cdd8 STR	X10, [SP, #248]

0x45cddc LDR	W9, [X22, #48]

0x45cde0 LDR	D8, [SP, #248]

0x45cde4 STR	D30, [SP, #184]

0x45cde8 CMP	W9, #0

0x45cdec B.LE	45d14c

0x45cdf0 ORR	X11, XZR, #0x55

0x45cdf4 ORR	X12, XZR, #0x55

0x45cdf8 STP	D10, D11, [SP, #112]

0x45cdfc MOVK	X11, #16325

0x45ce00 MOVK	X12, #16357

0x45ce04 STP	X23, X24, [SP, #48]

0x45ce08 FMOV	D10, X11

0x45ce0c FMOV	D11, X12

0x45ce10 STP	D12, D13, [SP, #128]

0x45ce14 STP	D14, D15, [SP, #144]

0x45ce18 LDRSW	X19, [X22, #64]

0x45ce1c LDR	X23, [X22, #760]

0x45ce20 ADD	X13, X23, W9,UXTW #3

0x45ce24 LDR	X24, [X22, #784]

0x45ce28 UBFM	X25, X19, #61, #60

0x45ce2c STP	X13, X27, [SP, #192]

0x45ce30 STP	X22, X26, [SP, #208]

(913) 0x45ce34 LDR	X27, [X23]

(913) 0x45ce38 LDR	D24, [SP, #184]

(913) 0x45ce3c LDR	X4, [X24]

(913) 0x45ce40 LDR	D12, [X27, #40]

(913) 0x45ce44 LDP	D13, D14, [X27, #72]

(913) 0x45ce48 LDR	D15, [X27, #120]

(913) 0x45ce4c FSUB	D28, D9, S12

(913) 0x45ce50 FSUB	D3, D24, S14

(913) 0x45ce54 FSUB	D5, D8, S15

(913) 0x45ce58 FMUL	D27, D28, D13

(913) 0x45ce5c FCMPE	D27, #0

(913) 0x45ce60 B.MI	45d21c

(913) 0x45ce64 LDR	W15, [X27, #56]

(913) 0x45ce68 FCVTZS	W14, D27

(913) 0x45ce6c SUB	W16, W15, #1

(913) 0x45ce70 CMP	W16, W14

(913) 0x45ce74 B.LT	45d234

(913) 0x45ce78 ORR	X17, XZR, #0x55

(913) 0x45ce7c FRINTZ	D26, D27

(913) 0x45ce80 FSUB	D6, D27, S26

(913) 0x45ce84 MOVK	X17, #49093

(913) 0x45ce88 FMOV	D4, #0.5000000

(913) 0x45ce8c FMOV	D2, #-0.5000000

(913) 0x45ce90 FMOV	D23, #-1.0000000

(913) 0x45ce94 SBFM	X28, X14, #0, #31

(913) 0x45ce98 FMOV	D25, X17

(913) 0x45ce9c FMSUB	D0, D6, D4, D4

(913) 0x45cea0 FMUL	D22, D6, D6

(913) 0x45cea4 FMADD	D1, D6, D4, D23

(913) 0x45cea8 FMADD	D16, D6, D0, D4

(913) 0x45ceac FMUL	D7, D6, D25

(913) 0x45ceb0 FMADD	D26, D1, D22, D11

(913) 0x45ceb4 FMADD	D24, D6, D16, D10

(913) 0x45ceb8 FADD	D17, D7, D4

(913) 0x45cebc FNMUL	D27, D7, D22

(913) 0x45cec0 FMADD	D18, D6, D17, D2

(913) 0x45cec4 FMADD	D30, D6, D18, D10

(913) 0x45cec8 LDR	D19, [X27, #112]

(913) 0x45cecc FMUL	D20, D3, D19

(913) 0x45ced0 FCMPE	D20, #0

(913) 0x45ced4 B.MI	45d1e0

(913) 0x45ced8 LDR	W30, [X27, #96]

(913) 0x45cedc FCVTZS	W26, D20

(913) 0x45cee0 SUB	W20, W30, #1

(913) 0x45cee4 CMP	W20, W26

(913) 0x45cee8 B.LT	45d254

(913) 0x45ceec ORR	X0, XZR, #0x55

(913) 0x45cef0 FRINTZ	D21, D20

(913) 0x45cef4 FSUB	D31, D20, S21

(913) 0x45cef8 MOVK	X0, #49093

(913) 0x45cefc FMOV	D29, #0.5000000

(913) 0x45cf00 FMOV	D12, #-0.5000000

(913) 0x45cf04 FMOV	D14, #-1.0000000

(913) 0x45cf08 SBFM	X3, X26, #0, #31

(913) 0x45cf0c FMOV	D13, X0

(913) 0x45cf10 FMSUB	D15, D31, D29, D29

(913) 0x45cf14 FMUL	D3, D31, D31

(913) 0x45cf18 FMADD	D6, D31, D29, D14

(913) 0x45cf1c FMADD	D4, D31, D15, D29

(913) 0x45cf20 FMUL	D28, D31, D13

(913) 0x45cf24 FMADD	D22, D6, D3, D11

(913) 0x45cf28 FMADD	D23, D31, D4, D10

(913) 0x45cf2c FADD	D2, D28, D29

(913) 0x45cf30 FNMUL	D0, D28, D3

(913) 0x45cf34 FMADD	D25, D31, D2, D12

(913) 0x45cf38 FMADD	D1, D31, D25, D10

(913) 0x45cf3c LDR	D7, [X27, #152]

(913) 0x45cf40 FMUL	D5, D5, D7

(913) 0x45cf44 FCMPE	D5, #0

(913) 0x45cf48 B.MI	45d204

(913) 0x45cf4c LDR	W6, [X27, #136]

(913) 0x45cf50 FCVTZS	W5, D5

(913) 0x45cf54 SUB	W7, W6, #1

(913) 0x45cf58 CMP	W7, W5

(913) 0x45cf5c B.LT	45d274

(913) 0x45cf60 ORR	X8, XZR, #0x55

(913) 0x45cf64 FRINTZ	D16, D5

(913) 0x45cf68 FSUB	D17, D5, S16

(913) 0x45cf6c MOVK	X8, #49093

(913) 0x45cf70 FMOV	D18, #0.5000000

(913) 0x45cf74 FMOV	D20, #-0.5000000

(913) 0x45cf78 FMOV	D31, #-1.0000000

(913) 0x45cf7c SBFM	X11, X5, #0, #31

(913) 0x45cf80 FMOV	D21, X8

(913) 0x45cf84 FMSUB	D29, D17, D18, D18

(913) 0x45cf88 FMUL	D19, D17, D17

(913) 0x45cf8c FMADD	D13, D17, D18, D31

(913) 0x45cf90 FMADD	D12, D17, D29, D18

(913) 0x45cf94 FMUL	D14, D17, D21

(913) 0x45cf98 FMADD	D13, D13, D19, D11

(913) 0x45cf9c FMADD	D12, D17, D12, D10

(913) 0x45cfa0 FADD	D15, D14, D18

(913) 0x45cfa4 FNMUL	D14, D14, D19

(913) 0x45cfa8 FMADD	D3, D17, D15, D20

(913) 0x45cfac FMADD	D15, D17, D3, D10

(913) 0x45cfb0 LDR	X26, [X27, #32]

(913) 0x45cfb4 LDP	X20, X22, [X27, #16]

(913) 0x45cfb8 STP	D30, D26, [SP, #256]

(913) 0x45cfbc STP	D24, D27, [SP, #272]

(913) 0x45cfc0 STP	D1, D22, [SP, #288]

(913) 0x45cfc4 STP	D23, D0, [SP, #304]

(913) 0x45cfc8 CBZ	X25, 45cfe8

(913) 0x45cfcc ORR	X0, XZR, X4

(913) 0x45cfd0 ORR	X2, XZR, X25

(913) 0x45cfd4 STP	X3, X11, [SP, #168]

(913) 0x45cfd8 MOVZ	W1, #0

(913) 0x45cfdc BL	4101d0

(913) 0x45cfe0 LDP	X3, X11, [SP, #168]

(913) 0x45cfe4 ORR	X4, XZR, X0

(913) 0x45cfe8 MUL	X12, X26, X11

(913) 0x45cfec LDR	X13, [X27, #8]

(913) 0x45cff0 CBZ	X19, 45d120

(913) 0x45cff4 MUL	X14, X3, X22

(913) 0x45cff8 UBFM	X16, X22, #61, #60

(913) 0x45cffc UBFM	X27, X22, #60, #59

(913) 0x45d000 MADD	X0, X28, X20, X12

(913) 0x45d004 ADD	X1, SP, #256

(913) 0x45d008 CNTD	X12, ALL

(913) 0x45d00c SUB	X18, X16, X26,LSL #3

(913) 0x45d010 DUP	Z19.D, Z12.D[0]

(913) 0x45d014 DUP	Z15.D, Z15.D[0]

(913) 0x45d018 SUB	X17, XZR, X14,LSL #3

(913) 0x45d01c ADD	X15, X14, X22

(913) 0x45d020 ADD	X28, X14, X26

(913) 0x45d024 ADD	X30, X15, X26

(913) 0x45d028 ADD	X2, X13, X28,LSL #3

(913) 0x45d02c DUP	Z3.D, Z13.D[0]

(913) 0x45d030 ADD	X15, X17, X30,LSL #3

(913) 0x45d034 DUP	Z12.D, Z14.D[0]

(913) 0x45d038 WHILELO	P8.D, XZR, X19

(913) 0x45d03c ADD	X17, X16, X26,LSL #4

(913) 0x45d040 PTRUE	P7.B, ALL

(913) 0x45d044 SUB	X14, XZR, X26,LSL #3

  (916) 0x45d048 ADD	X6, X2, X0,LSL #3

  (916) 0x45d04c ORR	X26, XZR, X21

  (916) 0x45d050 LDR	D30, [X1]

  (916) 0x45d054 DUP	Z6.D, Z30.D[0]

    (915) 0x45d058 LDR	D27, [X26]

    (915) 0x45d05c SUB	X22, X6, X14,LSL #1

    (915) 0x45d060 MOVZ	X3, #0

    (915) 0x45d064 ADD	X13, X6, X14

    (915) 0x45d068 SUB	X11, X6, X14

    (915) 0x45d06c LD1RD	{Z24.D}, P7/Z, [X26, #1]

    (915) 0x45d070 ADD	X10, X6, X18

    (915) 0x45d074 ADD	X9, X6, X16

    (915) 0x45d078 FMUL	Z28.D, Z24.D, Z6.D

    (915) 0x45d07c ADD	X8, X6, X15

    (915) 0x45d080 ADD	X7, X6, X17

    (915) 0x45d084 ORR	P3.B, P8/Z, P8.B, P8.B

    (915) 0x45d088 FMUL	D26, D30, D27

    (915) 0x45d08c DUP	Z4.D, Z26.D[0]

      (914) 0x45d090 LD1D	{Z2.D}, P3/Z, [X6, X3,LSL #3]

      (914) 0x45d094 LD1D	{Z25.D}, P3/Z, [X13, X3,LSL #3]

      (914) 0x45d098 LD1D	{Z0.D}, P3/Z, [X22, X3,LSL #3]

      (914) 0x45d09c LD1D	{Z1.D}, P3/Z, [X11, X3,LSL #3]

      (914) 0x45d0a0 LD1D	{Z7.D}, P3/Z, [X4, X3,LSL #3]

      (914) 0x45d0a4 ADD	X5, X4, X3,LSL #3

      (914) 0x45d0a8 FMUL	Z23.D, Z3.D, Z2.D

      (914) 0x45d0ac FMUL	Z22.D, Z12.D, Z0.D

      (914) 0x45d0b0 FMAD	Z25.D, P7/M, Z15.D, Z23.D

      (914) 0x45d0b4 FMAD	Z1.D, P7/M, Z19.D, Z22.D

      (914) 0x45d0b8 FADD	Z5.D, Z1.D, Z25.D

      (914) 0x45d0bc FMAD	Z5.D, P7/M, Z4.D, Z7.D

      (914) 0x45d0c0 ST1D	{Z5.D}, P3, [X5, MUL VL]

      (914) 0x45d0c4 LD1D	{Z16.D}, P3/Z, [X9, X3,LSL #3]

      (914) 0x45d0c8 LD1D	{Z17.D}, P3/Z, [X10, X3,LSL #3]

      (914) 0x45d0cc LD1D	{Z20.D}, P3/Z, [X7, X3,LSL #3]

      (914) 0x45d0d0 LD1D	{Z31.D}, P3/Z, [X8, X3,LSL #3]

      (914) 0x45d0d4 FMUL	Z18.D, Z16.D, Z3.D

      (914) 0x45d0d8 FMUL	Z21.D, Z20.D, Z12.D

      (914) 0x45d0dc FMAD	Z17.D, P7/M, Z15.D, Z18.D

      (914) 0x45d0e0 FMAD	Z31.D, P7/M, Z19.D, Z21.D

      (914) 0x45d0e4 FADD	Z29.D, Z31.D, Z17.D

      (914) 0x45d0e8 FMLA	Z5.D, P7/M, Z29.D, Z28.D

      (914) 0x45d0ec ST1D	{Z5.D}, P3, [X5, MUL VL]

      (914) 0x45d0f0 ADD	X3, X3, X12

      (914) 0x45d0f4 WHILELO	P3.D, X3, X19

      (914) 0x45d0f8 B.NE	45d090

    (915) 0x45d0fc ADD	X26, X26, #16

    (915) 0x45d100 ADD	X28, SP, #320

    (915) 0x45d104 ADD	X6, X6, X27

    (915) 0x45d108 CMP	X26, X28

    (915) 0x45d10c B.NE	45d058

  (916) 0x45d110 ADD	X1, X1, #8

  (916) 0x45d114 ADD	X0, X0, X20

  (916) 0x45d118 CMP	X1, X21

  (916) 0x45d11c B.NE	45d048

(913) 0x45d120 LDR	X30, [SP, #192]

(913) 0x45d124 ADD	X23, X23, #8

(913) 0x45d128 ADD	X24, X24, #24

(913) 0x45d12c CMP	X30, X23

(913) 0x45d130 B.NE	45ce34

0x45d134 LDP	D10, D11, [SP, #112]

0x45d138 LDP	X23, X24, [SP, #48]

0x45d13c LDP	X27, X22, [SP, #200]

0x45d140 LDP	D12, D13, [SP, #128]

0x45d144 LDP	D14, D15, [SP, #144]

0x45d148 LDR	X26, [SP, #216]

0x45d14c ORR	X0, XZR, X27

0x45d150 MOVZ	X20, #0

0x45d154 BL	4cf8e0

0x45d158 LDR	W4, [X22, #48]

0x45d15c MOVZ	W19, #0

0x45d160 CMP	W4, #0

0x45d164 B.LE	45d1c4

(912) 0x45d168 LDR	W11, [X22, #64]

(912) 0x45d16c MUL	W6, W4, W19

(912) 0x45d170 ADD	W19, W19, #1

(912) 0x45d174 LDR	W13, [X22, #8]

(912) 0x45d178 MUL	W10, W19, W11

(912) 0x45d17c CMP	W10, W13

(912) 0x45d180 CSEL	W9, W10, W13, #13

(912) 0x45d184 SUB	W8, W9, W6

(912) 0x45d188 CMP	W8, #0

(912) 0x45d18c B.LE	45d1b8

(912) 0x45d190 LDR	X3, [X26, #24]

(912) 0x45d194 UBFM	X7, X6, #61, #31

(912) 0x45d198 UBFM	X2, X8, #61, #31

(912) 0x45d19c LDR	X5, [X22, #784]

(912) 0x45d1a0 ADD	X0, X3, X7

(912) 0x45d1a4 LDR	X1, [X5, X20]

(912) 0x45d1a8 CMP	X2, #8

(912) 0x45d1ac B.EQ	45d294

(912) 0x45d1b0 BL	4100a0

(912) 0x45d1b4 LDR	W4, [X22, #48]

(912) 0x45d1b8 ADD	X20, X20, #24

(912) 0x45d1bc CMP	W19, W4

(912) 0x45d1c0 B.LT	45d168

0x45d1c4 LDP	D8, D9, [SP, #96]

0x45d1c8 LDP	X19, X20, [SP, #16]

0x45d1cc LDP	X21, X22, [SP, #32]

0x45d1d0 LDP	X25, X26, [SP, #64]

0x45d1d4 LDP	X27, X28, [SP, #80]

0x45d1d8 LDP	X29, X30, [SP], #320

0x45d1dc RET

(913) 0x45d1e0 LDR	D7, [X27, #152]

(913) 0x45d1e4 FMOV	D23, D10

(913) 0x45d1e8 MOVI	D0, #0

(913) 0x45d1ec FMOV	D22, D11

(913) 0x45d1f0 FMOV	D1, D10

(913) 0x45d1f4 MOVZ	X3, #0

(913) 0x45d1f8 FMUL	D5, D5, D7

(913) 0x45d1fc FCMPE	D5, #0

(913) 0x45d200 B.GE	45cf4c

(913) 0x45d204 FMOV	D12, D10

(913) 0x45d208 MOVI	D14, #0

(913) 0x45d20c MOVZ	X11, #0

(913) 0x45d210 FMOV	D13, D11

(913) 0x45d214 FMOV	D15, D10

(913) 0x45d218 B	45cfb0

(913) 0x45d21c FMOV	D24, D10

(913) 0x45d220 MOVI	D27, #0

(913) 0x45d224 MOVZ	X28, #0

(913) 0x45d228 FMOV	D26, D11

(913) 0x45d22c FMOV	D30, D10

(913) 0x45d230 B	45cec8

(913) 0x45d234 ADRP	X18,

(913) 0x45d238 ADRP	X22,

(913) 0x45d23c MOVI	D30, #0

(913) 0x45d240 FMOV	D24, D11

(913) 0x45d244 SBFM	X28, X16, #0, #31

(913) 0x45d248 LDR	D27, [X18, #3392]

(913) 0x45d24c LDR	D26, [X22, #3400]

(913) 0x45d250 B	45cec8

(913) 0x45d254 ADRP	X1,

(913) 0x45d258 ADRP	X2,

(913) 0x45d25c MOVI	D1, #0

(913) 0x45d260 FMOV	D23, D11

(913) 0x45d264 SBFM	X3, X20, #0, #31

(913) 0x45d268 LDR	D0, [X1, #3392]

(913) 0x45d26c LDR	D22, [X2, #3400]

(913) 0x45d270 B	45cf3c

(913) 0x45d274 ADRP	X9,

(913) 0x45d278 ADRP	X10,

(913) 0x45d27c MOVI	D15, #0

(913) 0x45d280 FMOV	D12, D11

(913) 0x45d284 SBFM	X11, X7, #0, #31

(913) 0x45d288 LDR	D14, [X9, #3392]

(913) 0x45d28c LDR	D13, [X10, #3400]

(913) 0x45d290 B	45cfb0

(912) 0x45d294 LDR	D30, [X1]

(912) 0x45d298 STR	D30, [X3, X7]

(912) 0x45d29c B	45d1b8

Coverage (%)	Name	Source Location	Module
►50.17+	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:248	exec
○	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:992	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►48.33+	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:248	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:266	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.04% of application time for run gcc_0

Source file and lines	einspline_spo_ref.hpp:172-189
Module	exec

The function is defined in:

/usr/include/c++/14/bits/stl_algobase.h:238,413,451-452,951-952
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53,60-63
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:172-189
/usr/include/c++/14/bits/stl_algo.h:683,709
/usr/include/c++/14/bits/stl_vector.h:1263
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:42-49,57-71
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:168-174
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:54-57

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.50 to 9.50 cycles (1.84x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 45% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 17.50 to 8.92 cycles (1.96x speedup).

Details

34% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU loads are used in vector version.
36% of VPU stores are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
33% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249

Matching between your function (in the source code) and the binary function

The binary function is composed of 23 FP arithmetical operations:

14: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 76 bytes. The binary function is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	113
nb uops	113
loop length	452
used w registers	9
used x registers	25
used b registers	0
used h registers	0
used s registers	1
used d registers	28
used q registers	0
used v registers	0
used z registers	5
nb stack references	32
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.13 cycles
front end	14.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	8.50	8.50	8.50	8.50	9.50	9.50	6.50	6.50	17.50	17.17	17.33	5.00	5.00
cycles	3.50	3.50	8.50	8.50	8.50	8.50	9.50	9.50	6.50	6.50	17.50	17.17	17.33	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.13
Dispatch	17.50
Overall L1	17.50

Vectorization ratios

INT

all	32%
load	42%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	42%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	100%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	75%

INT+FP

all	34%
load	42%
store	36%
mul	0%
add-sub	50%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	42%
load	42%
store	51%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	56%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	100%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	81%

INT+FP

all	45%
load	42%
store	51%
mul	25%
add-sub	62%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	49%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.50 cycles. At this rate:

4% of peak load performance is reached (4.34 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.66 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 45ccc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #704]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W19, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X26, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR X27, [X0, #856]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4cf640 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W0, [X20, #292]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X20, #296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W19, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 45cd14 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SMADDL X4, W19, W1, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP D28, D27, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVZ W5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X21, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P4.D, WZR, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
MOVZ X3, #48304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP D26, D6, [X22, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
DUP Z30.D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
CNTD X6, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
WHILELO P5.D, W6, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LDP D4, D2, [X22, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D5, D3, [X22, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMUL D0, D27, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR D24, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D1, D27, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMUL D7, D27, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR D22, [X22, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP D23, D25, [X22, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMADD D16, D28, D5, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D8, D28, D3, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D9, D28, D26, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D17, D24, D23, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D18, D24, D25, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D19, D24, D22, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STP D17, D18, [SP, #288]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STR D19, [SP, #304]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LD1D {Z20.D}, P4/Z, [X21, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FCMLT P6.D, P7/Z, Z20.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z21, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
FRINTM Z21.D, P7/M, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	vect (100.0%)
FCMGT P0.D, P6/Z, Z20.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P1.B, P7/Z, P0.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
MOVPRFX Z21.D, P1/Z, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FSUBR Z21.D, P1/M, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z21.D}, P4, [X21, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B.EQ 45cdc8 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z31.D}, P5/Z, [X21, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FCMLT P6.D, P7/Z, Z31.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z29, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
FRINTM Z29.D, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	vect (100.0%)
FCMGT P15.D, P6/Z, Z31.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P2.B, P7/Z, P15.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
MOVPRFX Z29.D, P2/Z, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FSUBR Z29.D, P2/M, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z29.D}, P5, [X21, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP X8, X9, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X10, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X8, X9, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP D9, D30, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
STR X10, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W9, [X22, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR D8, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D30, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 45d14c <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X11, XZR, #0x55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X12, XZR, #0x55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
MOVK X11, #16325	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK X12, #16357	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
FMOV D10, X11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D11, X12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDRSW X19, [X22, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X23, [X22, #760]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X13, X23, W9,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X24, [X22, #784]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X25, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X13, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X26, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X22, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR X26, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4cf8e0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W4, [X22, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 45d1c4 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #320	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.04% of application time for run gcc_0

Source file and lines	einspline_spo_ref.hpp:172-189
Module	exec

The function is defined in:

/usr/include/c++/14/bits/stl_algobase.h:238,413,451-452,951-952
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53,60-63
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:172-189
/usr/include/c++/14/bits/stl_algo.h:683,709
/usr/include/c++/14/bits/stl_vector.h:1263
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:42-49,57-71
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:168-174
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:54-57

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.50 to 9.50 cycles (1.84x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

34% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU loads are used in vector version.
36% of VPU stores are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
33% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249

Matching between your function (in the source code) and the binary function

The binary function is composed of 23 FP arithmetical operations:

14: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 76 bytes. The binary function is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	113
nb uops	113
loop length	452
used w registers	9
used x registers	25
used b registers	0
used h registers	0
used s registers	1
used d registers	28
used q registers	0
used v registers	0
used z registers	5
nb stack references	32
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.13 cycles
front end	14.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	8.50	8.50	8.50	8.50	9.50	9.50	6.50	6.50	17.50	17.17	17.33	5.00	5.00
cycles	3.50	3.50	8.50	8.50	8.50	8.50	9.50	9.50	6.50	6.50	17.50	17.17	17.33	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.13
Dispatch	17.50
Overall L1	17.50

Vectorization ratios

INT

all	32%
load	42%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	42%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	100%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	75%

INT+FP

all	34%
load	42%
store	36%
mul	0%
add-sub	50%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	42%
load	42%
store	51%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	56%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	100%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	81%

INT+FP

all	45%
load	42%
store	51%
mul	25%
add-sub	62%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	49%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.50 cycles. At this rate:

4% of peak load performance is reached (4.34 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.66 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 45ccc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #704]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W19, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X26, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR X27, [X0, #856]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4cf640 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W0, [X20, #292]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X20, #296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W19, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 45cd14 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SMADDL X4, W19, W1, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP D28, D27, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVZ W5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X21, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P4.D, WZR, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
MOVZ X3, #48304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP D26, D6, [X22, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
DUP Z30.D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
CNTD X6, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
WHILELO P5.D, W6, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LDP D4, D2, [X22, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D5, D3, [X22, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMUL D0, D27, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR D24, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D1, D27, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMUL D7, D27, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR D22, [X22, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP D23, D25, [X22, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMADD D16, D28, D5, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D8, D28, D3, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D9, D28, D26, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D17, D24, D23, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D18, D24, D25, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D19, D24, D22, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STP D17, D18, [SP, #288]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STR D19, [SP, #304]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LD1D {Z20.D}, P4/Z, [X21, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FCMLT P6.D, P7/Z, Z20.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z21, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
FRINTM Z21.D, P7/M, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	vect (100.0%)
FCMGT P0.D, P6/Z, Z20.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P1.B, P7/Z, P0.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
MOVPRFX Z21.D, P1/Z, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FSUBR Z21.D, P1/M, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z21.D}, P4, [X21, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B.EQ 45cdc8 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z31.D}, P5/Z, [X21, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FCMLT P6.D, P7/Z, Z31.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z29, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
FRINTM Z29.D, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	vect (100.0%)
FCMGT P15.D, P6/Z, Z31.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P2.B, P7/Z, P15.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
MOVPRFX Z29.D, P2/Z, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FSUBR Z29.D, P2/M, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z29.D}, P5, [X21, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP X8, X9, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X10, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X8, X9, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP D9, D30, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
STR X10, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W9, [X22, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR D8, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D30, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 45d14c <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X11, XZR, #0x55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X12, XZR, #0x55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
MOVK X11, #16325	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK X12, #16357	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
FMOV D10, X11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D11, X12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDRSW X19, [X22, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X23, [X22, #760]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X13, X23, W9,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X24, [X22, #784]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X25, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X13, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X26, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X22, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR X26, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4cf8e0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W4, [X22, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 45d1c4 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #320	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)–	23.48	35.95
▼Loop 913 - einspline_spo_ref.hpp:175-176 - exec–	0.01	0.03
▼Loop 916 - MultiBsplineRef.hpp:63-71 - exec–	0.00	0.02
▼Loop 915 - MultiBsplineRef.hpp:64-71 - exec–	0.01	0.03
○Loop 914 - MultiBsplineRef.hpp:68-71 - exec	23.41	35.51
○Loop 912 - einspline_spo_ref.hpp:183-187 - exec	0.01	0.02

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Matching between your function (in the source code) and the binary function

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Cycles and memory resources usage

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ASM code