OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib<qmcplusplus::TinyVector<double, 3u>, std::allocator<qmcplusplus::TinyVector<double, 3u> > >&, qmcplusplus::ParticleAttrib<double, std::allocator<double> >&, bool)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evalua ...	Module: exec	Source: DiracDeterminantRef.cpp:152-181 [...]	Coverage (incl. loops): 0.54% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 61 - 94

--------------------------------------------------------------------------------

61:   inline typename BinaryReturn<T1, T2, OpMultiply>::Type_t operator()(const T1& a, const T2& b) const

62:   {

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 62 - 62

--------------------------------------------------------------------------------

62:       X[d] = T(0);

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 217 - 217

--------------------------------------------------------------------------------

217:   inline Type_t* operator[](size_type i) { return X.data() + i * D2; }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h: 110 - 131

--------------------------------------------------------------------------------

110:     for (unsigned d = 0; d < D; ++d)

[...]

129:     Type_t res = lhs[0] * rhs[0];

130:     for (unsigned d = 1; d < D; ++d)

131:       res += lhs[d] * rhs[d];

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 56 - 248

--------------------------------------------------------------------------------

56:   explicit inline Vector(T* ref, size_t n) : nLocal(n), X(ref) {}

[...]

144:   virtual ~Vector() { free(); }

[...]

210:     if (nAllocated)

[...]

221:   inline Type_t& operator[](size_t i)

222:   {

223:     return X[i];

[...]

248:   inline pointer data() { return X; }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h: 106 - 111

--------------------------------------------------------------------------------

106:     for (int iat = first, i = 0; iat < last; ++iat, ++i)

107:     {

108:       ValueVector_t v(logdet[i], OrbitalSetSize);

109:       GradVector_t g(dlogdet[i], OrbitalSetSize);

110:       ValueVector_t l(d2logdet[i], OrbitalSetSize);

111:       evaluate(P, iat, v, g, l);

/usr/include/c++/14/bits/unique_ptr.h: 193 - 193

--------------------------------------------------------------------------------

193:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 82 - 156

--------------------------------------------------------------------------------

82:   for (int i = 0; i < n; i++)

83:     res += a[i] * b[i];

[...]

155:   for (int i = 0; i < n; i++)

156:     res += a[i] * b[i];

/usr/include/c++/14/bits/new_allocator.h: 104 - 172

--------------------------------------------------------------------------------

104:       ~__new_allocator() _GLIBCXX_USE_NOEXCEPT { }

[...]

172: 	_GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n));

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 152 - 181

--------------------------------------------------------------------------------

152: void DiracDeterminantRef<DU_TYPE>::evaluateGL(ParticleSet& P,

153:                                               ParticleSet::ParticleGradient& G,

154:                                               ParticleSet::ParticleLaplacian& L,

155:                                               bool fromscratch)

156: {

157:   if (UpdateMode == ORB_PBYP_RATIO)

158:   { //need to compute dpsiM and d2psiM. Do not touch psiM!

159:     SPOVGLTimer->start();

160:     Phi->evaluate_notranspose(P, FirstIndex, LastIndex, psiM_temp, dpsiM, d2psiM);

161:     SPOVGLTimer->stop();

162:   }

163:

164:   if (NumPtcls == 1)

165:   {

166:     ValueType y = psiM(0, 0);

167:     GradType rv = y * dpsiM(0, 0);

168:     G[FirstIndex] += rv;

169:     L[FirstIndex] += y * d2psiM(0, 0) - dot(rv, rv);

170:   }

171:   else

172:   {

173:     for (size_t i = 0, iat = FirstIndex; i < NumPtcls; ++i, ++iat)

174:     {

175:       mValueType dot_temp = simd::dot(psiM[i], d2psiM[i], NumOrbitals);

176:       mGradType rv        = simd::dot(psiM[i], dpsiM[i], NumOrbitals);

177:       G[iat] += rv;

178:       L[iat] += dot_temp - dot(rv, rv);

179:     }

180:   }

181: }

0x4733c0 STP	X29, X30, [SP, #752]!

0x4733c4 ADD	X29, SP, #0

0x4733c8 ORR	X9, XZR, X0

0x4733cc LDR	W0, [X0, #12]

0x4733d0 STR	X1, [SP, #96]

0x4733d4 STP	X2, X3, [SP, #120]

0x4733d8 CBZ	W0, 473818

0x4733dc LDR	W14, [X9, #1156]

0x4733e0 LDR	W18, [X9, #1144]

0x4733e4 CMP	W14, #1

0x4733e8 B.EQ	473790

0x4733ec STP	X23, X24, [SP, #48]

0x4733f0 SBFM	X23, X14, #0, #31

0x4733f4 CBZ	W14, 473a00

0x4733f8 CNTW	X6, ALL

0x4733fc MOVZ	W30, #24

0x473400 PTRUE	P7.B, ALL

0x473404 LDP	X0, X1, [SP, #120]

0x473408 MOVZ	X17, #0

0x47340c MOVZ	X16, #0

0x473410 MOVZ	X10, #0

0x473414 CNTD	X7, ALL

0x473418 CNTB	X4, ALL, MUL #2

0x47341c STP	X19, X20, [SP, #16]

0x473420 STP	X21, X22, [SP, #32]

0x473424 STP	X25, X26, [SP, #64]

0x473428 ADD	W26, W6, #3

0x47342c STP	X27, X28, [SP, #80]

0x473430 MOVZ	W27, #96

0x473434 LDR	X20, [X9, #216]

0x473438 LDR	X25, [X9, #256]

0x47343c LDR	X19, [X9, #344]

0x473440 UBFM	X22, X20, #61, #60

0x473444 LDR	X24, [X9, #384]

0x473448 LDR	W14, [X9, #1152]

0x47344c UBFM	X21, X19, #61, #60

0x473450 LDR	X2, [X0, #24]

0x473454 ORR	X0, XZR, X25

0x473458 ORR	X15, XZR, X24

0x47345c LDR	X3, [X1, #24]

0x473460 UBFM	W11, W14, #2, #31

0x473464 AND	W12, W14, #0x3

0x473468 AND	W13, W14, #0xfffffffc

0x47346c SUB	W28, W14, #1

0x473470 SUB	W5, W14, W6

0x473474 SMADDL	X8, W18, W30, X2

0x473478 ADD	X18, X3, W18,SXTW #3

0x47347c STR	W11, [SP, #96]

0x473480 STR	W12, [SP, #104]

0x473484 STR	W13, [SP, #112]

(1105) 0x473488 CMP	W14, #0

(1105) 0x47348c B.LE	47375c

(1105) 0x473490 MOVZ	W30, #0

(1105) 0x473494 CMP	W28, W26

(1105) 0x473498 B.CC	473778

(1105) 0x47349c ORR	X2, XZR, X15

(1105) 0x4734a0 ORR	X1, XZR, X0

(1105) 0x4734a4 DUP	Z3.D, #0

(1105) 0x4734a8 ORR	Z1.D, Z3.D, Z3.D

  (1108) 0x4734ac ADD	W30, W30, W6

  (1108) 0x4734b0 LD1D	{Z2.D}, P7/Z, [X1, #1, MUL VL]

  (1108) 0x4734b4 LD1D	{Z22.D}, P7/Z, [X2, #1, MUL VL]

  (1108) 0x4734b8 LD1D	{Z21.D}, P7/Z, [X1, MUL VL]

  (1108) 0x4734bc LD1D	{Z20.D}, P7/Z, [X2, MUL VL]

  (1108) 0x4734c0 ADD	X1, X1, X4

  (1108) 0x4734c4 ADD	X2, X2, X4

  (1108) 0x4734c8 FMLA	Z3.D, P7/M, Z2.D, Z22.D

  (1108) 0x4734cc FMLA	Z1.D, P7/M, Z21.D, Z20.D

  (1108) 0x4734d0 CMP	W5, W30

  (1108) 0x4734d4 B.CS	4734ac

(1105) 0x4734d8 FADD	Z0.D, Z1.D, Z3.D

(1105) 0x4734dc CMP	W14, W30

(1105) 0x4734e0 B.EQ	47351c

(1105) 0x4734e4 ORR	W3, WZR, W30

(1105) 0x4734e8 SUB	W12, W14, W30

(1105) 0x4734ec WHILELO	P6.D, WZR, W12

(1105) 0x4734f0 ADD	X11, X16, X3

(1105) 0x4734f4 ADD	X13, X17, X3

(1105) 0x4734f8 ADD	X30, X25, X11,LSL #3

(1105) 0x4734fc MOVZ	X1, #0

(1105) 0x473500 ADD	X2, X24, X13,LSL #3

  (1106) 0x473504 LD1D	{Z19.D}, P6/Z, [X30, X1,LSL #3]

  (1106) 0x473508 LD1D	{Z18.D}, P6/Z, [X2, X1,LSL #3]

  (1106) 0x47350c ADD	X1, X1, X7

  (1106) 0x473510 FMLA	Z0.D, P6/M, Z19.D, Z18.D

  (1106) 0x473514 WHILELO	P6.D, W1, W12

  (1106) 0x473518 B.NE	473504

(1105) 0x47351c LDR	X3, [X9, #280]

(1105) 0x473520 FADDV	D27, P7, Z0.D

(1105) 0x473524 LDR	X13, [X9, #320]

(1105) 0x473528 MUL	X11, X10, X3

(1105) 0x47352c CMP	W28, #2

(1105) 0x473530 B.LS	473780

(1105) 0x473534 ADD	X12, X11, X11,LSL #1

(1105) 0x473538 LDR	W30, [SP, #96]

(1105) 0x47353c MOVI	V17.2D, #0

(1105) 0x473540 ORR	X3, XZR, X0

(1105) 0x473544 ADD	X1, X13, X12,LSL #3

(1105) 0x473548 UBFM	X2, X12, #61, #60

(1105) 0x47354c ORR	V16.16B, V17.16B, V17.16B

(1105) 0x473550 ORR	V7.16B, V17.16B, V17.16B

(1105) 0x473554 UMADDL	X12, W30, W27, X1

(1105) 0x473558 ORR	V6.16B, V17.16B, V17.16B

(1105) 0x47355c ORR	V5.16B, V17.16B, V17.16B

(1105) 0x473560 ORR	V4.16B, V17.16B, V17.16B

(1105) 0x473564 SUB	X30, X12, X1

(1105) 0x473568 TBZ	W30, #5, 4735a8

(1105) 0x47356c LDP	Q25, Q23, [X0]

(1105) 0x473570 ADD	X3, X0, #32

(1105) 0x473574 LDP	Q31, Q30, [X1, #16]

(1105) 0x473578 LDP	Q29, Q28, [X1, #48]

(1105) 0x47357c ADD	X1, X1, #96

(1105) 0x473580 LDUR	Q26, [X1, #496]

(1105) 0x473584 LDR	Q24, [X13, X2]

(1105) 0x473588 FMLA	V5.2D, V31.2D, V25.2D

(1105) 0x47358c FMLA	V4.2D, V24.2D, V25.D[0]

(1105) 0x473590 FMLA	V6.2D, V30.2D, V25.D[1]

(1105) 0x473594 FMLA	V7.2D, V29.2D, V23.D[0]

(1105) 0x473598 FMLA	V16.2D, V28.2D, V23.2D

(1105) 0x47359c FMLA	V17.2D, V26.2D, V23.D[1]

(1105) 0x4735a0 CMP	X12, X1

(1105) 0x4735a4 B.EQ	47361c

  (1107) 0x4735a8 ORR	X2, XZR, X1

  (1107) 0x4735ac LDP	Q18, Q24, [X3]

  (1107) 0x4735b0 ORR	X30, XZR, X3

  (1107) 0x4735b4 ADD	X3, X3, #64

  (1107) 0x4735b8 LDR	Q0, [X2], #96

  (1107) 0x4735bc LDP	Q1, Q22, [X1, #16]

  (1107) 0x4735c0 LDP	Q3, Q2, [X1, #48]

  (1107) 0x4735c4 ADD	X1, X1, #192

  (1107) 0x4735c8 LDUR	Q21, [X1, #400]

  (1107) 0x4735cc FMLA	V4.2D, V0.2D, V18.D[0]

  (1107) 0x4735d0 LDP	Q20, Q19, [X2, #48]

  (1107) 0x4735d4 LDP	Q31, Q30, [X2, #16]

  (1107) 0x4735d8 FMLA	V5.2D, V1.2D, V18.2D

  (1107) 0x4735dc LDUR	Q23, [X1, #416]

  (1107) 0x4735e0 LDUR	Q25, [X3, #480]

  (1107) 0x4735e4 FMLA	V6.2D, V22.2D, V18.D[1]

  (1107) 0x4735e8 LDR	Q28, [X30, #48]

  (1107) 0x4735ec FMLA	V7.2D, V3.2D, V24.D[0]

  (1107) 0x4735f0 LDR	Q29, [X2, #80]

  (1107) 0x4735f4 FMLA	V16.2D, V2.2D, V24.2D

  (1107) 0x4735f8 FMLA	V17.2D, V21.2D, V24.D[1]

  (1107) 0x4735fc FMLA	V4.2D, V23.2D, V25.D[0]

  (1107) 0x473600 FMLA	V5.2D, V31.2D, V25.2D

  (1107) 0x473604 FMLA	V6.2D, V30.2D, V25.D[1]

  (1107) 0x473608 FMLA	V7.2D, V20.2D, V28.D[0]

  (1107) 0x47360c FMLA	V16.2D, V19.2D, V28.2D

  (1107) 0x473610 FMLA	V17.2D, V29.2D, V28.D[1]

  (1107) 0x473614 CMP	X12, X1

  (1107) 0x473618 B.NE	4735a8

(1105) 0x47361c EXT	V26.16B, V16.16B, V17.16B, #8

(1105) 0x473620 LDR	W12, [SP, #104]

(1105) 0x473624 EXT	V0.16B, V5.16B, V6.16B, #8

(1105) 0x473628 MOV	D17, V17.D[1]

(1105) 0x47362c MOV	D6, V6.D[1]

(1105) 0x473630 FADD	V4.2D, V7.2D, V4.2D

(1105) 0x473634 FADD	D5, D5, D16

(1105) 0x473638 FADD	V7.2D, V26.2D, V0.2D

(1105) 0x47363c FADD	D16, D17, D6

(1105) 0x473640 FADD	V31.2D, V7.2D, V4.2D

(1105) 0x473644 FADD	D26, D5, D16

(1105) 0x473648 CBZ	W12, 4736e0

(1105) 0x47364c LDR	W30, [SP, #112]

(1105) 0x473650 ADD	X3, X11, W30,SXTW

(1105) 0x473654 ADD	X1, X3, X3,LSL #1

(1105) 0x473658 ORR	W2, WZR, W30

(1105) 0x47365c UBFM	X3, X2, #61, #60

(1105) 0x473660 ADD	W2, W30, #1

(1105) 0x473664 ADD	X12, X13, X1,LSL #3

(1105) 0x473668 UBFM	X1, X1, #61, #60

(1105) 0x47366c LDR	D1, [X0, X3]

(1105) 0x473670 LDR	Q22, [X13, X1]

(1105) 0x473674 LDR	D3, [X12, #16]

(1105) 0x473678 FMLA	V31.2D, V22.2D, V1.D[0]

(1105) 0x47367c FMADD	D26, D3, D1, D26

(1105) 0x473680 CMP	W14, W2

(1105) 0x473684 B.LE	4736e0

(1105) 0x473688 ADD	X12, X11, W2,SXTW

(1105) 0x47368c ADD	X2, X12, X12,LSL #1

(1105) 0x473690 ADD	X3, X0, X3

(1105) 0x473694 ADD	W30, W30, #2

(1105) 0x473698 ADD	X1, X13, X2,LSL #3

(1105) 0x47369c UBFM	X12, X2, #61, #60

(1105) 0x4736a0 LDR	D21, [X3, #8]

(1105) 0x4736a4 LDR	Q2, [X13, X12]

(1105) 0x4736a8 LDR	D20, [X1, #16]

(1105) 0x4736ac FMLA	V31.2D, V2.2D, V21.D[0]

(1105) 0x4736b0 FMADD	D26, D21, D20, D26

(1105) 0x4736b4 CMP	W14, W30

(1105) 0x4736b8 B.LE	4736e0

(1105) 0x4736bc ADD	X11, X11, W30,SXTW

(1105) 0x4736c0 ADD	X30, X11, X11,LSL #1

(1105) 0x4736c4 LDR	D24, [X3, #16]

(1105) 0x4736c8 ADD	X2, X13, X30,LSL #3

(1105) 0x4736cc UBFM	X1, X30, #61, #60

(1105) 0x4736d0 LDR	Q19, [X13, X1]

(1105) 0x4736d4 LDR	D18, [X2, #16]

(1105) 0x4736d8 FMLA	V31.2D, V19.2D, V24.D[0]

(1105) 0x4736dc FMADD	D26, D18, D24, D26

(1105) 0x4736e0 MOV	D23, V31.D[1]

(1105) 0x4736e4 FMUL	D28, D26, D26

(1105) 0x4736e8 FMUL	D30, D31, D31

(1105) 0x4736ec FMUL	D29, D23, D23

(1105) 0x4736f0 LDR	D25, [X8, #16]

(1105) 0x4736f4 FADD	D30, D29, D30

(1105) 0x4736f8 ADD	X0, X0, X22

(1105) 0x4736fc ADD	X15, X15, X21

(1105) 0x473700 ADD	X16, X16, X20

(1105) 0x473704 LDR	Q29, [X8]

(1105) 0x473708 ADD	X17, X17, X19

(1105) 0x47370c ADD	X8, X8, #24

(1105) 0x473710 FADD	D26, D25, D26

(1105) 0x473714 FADD	V31.2D, V29.2D, V31.2D

(1105) 0x473718 STUR	D26, [X8, #504]

(1105) 0x47371c STUR	Q31, [X8, #488]

(1105) 0x473720 LDR	D0, [X18, X10,LSL #3]

(1105) 0x473724 FADD	D27, D27, D0

(1105) 0x473728 FSUB	D28, D27, S28

(1105) 0x47372c FSUB	D17, D28, S30

(1105) 0x473730 STR	D17, [X18, X10,LSL #3]

(1105) 0x473734 ADD	X10, X10, #1

(1105) 0x473738 CMP	X23, X10

(1105) 0x47373c B.NE	473488

0x473740 LDP	X19, X20, [SP, #16]

0x473744 LDP	X21, X22, [SP, #32]

0x473748 LDP	X23, X24, [SP, #48]

0x47374c LDP	X25, X26, [SP, #64]

0x473750 LDP	X27, X28, [SP, #80]

0x473754 LDP	X29, X30, [SP], #272

0x473758 RET

(1105) 0x47375c MOVI	V31.2D, #0

(1105) 0x473760 FMOV	D30, D31

(1105) 0x473764 FMOV	D29, D31

(1105) 0x473768 FMOV	D28, D31

(1105) 0x47376c FMOV	D27, D31

(1105) 0x473770 FMOV	D26, D31

(1105) 0x473774 B	4736f0

(1105) 0x473778 DUP	Z0.D, #0

(1105) 0x47377c B	4734e4

(1105) 0x473780 MOVI	V31.2D, #0

(1105) 0x473784 MOVZ	W30, #0

(1105) 0x473788 FMOV	D26, D31

(1105) 0x47378c B	473650

0x473790 MOVZ	W6, #24

0x473794 LDR	X5, [X9, #256]

0x473798 SBFM	X7, X18, #61, #31

0x47379c LDP	X4, X13, [SP, #120]

0x4737a0 SMULL	X14, W18, W6

0x4737a4 LDR	X18, [X9, #320]

0x4737a8 LDR	D7, [X5]

0x4737ac LDR	X12, [X4, #24]

0x4737b0 LDP	D6, D4, [X18]

0x4737b4 LDR	D5, [X18, #16]

0x4737b8 ADD	X3, X12, X14

0x4737bc LDR	X11, [X13, #24]

0x4737c0 FMUL	D16, D7, D6

0x4737c4 FMUL	D1, D7, D4

0x4737c8 LDR	X9, [X9, #384]

0x4737cc FMUL	D22, D7, D5

0x4737d0 STP	D16, D1, [SP, #224]

0x4737d4 FMUL	D3, D1, D1

0x4737d8 LDR	Q2, [X12, X14]

0x4737dc LDR	Q20, [SP, #224]

0x4737e0 FMADD	D21, D16, D16, D3

0x4737e4 FADD	V19.2D, V2.2D, V20.2D

0x4737e8 STR	Q19, [X12, X14]

0x4737ec LDR	D18, [X3, #16]

0x4737f0 FADD	D24, D18, D22

0x4737f4 STR	D24, [X3, #16]

0x4737f8 LDR	D23, [X11, X7]

0x4737fc LDR	D30, [X9]

0x473800 FMADD	D29, D7, D30, D23

0x473804 FMSUB	D25, D22, D22, D29

0x473808 FSUB	D31, D25, S21

0x47380c STR	D31, [X11, X7]

0x473810 LDP	X29, X30, [SP], #272

0x473814 RET

0x473818 STP	X21, X22, [SP, #32]

0x47381c LDR	X0, [X9, #1128]

0x473820 STR	X9, [SP, #104]

0x473824 BL	4cf640

0x473828 LDR	X9, [SP, #104]

0x47382c ADRP	X1,

0x473830 ADD	X4, X1, #672

0x473834 LDR	X21, [X9, #1136]

0x473838 LDR	W2, [X9, #1144]

0x47383c LDR	W3, [X9, #1148]

0x473840 LDR	X5, [X21]

0x473844 STR	W2, [SP, #104]

0x473848 LDR	X7, [X5, #40]

0x47384c CMP	X7, X4

0x473850 B.NE	4739d8

0x473854 CMP	W2, W3

0x473858 B.GE	473974

0x47385c STP	X19, X20, [SP, #16]

0x473860 ADRP	X19,

0x473864 ADRP	X20,

0x473868 SUB	W3, W3, W2

0x47386c MOVZ	X22, #0

0x473870 ADD	X19, X19, #552

0x473874 ADD	X20, X20, #3104

0x473878 STP	X23, X24, [SP, #48]

0x47387c ADD	X24, X9, #360

0x473880 ADD	X23, X9, #336

0x473884 STP	X25, X26, [SP, #64]

0x473888 ADD	X26, X9, #296

0x47388c ADD	X25, X9, #272

0x473890 STP	X27, X28, [SP, #80]

0x473894 ADD	X28, X9, #168

0x473898 ADD	X27, X9, #144

0x47389c STR	X3, [SP, #112]

0x4738a0 STR	X9, [SP, #136]

(1109) 0x4738a4 LDR	X13, [X25, #8]

(1109) 0x4738a8 ADD	X5, SP, #224

(1109) 0x4738ac ADD	X4, SP, #184

(1109) 0x4738b0 STR	X19, [SP, #144]

(1109) 0x4738b4 ADD	X3, SP, #144

(1109) 0x4738b8 LDR	X8, [X23, #8]

(1109) 0x4738bc STR	X20, [SP, #184]

(1109) 0x4738c0 LDR	X30, [X27, #8]

(1109) 0x4738c4 MUL	X14, X22, X13

(1109) 0x4738c8 LDR	X1, [X28, #24]

(1109) 0x4738cc MUL	X11, X22, X8

(1109) 0x4738d0 LDR	X10, [X24, #24]

(1109) 0x4738d4 ADD	X15, X14, X14,LSL #1

(1109) 0x4738d8 MUL	X0, X22, X30

(1109) 0x4738dc LDR	X16, [X26, #24]

(1109) 0x4738e0 LDRSW	X18, [X21, #8]

(1109) 0x4738e4 ADD	X7, X1, X0,LSL #3

(1109) 0x4738e8 ORR	X0, XZR, X21

(1109) 0x4738ec STR	X19, [SP, #224]

(1109) 0x4738f0 ADD	X12, X10, X11,LSL #3

(1109) 0x4738f4 LDR	X9, [X21]

(1109) 0x4738f8 ADD	X17, X16, X15,LSL #3

(1109) 0x4738fc STR	XZR, [SP, #160]

(1109) 0x473900 LDR	W6, [SP, #104]

(1109) 0x473904 STR	X18, [SP, #152]

(1109) 0x473908 LDR	X1, [SP, #96]

(1109) 0x47390c STR	X7, [SP, #168]

(1109) 0x473910 STP	X18, XZR, [SP, #192]

(1109) 0x473914 ADD	W2, W6, W22

(1109) 0x473918 LDR	X6, [X9, #24]

(1109) 0x47391c STR	X17, [SP, #208]

(1109) 0x473920 STP	X18, XZR, [SP, #232]

(1109) 0x473924 STR	X12, [SP, #248]

(1109) 0x473928 BLR	X6

(1109) 0x47392c LDR	X3, [SP, #240]

(1109) 0x473930 STR	X19, [SP, #224]

(1109) 0x473934 CBNZ	X3, 4739c8

(1109) 0x473938 LDR	X8, [SP, #200]

(1109) 0x47393c STR	X20, [SP, #184]

(1109) 0x473940 CBNZ	X8, 47398c

(1109) 0x473944 LDR	X10, [SP, #160]

(1109) 0x473948 STR	X19, [SP, #144]

(1109) 0x47394c CBNZ	X10, 4739a8

(1109) 0x473950 LDR	X12, [SP, #112]

(1109) 0x473954 ADD	X22, X22, #1

(1109) 0x473958 CMP	X22, X12

(1109) 0x47395c B.NE	4738a4

0x473960 LDR	X9, [SP, #136]

0x473964 LDP	X19, X20, [SP, #16]

0x473968 LDP	X23, X24, [SP, #48]

0x47396c LDP	X25, X26, [SP, #64]

0x473970 LDP	X27, X28, [SP, #80]

0x473974 STR	X9, [SP, #96]

0x473978 LDR	X0, [X9, #1128]

0x47397c BL	4cf8e0

0x473980 LDR	X9, [SP, #96]

0x473984 LDP	X21, X22, [SP, #32]

0x473988 B	4733dc

(1109) 0x47398c ADD	X11, X8, X8,LSL #1

(1109) 0x473990 LDR	X0, [SP, #208]

(1109) 0x473994 UBFM	X1, X11, #61, #60

(1109) 0x473998 BL	4100d0

(1109) 0x47399c LDR	X10, [SP, #160]

(1109) 0x4739a0 STR	X19, [SP, #144]

(1109) 0x4739a4 CBZ	X10, 473950

(1109) 0x4739a8 LDR	X0, [SP, #168]

(1109) 0x4739ac UBFM	X1, X10, #61, #60

(1109) 0x4739b0 ADD	X22, X22, #1

(1109) 0x4739b4 BL	4100d0

(1109) 0x4739b8 LDR	X13, [SP, #112]

(1109) 0x4739bc CMP	X13, X22

(1109) 0x4739c0 B.NE	4738a4

0x4739c4 B	473960

(1109) 0x4739c8 LDR	X0, [SP, #248]

(1109) 0x4739cc UBFM	X1, X3, #61, #60

(1109) 0x4739d0 BL	4100d0

(1109) 0x4739d4 B	473938

0x4739d8 LDR	X1, [SP, #96]

0x4739dc ADD	X6, X9, #336

0x4739e0 ADD	X5, X9, #272

0x4739e4 ADD	X4, X9, #144

0x4739e8 ORR	X0, XZR, X21

0x4739ec STR	X9, [SP, #96]

0x4739f0 LDR	W2, [SP, #104]

0x4739f4 BLR	X7

0x4739f8 LDR	X9, [SP, #96]

0x4739fc B	473974

0x473a00 LDP	X23, X24, [SP, #48]

0x473a04 B	473754

0x473a08 LDR	X4, [SP, #240]

0x473a0c ORR	X22, XZR, X0

0x473a10 STR	X19, [SP, #224]

0x473a14 CBZ	X4, 473a24

0x473a18 LDR	X0, [SP, #248]

0x473a1c UBFM	X1, X4, #61, #60

0x473a20 BL	4100d0

0x473a24 LDR	X21, [SP, #200]

0x473a28 STR	X20, [SP, #184]

0x473a2c CBZ	X21, 473a40

0x473a30 MOVZ	X2, #24

0x473a34 LDR	X0, [SP, #208]

0x473a38 MUL	X1, X21, X2

0x473a3c BL	4100d0

0x473a40 LDR	X5, [SP, #160]

0x473a44 STR	X19, [SP, #144]

0x473a48 CBZ	X5, 473a58

0x473a4c LDR	X0, [SP, #168]

0x473a50 UBFM	X1, X5, #61, #60

0x473a54 BL	4100d0

0x473a58 ORR	X0, XZR, X22

0x473a5c BL	4104a0

Coverage (%)	Name	Source Location	Module
►49.82+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:250	exec
○	main._omp_fn.1	stl_vector.h:1131	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►48.41+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:249	exec
○	main._omp_fn.1	stl_vector.h:1131	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	DiracDeterminantRef.cpp:152-181
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:61-63,94
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h:110,129-131
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:56,144,210,221-223,248
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:106-111
/usr/include/c++/14/bits/unique_ptr.h:193
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155-156
/usr/include/c++/14/bits/new_allocator.h:104,172
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:152-181

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.83 to 6.33 cycles (4.55x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 32% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 28.83 to 17.00 cycles (1.70x speedup).

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

11% of VPU loads are used in vector version.
6% of VPU stores are used in vector version.
5% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:159
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:161
unknown: 5 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:160
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:104

Matching between your function (in the source code) and the binary function

The binary function is composed of 14 FP arithmetical operations:

7: addition or subtraction (3 inside FMA instructions)
7: multiply (3 inside FMA instructions)

The binary function is loading 21 bytes. The binary function is storing 12 bytes.

Arithmetic intensity

Arithmetic intensity is 0.42 FP operations per loaded or stored byte.

General properties

nb instructions	172
nb uops	172
loop length	688
used w registers	14
used x registers	32
used b registers	0
used h registers	0
used s registers	2
used d registers	16
used q registers	3
used v registers	3
used z registers	0
nb stack references	54
ADD-SUB / MUL ratio	0.75

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.50 cycles
front end	21.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.50	10.50	15.75	15.75	15.75	15.75	3.50	3.50	3.50	3.50	28.83	28.50	28.67	12.50	12.50
cycles	10.50	10.50	15.75	15.75	15.75	15.75	3.50	3.50	3.50	3.50	28.83	28.50	28.67	12.50	12.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.50
Dispatch	28.83
Overall L1	28.83

Vectorization ratios

INT

all	5%
load	11%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	33%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	11%
store	6%
mul	0%
add-sub	5%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	32%
load	37%
store	35%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	12%
other	30%

all	27%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	33%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	32%
load	37%
store	35%
mul	25%
add-sub	25%
fma	21%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.83 cycles. At this rate:

0% of peak load performance is reached (0.73 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.42 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4733c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #752]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X9, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W0, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X2, X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ W0, 473818 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x458>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W14, [X9, #1156]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W18, [X9, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 473790 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SBFM X23, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
CBZ W14, 473a00 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTW X6, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W30, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDP X0, X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X7, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CNTB X4, ALL, MUL #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W26, W6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W27, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X20, [X9, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X25, [X9, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X19, [X9, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X22, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X24, [X9, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W14, [X9, #1152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X2, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X15, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X3, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM W11, W14, #2, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W12, W14, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W13, W14, #0xfffffffc	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W28, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W5, W14, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SMADDL X8, W18, W30, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD X18, X3, W18,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR W11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W12, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W13, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #272	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W6, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X5, [X9, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X7, X18, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X4, X13, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
SMULL X14, W18, W6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X18, [X9, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D7, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X12, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP D6, D4, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR D5, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X3, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X13, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D16, D7, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMUL D1, D7, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR X9, [X9, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D22, D7, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STP D16, D1, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
FMUL D3, D1, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR Q2, [X12, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q20, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMADD D21, D16, D16, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FADD V19.2D, V2.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STR Q19, [X12, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR D18, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D24, D18, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D24, [X3, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D23, [X11, X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D30, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D29, D7, D30, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMSUB D25, D22, D22, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FSUB D31, D25, S21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D31, [X11, X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP X29, X30, [SP], #272	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X9, #1128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4cf640 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X1, <20045d82c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X1, #672	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X21, [X9, #1136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [X9, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W3, [X9, #1148]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X7, [X5, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4739d8 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x618>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W2, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 473974 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x5b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X19, <543860>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X20, <542864>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB W3, W3, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X19, #552	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X20, X20, #3104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X24, X9, #360	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X23, X9, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X26, X9, #296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X25, X9, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X28, X9, #168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X27, X9, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X9, #1128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4cf8e0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B 4733dc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 473960 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X9, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X9, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X9, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
BLR X7	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 473974 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x5b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 473754 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X4, 473a24 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x664>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X1, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X21, 473a40 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x680>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X2, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X1, X21, X2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X5, 473a58 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x698>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X1, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4104a0 <@plt_start@+0x480>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	DiracDeterminantRef.cpp:152-181
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:61-63,94
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h:110,129-131
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:56,144,210,221-223,248
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:106-111
/usr/include/c++/14/bits/unique_ptr.h:193
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155-156
/usr/include/c++/14/bits/new_allocator.h:104,172
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:152-181

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.83 to 6.33 cycles (4.55x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

11% of VPU loads are used in vector version.
6% of VPU stores are used in vector version.
5% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:159
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:161
unknown: 5 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:160
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:104

Matching between your function (in the source code) and the binary function

The binary function is composed of 14 FP arithmetical operations:

7: addition or subtraction (3 inside FMA instructions)
7: multiply (3 inside FMA instructions)

The binary function is loading 21 bytes. The binary function is storing 12 bytes.

Arithmetic intensity

Arithmetic intensity is 0.42 FP operations per loaded or stored byte.

General properties

nb instructions	172
nb uops	172
loop length	688
used w registers	14
used x registers	32
used b registers	0
used h registers	0
used s registers	2
used d registers	16
used q registers	3
used v registers	3
used z registers	0
nb stack references	54
ADD-SUB / MUL ratio	0.75

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.50 cycles
front end	21.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.50	10.50	15.75	15.75	15.75	15.75	3.50	3.50	3.50	3.50	28.83	28.50	28.67	12.50	12.50
cycles	10.50	10.50	15.75	15.75	15.75	15.75	3.50	3.50	3.50	3.50	28.83	28.50	28.67	12.50	12.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.50
Dispatch	28.83
Overall L1	28.83

Vectorization ratios

INT

all	5%
load	11%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	33%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	11%
store	6%
mul	0%
add-sub	5%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	32%
load	37%
store	35%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	12%
other	30%

all	27%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	33%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	32%
load	37%
store	35%
mul	25%
add-sub	25%
fma	21%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.83 cycles. At this rate:

0% of peak load performance is reached (0.73 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.42 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4733c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #752]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X9, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W0, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X2, X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ W0, 473818 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x458>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W14, [X9, #1156]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W18, [X9, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 473790 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SBFM X23, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
CBZ W14, 473a00 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTW X6, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W30, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDP X0, X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X7, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CNTB X4, ALL, MUL #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W26, W6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W27, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X20, [X9, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X25, [X9, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X19, [X9, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X22, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X24, [X9, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W14, [X9, #1152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X2, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X15, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X3, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM W11, W14, #2, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W12, W14, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W13, W14, #0xfffffffc	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W28, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W5, W14, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SMADDL X8, W18, W30, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD X18, X3, W18,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR W11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W12, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W13, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #272	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W6, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X5, [X9, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X7, X18, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X4, X13, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
SMULL X14, W18, W6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X18, [X9, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D7, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X12, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP D6, D4, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR D5, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X3, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X13, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D16, D7, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMUL D1, D7, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR X9, [X9, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D22, D7, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STP D16, D1, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
FMUL D3, D1, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR Q2, [X12, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q20, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMADD D21, D16, D16, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FADD V19.2D, V2.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STR Q19, [X12, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR D18, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D24, D18, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D24, [X3, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D23, [X11, X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D30, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D29, D7, D30, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMSUB D25, D22, D22, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FSUB D31, D25, S21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D31, [X11, X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP X29, X30, [SP], #272	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X9, #1128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4cf640 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X1, <20045d82c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X1, #672	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X21, [X9, #1136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [X9, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W3, [X9, #1148]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X7, [X5, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4739d8 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x618>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W2, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 473974 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x5b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X19, <543860>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X20, <542864>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB W3, W3, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X19, #552	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X20, X20, #3104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X24, X9, #360	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X23, X9, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X26, X9, #296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X25, X9, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X28, X9, #168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X27, X9, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X9, #1128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4cf8e0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B 4733dc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 473960 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X9, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X9, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X9, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
BLR X7	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 473974 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x5b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 473754 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X4, 473a24 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x664>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X1, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X21, 473a40 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x680>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X2, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X1, X21, X2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X5, 473a58 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x698>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X1, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4104a0 <@plt_start@+0x480>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus:...–	0.54	0.83
▼Loop 1105 - DiracDeterminantRef.cpp:173-178 - exec–	0.00	0.02
○Loop 1107 - inner_product.hpp:155-155 - exec	0.34	0.52
○Loop 1108 - inner_product.hpp:82-83 - exec	0.20	0.30
○Loop 1106 - inner_product.hpp:82-83 - exec	0.00	0.00
○Loop 1109 - SPOSet.h:106-111 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

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Cycles and memory resources usage

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