OV - exec - Loop 1126

	Loop Id: 1126	Module: exec	Source: inner_product.hpp:211-212	Coverage: 0.06%

0x474074 ADD	X3, X0, X1,LSL #1

0x474078 LDR	D28, [X0]    [1]

0x47407c ADD	X2, X0, X1

0x474080 ORR	X5, XZR, X17

0x474084 ADD	X17, X17, #64

0x474088 ADD	X12, X3, X1,LSL #1

0x47408c LDR	D29, [X0, X1]    [1]

0x474090 ADD	X10, X3, X1

0x474094 ADD	X8, X12, X1,LSL #1

0x474098 ADD	X11, X12, X1

0x47409c LDR	D30, [X2, X1]    [8]

0x4740a0 LDR	D6, [X11, X1]    [5]

0x4740a4 ADD	X0, X8, X1,LSL #1

0x4740a8 STR	D28, [X5], #8    [2]

0x4740ac LDR	D7, [X8, X1]    [3]

0x4740b0 STUR	D29, [X17, #456]    [7]

0x4740b4 LDR	D15, [X12, X1]    [6]

0x4740b8 STR	D30, [X5, #8]    [2]

0x4740bc LDR	D16, [X10, X1]    [4]

0x4740c0 STP	D6, D7, [X17, #1008]    [7]

0x4740c4 STP	D16, D15, [X17, #992]    [7]

0x4740c8 LDR	D17, [X3, X1]    [9]

0x4740cc STUR	D17, [X17, #472]    [7]

0x4740d0 CMP	X17, X4

0x4740d4 B.NE	474074

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 211 - 212

--------------------------------------------------------------------------------

211:     for (size_t j = 0; j < m; ++j)

212:       B[i * ldb + j] = A[j * lda + i];

Coverage (%)	Name	Source Location	Module
►50.68+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main._omp_fn.0	miniqmc.cpp:397	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►47.68+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main._omp_fn.0	miniqmc.cpp:397	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.49
Bottlenecks	P10, P11, P12,
Function	miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&)
Source	inner_product.hpp:211-212
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.67
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	1.33
Front-end cycles	3.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	4.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	14.29
Vectorization ratio load	0.00
Vectorization ratio store	33.33
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	28.57
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	33.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.49
Bottlenecks	P10, P11, P12,
Function	miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&)
Source	inner_product.hpp:211-212
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.67
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	1.33
Front-end cycles	3.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	4.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	14.29
Vectorization ratio load	0.00
Vectorization ratio store	33.33
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	28.57
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	33.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&)
Source file and lines	inner_product.hpp:211-212
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:211-212.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 4.67 to 1.33 cycles (3.50x speedup).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	25
nb uops	25
loop length	100
used w registers	0
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	8
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.13 cycles
front end	3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.50	2.50	2.50	2.50	3.00	3.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00
cycles	0.50	0.50	2.50	2.50	2.50	2.50	3.00	3.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	3.13
Dispatch	4.67
Data deps.	4.00
Overall L1	4.67

Vectorization ratios

all	14%
load	0%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	28%
load	25%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.67 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 474074

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
ADD X3, X0, X1,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D28, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X2, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X5, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X17, X17, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X12, X3, X1,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D29, [X0, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X10, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X8, X12, X1,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X11, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D30, [X2, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D6, [X11, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X0, X8, X1,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR D28, [X5], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D7, [X8, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STUR D29, [X17, #456]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D15, [X12, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D30, [X5, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D16, [X10, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STP D6, D7, [X17, #1008]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STP D16, D15, [X17, #992]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
LDR D17, [X3, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STUR D17, [X17, #472]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
CMP X17, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 474074 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&)
Source file and lines	inner_product.hpp:211-212
Module	exec

gain
potential
hint
expert

Vectorization

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	25
nb uops	25
loop length	100
used w registers	0
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	8
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.13 cycles
front end	3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.50	2.50	2.50	2.50	3.00	3.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00
cycles	0.50	0.50	2.50	2.50	2.50	2.50	3.00	3.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	3.13
Dispatch	4.67
Data deps.	4.00
Overall L1	4.67

Vectorization ratios

all	14%
load	0%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	28%
load	25%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.67 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 474074

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
ADD X3, X0, X1,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D28, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X2, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X5, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X17, X17, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X12, X3, X1,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D29, [X0, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X10, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X8, X12, X1,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X11, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D30, [X2, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D6, [X11, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X0, X8, X1,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR D28, [X5], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D7, [X8, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STUR D29, [X17, #456]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D15, [X12, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D30, [X5, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D16, [X10, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STP D6, D7, [X17, #1008]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STP D16, D15, [X17, #992]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
LDR D17, [X3, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STUR D17, [X17, #472]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
CMP X17, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 474074 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code