OV - exec - Loop 234

	Loop Id: 234	Module: exec	Source: BsplineFunctor.h:305-336 [...]	Coverage: 0.03%

0x426860 PUNPKLO	P5.H, P4.B

0x426864 PUNPKHI	P6.H, P4.B

0x426868 LD1D	{Z27.D}, P5/Z, [X11, X5,LSL #3]    [20]

0x42686c LD1D	{Z24.D}, P6/Z, [X13, X5,LSL #3]    [22]

0x426870 FMUL	Z15.D, Z27.D, Z19.D

0x426874 FMUL	Z31.D, Z24.D, Z19.D

0x426878 MOVPRFX	Z17, Z15

0x42687c FCVTZS	Z17.S, P7/M, Z15.D

0x426880 MOVPRFX	Z18, Z31

0x426884 FCVTZS	Z18.S, P7/M, Z31.D

0x426888 MOVPRFX	Z20, Z15

0x42688c FRINTZ	Z20.D, P7/M, Z15.D

0x426890 UZP1	Z21.S, Z17.S, Z18.S

0x426894 FSUB	Z30.D, Z15.D, Z20.D

0x426898 MOVPRFX	Z22, Z21

0x42689c ADD	Z22.S, Z22.S, #1

0x4268a0 MOVPRFX	Z28, Z3

0x4268a4 FMLA	Z28.D, P7/M, Z30.D, Z2.D

0x4268a8 SUNPKLO	Z25.D, Z22

0x4268ac LD1D	{Z13.D}, P5/Z, [X4, Z25.D,LSL #3]    [41]

0x4268b0 FMUL	Z12.D, Z13.D, Z28.D

0x4268b4 MOVPRFX	Z26, Z21

0x4268b8 ADD	Z26.S, Z26.S, #3

0x4268bc SUNPKHI	Z23.D, Z22

0x4268c0 SUNPKLO	Z16.D, Z21

0x4268c4 SUNPKLO	Z22.D, Z26

0x4268c8 LD1D	{Z14.D}, P5/Z, [X4, Z16.D,LSL #3]    [41]

0x4268cc MOVPRFX	Z28, Z21

0x4268d0 ADD	Z28.S, Z28.S, #2

0x4268d4 MOVPRFX	Z29, Z1

0x4268d8 FMLA	Z29.D, P7/M, Z30.D, Z0.D

0x4268dc SUNPKHI	Z26.D, Z26

0x4268e0 FMAD	Z29.D, P7/M, Z14.D, Z12.D

0x4268e4 SUNPKHI	Z12.D, Z21

0x4268e8 SUNPKLO	Z21.D, Z28

0x4268ec LD1D	{Z15.D}, P5/Z, [X4, Z22.D,LSL #3]    [41]

0x4268f0 ADDVL	X30, SP, #21

0x4268f4 LD1D	{Z22.D}, P6/Z, [X4, Z26.D,LSL #3]    [41]

0x4268f8 LD1D	{Z26.D}, P5/Z, [X4, Z21.D,LSL #3]    [41]

0x4268fc MOVPRFX	Z21, Z31

0x426900 FRINTZ	Z21.D, P7/M, Z31.D

0x426904 LD1D	{Z17.D}, P6/Z, [X4, Z23.D,LSL #3]    [41]

0x426908 FSUB	Z31.D, Z31.D, Z21.D

0x42690c SUNPKHI	Z16.D, Z28

0x426910 MOVPRFX	Z21, Z3

0x426914 FMLA	Z21.D, P7/M, Z31.D, Z2.D

0x426918 ADD	X30, X30, #176

0x42691c LDR	Z20, [X30, MUL VL]    [28]

0x426920 MOVPRFX	Z25, Z5

0x426924 FMLA	Z25.D, P7/M, Z30.D, Z4.D

0x426928 ORR	Z18.D, Z20.D, Z20.D

0x42692c ADDVL	X8, SP, #24

0x426930 FMLA	Z18.D, P7/M, Z30.D, Z6.D

0x426934 FMLA	Z20.D, P7/M, Z31.D, Z6.D

0x426938 FMUL	Z23.D, Z15.D, Z18.D

0x42693c FMAD	Z25.D, P7/M, Z26.D, Z23.D

0x426940 FADD	Z29.D, Z29.D, Z25.D

0x426944 LD1D	{Z18.D}, P6/Z, [X4, Z12.D,LSL #3]    [41]

0x426948 LD1D	{Z23.D}, P6/Z, [X4, Z16.D,LSL #3]    [41]

0x42694c LD1W	{Z25.S}, P4/Z, [X12, X5,LSL #2]    [21]

0x426950 ADD	X8, X8, #176

0x426954 LDR	Z12, [X8, MUL VL]    [37]

0x426958 SUNPKLO	Z16.D, Z25

0x42695c FMUL	Z28.D, Z29.D, Z12.D

0x426960 ADDVL	X17, SP, #10

0x426964 ST1D	{Z28.D}, P5, [X10, Z16.D,LSL #3]    [18]

0x426968 FMUL	Z29.D, Z22.D, Z20.D

0x42696c FMUL	Z20.D, Z17.D, Z21.D

0x426970 FDUP	Z21.D, #112

0x426974 SUNPKHI	Z25.D, Z25

0x426978 ADD	X17, X17, #176

0x42697c ADD	X30, SP, #176

0x426980 MOVPRFX	Z28, Z5

0x426984 FMLA	Z28.D, P7/M, Z31.D, Z4.D

0x426988 FDIVR	Z27.D, P7/M, Z27.D, Z21.D

0x42698c FMAD	Z28.D, P7/M, Z23.D, Z29.D

0x426990 ADDVL	X16, SP, #11

0x426994 MOVPRFX	Z29, Z1

0x426998 FMLA	Z29.D, P7/M, Z31.D, Z0.D

0x42699c ADDVL	X6, SP, #8

0x4269a0 FMAD	Z29.D, P7/M, Z18.D, Z20.D

0x4269a4 FADD	Z28.D, Z29.D, Z28.D

0x4269a8 FMUL	Z12.D, Z28.D, Z12.D

0x4269ac ST1D	{Z12.D}, P6, [X10, Z25.D,LSL #3]    [18]

0x4269b0 LDR	Z20, [X17, MUL VL]    [14]

0x4269b4 LDR	Z21, [X30, #7, MUL VL]    [27]

0x4269b8 FMUL	Z28.D, Z30.D, Z30.D

0x4269bc ADD	X8, SP, #176

0x4269c0 ADD	X16, X16, #176

0x4269c4 LDR	Z12, [X16, MUL VL]    [9]

0x4269c8 ADD	X6, X6, #176

0x4269cc LDR	Z29, [X6, MUL VL]    [4]

0x4269d0 FMLA	Z12.D, P7/M, Z30.D, Z20.D

0x4269d4 FMLA	Z29.D, P7/M, Z30.D, Z21.D

0x4269d8 INCB	X30, ALL, MUL #9

0x4269dc LDR	Z20, [X30, MUL VL]    [26]

0x4269e0 LDR	Z21, [X8, #6, MUL VL]    [36]

0x4269e4 FMLA	Z12.D, P7/M, Z28.D, Z20.D

0x4269e8 FMLA	Z29.D, P7/M, Z28.D, Z21.D

0x4269ec FMUL	Z21.D, Z15.D, Z12.D

0x4269f0 LDR	Z12, [X8, #4, MUL VL]    [36]

0x4269f4 LDR	Z20, [X8, #5, MUL VL]    [36]

0x4269f8 FMAD	Z29.D, P7/M, Z26.D, Z21.D

0x4269fc FMLA	Z20.D, P7/M, Z30.D, Z12.D

0x426a00 LDR	Z21, [X8, #3, MUL VL]    [36]

0x426a04 LDR	Z12, [X8, #1, MUL VL]    [36]

0x426a08 FMLA	Z20.D, P7/M, Z28.D, Z21.D

0x426a0c ADDVL	X16, SP, #10

0x426a10 LDR	Z21, [X8, #2, MUL VL]    [36]

0x426a14 FMUL	Z20.D, Z13.D, Z20.D

0x426a18 FMLA	Z21.D, P7/M, Z30.D, Z12.D

0x426a1c LDR	Z12, [X8, MUL VL]    [36]

0x426a20 FMUL	Z27.D, Z27.D, Z19.D

0x426a24 FMLA	Z21.D, P7/M, Z28.D, Z12.D

0x426a28 FMAD	Z21.D, P7/M, Z14.D, Z20.D

0x426a2c FADD	Z29.D, Z29.D, Z21.D

0x426a30 FMUL	Z27.D, Z29.D, Z27.D

0x426a34 ADD	X16, X16, #176

0x426a38 ST1D	{Z27.D}, P5, [X9, Z16.D,LSL #3]    [15]

0x426a3c LDR	Z20, [X16, MUL VL]    [8]

0x426a40 ADD	X6, SP, #176

0x426a44 FDUP	Z21.D, #112

0x426a48 LDR	Z27, [X6, #7, MUL VL]    [3]

0x426a4c ADDVL	X17, SP, #8

0x426a50 FMUL	Z29.D, Z31.D, Z31.D

0x426a54 ADD	X30, SP, #176

0x426a58 INCB	X8, ALL, MUL #11

0x426a5c LDR	Z12, [X8, MUL VL]    [35]

0x426a60 ADD	X17, X17, #176

0x426a64 FMLA	Z12.D, P7/M, Z31.D, Z20.D

0x426a68 INCB	X6, ALL, MUL #9

0x426a6c FDIVR	Z24.D, P7/M, Z24.D, Z21.D

0x426a70 LDR	Z21, [X17, MUL VL]    [13]

0x426a74 LDR	Z20, [X6, MUL VL]    [2]

0x426a78 FMLA	Z21.D, P7/M, Z31.D, Z27.D

0x426a7c FMLA	Z12.D, P7/M, Z29.D, Z20.D

0x426a80 LDR	Z27, [X30, #6, MUL VL]    [25]

0x426a84 FMLA	Z21.D, P7/M, Z29.D, Z27.D

0x426a88 LDR	Z20, [X30, #5, MUL VL]    [25]

0x426a8c FMUL	Z27.D, Z22.D, Z12.D

0x426a90 LDR	Z12, [X30, #4, MUL VL]    [25]

0x426a94 FMAD	Z21.D, P7/M, Z23.D, Z27.D

0x426a98 FMLA	Z20.D, P7/M, Z31.D, Z12.D

0x426a9c LDR	Z27, [X30, #3, MUL VL]    [25]

0x426aa0 LDR	Z12, [X30, #1, MUL VL]    [25]

0x426aa4 FMLA	Z20.D, P7/M, Z29.D, Z27.D

0x426aa8 ADDVL	X17, SP, #17

0x426aac LDR	Z27, [X30, #2, MUL VL]    [25]

0x426ab0 FMUL	Z20.D, Z17.D, Z20.D

0x426ab4 FMLA	Z27.D, P7/M, Z31.D, Z12.D

0x426ab8 LDR	Z12, [X30, MUL VL]    [25]

0x426abc FMLA	Z27.D, P7/M, Z29.D, Z12.D

0x426ac0 FMAD	Z27.D, P7/M, Z18.D, Z20.D

0x426ac4 FADD	Z21.D, Z27.D, Z21.D

0x426ac8 ADDVL	X8, X30, #22

0x426acc ADD	X17, X17, #176

0x426ad0 FMUL	Z24.D, Z24.D, Z19.D

0x426ad4 ADDVL	X16, SP, #18

0x426ad8 FMUL	Z24.D, Z21.D, Z24.D

0x426adc ADDVL	X6, SP, #16

0x426ae0 ST1D	{Z24.D}, P6, [X9, Z25.D,LSL #3]    [15]

0x426ae4 LDR	Z21, [X17, MUL VL]    [12]

0x426ae8 ADDVL	X30, SP, #13

0x426aec ADD	X16, X16, #176

0x426af0 LDR	Z20, [X16, MUL VL]    [7]

0x426af4 ADD	X6, X6, #176

0x426af8 FMLA	Z20.D, P7/M, Z30.D, Z21.D

0x426afc LDR	Z21, [X6, MUL VL]    [1]

0x426b00 ADD	X30, X30, #176

0x426b04 LDR	Z12, [X8, MUL VL]    [34]

0x426b08 FMUL	Z27.D, Z30.D, Z28.D

0x426b0c FMUL	Z24.D, Z28.D, Z12.D

0x426b10 ADDVL	X8, SP, #12

0x426b14 FMLA	Z24.D, P7/M, Z27.D, Z21.D

0x426b18 LDR	Z21, [X30, MUL VL]    [24]

0x426b1c ADDVL	X16, SP, #15

0x426b20 ADDVL	X17, SP, #14

0x426b24 FMUL	Z21.D, Z28.D, Z21.D

0x426b28 ADDVL	X6, SP, #23

0x426b2c ADDVL	X30, SP, #19

0x426b30 FADD	Z24.D, Z20.D, Z24.D

0x426b34 ADD	X8, X8, #176

0x426b38 LDR	Z20, [X8, MUL VL]    [33]

0x426b3c ADD	X16, X16, #176

0x426b40 FMLA	Z21.D, P7/M, Z27.D, Z20.D

0x426b44 ADD	X17, X17, #176

0x426b48 ADD	X6, X6, #176

0x426b4c ADD	X30, X30, #176

0x426b50 LDR	Z20, [X16, MUL VL]    [6]

0x426b54 FMUL	Z24.D, Z24.D, Z13.D

0x426b58 LDR	Z13, [X17, MUL VL]    [11]

0x426b5c ADDVL	X8, SP, #20

0x426b60 FMLA	Z20.D, P7/M, Z30.D, Z13.D

0x426b64 ADDVL	X16, SP, #18

0x426b68 FADD	Z20.D, Z20.D, Z21.D

0x426b6c LDR	Z21, [X30, MUL VL]    [23]

0x426b70 FMAD	Z20.D, P7/M, Z14.D, Z24.D

0x426b74 LDR	Z14, [X6, MUL VL]    [31]

0x426b78 ADDVL	X17, SP, #17

0x426b7c ADDVL	X6, SP, #16

0x426b80 ADDVL	X30, SP, #13

0x426b84 MOVPRFX	Z24, Z11

0x426b88 FMLA	Z24.D, P7/M, Z30.D, Z10.D

0x426b8c ADD	X8, X8, #176

0x426b90 ADD	X16, X16, #176

0x426b94 FMUL	Z13.D, Z28.D, Z9.D

0x426b98 ADD	X17, X17, #176

0x426b9c FMUL	Z28.D, Z28.D, Z14.D

0x426ba0 ADD	X6, X6, #176

0x426ba4 ADD	X30, X30, #176

0x426ba8 FMLA	Z13.D, P7/M, Z27.D, Z8.D

0x426bac FMAD	Z27.D, P7/M, Z21.D, Z28.D

0x426bb0 LDR	Z28, [X8, MUL VL]    [32]

0x426bb4 FADD	Z13.D, Z13.D, Z24.D

0x426bb8 FMAD	Z30.D, P7/M, Z28.D, Z7.D

0x426bbc FMUL	Z15.D, Z13.D, Z15.D

0x426bc0 FADD	Z30.D, Z27.D, Z30.D

0x426bc4 ADDVL	X8, SP, #12

0x426bc8 FMAD	Z26.D, P7/M, Z30.D, Z15.D

0x426bcc FMUL	Z27.D, Z29.D, Z12.D

0x426bd0 FADD	Z26.D, Z26.D, Z20.D

0x426bd4 ST1D	{Z26.D}, P5, [X18, Z16.D,LSL #3]    [39]

0x426bd8 LDR	Z20, [X17, MUL VL]    [10]

0x426bdc LDR	Z24, [X6, MUL VL]    [30]

0x426be0 LDR	Z12, [X16, MUL VL]    [5]

0x426be4 LDR	Z21, [X30, MUL VL]    [17]

0x426be8 FMUL	Z16.D, Z31.D, Z29.D

0x426bec FMLA	Z12.D, P7/M, Z31.D, Z20.D

0x426bf0 FMLA	Z27.D, P7/M, Z16.D, Z24.D

0x426bf4 ADDVL	X16, SP, #15

0x426bf8 ADDVL	X17, SP, #14

0x426bfc ADDVL	X6, SP, #19

0x426c00 FADD	Z13.D, Z12.D, Z27.D

0x426c04 ADDVL	X30, SP, #20

0x426c08 FMUL	Z15.D, Z29.D, Z21.D

0x426c0c FMUL	Z12.D, Z29.D, Z9.D

0x426c10 ADD	X8, X8, #176

0x426c14 LDR	Z28, [X8, MUL VL]    [19]

0x426c18 FMLA	Z12.D, P7/M, Z16.D, Z8.D

0x426c1c FMLA	Z15.D, P7/M, Z16.D, Z28.D

0x426c20 ADD	X16, X16, #176

0x426c24 LDR	Z30, [X16, MUL VL]    [38]

0x426c28 ADD	X17, X17, #176

0x426c2c LDR	Z26, [X17, MUL VL]    [40]

0x426c30 ADD	X6, X6, #176

0x426c34 FMLA	Z30.D, P7/M, Z31.D, Z26.D

0x426c38 ADD	X30, X30, #176

0x426c3c LDR	Z24, [X30, MUL VL]    [16]

0x426c40 FMUL	Z17.D, Z17.D, Z13.D

0x426c44 FADD	Z20.D, Z30.D, Z15.D

0x426c48 FMAD	Z20.D, P7/M, Z18.D, Z17.D

0x426c4c FMUL	Z18.D, Z29.D, Z14.D

0x426c50 LDR	Z14, [X6, MUL VL]    [29]

0x426c54 MOVPRFX	Z29, Z11

0x426c58 FMLA	Z29.D, P7/M, Z31.D, Z10.D

0x426c5c FMAD	Z16.D, P7/M, Z14.D, Z18.D

0x426c60 FADD	Z27.D, Z29.D, Z12.D

0x426c64 FMAD	Z31.D, P7/M, Z24.D, Z7.D

0x426c68 FMUL	Z22.D, Z22.D, Z27.D

0x426c6c FADD	Z31.D, Z16.D, Z31.D

0x426c70 FMAD	Z23.D, P7/M, Z31.D, Z22.D

0x426c74 FADD	Z23.D, Z20.D, Z23.D

0x426c78 ST1D	{Z23.D}, P6, [X18, Z25.D,LSL #3]    [39]

0x426c7c ADD	X5, X5, X0

0x426c80 WHILELO	P4.S, W5, W7

0x426c84 B.NE	426860

/usr/include/c++/14/bits/stl_vector.h: 1147 - 1147

--------------------------------------------------------------------------------

1147:       operator[](size_type __n) const _GLIBCXX_NOEXCEPT

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 305 - 336

--------------------------------------------------------------------------------

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

Coverage (%)	Name	Source Location	Module
►97.41+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main._omp_fn.1	miniqmc.cpp:443	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	stl_vector.h:1147-1147,BsplineFunctor.h:305-336
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	69.00
CQA cycles if no scalar integer	69.00
CQA cycles if FP arith vectorized	69.00
CQA cycles if fully vectorized	68.03
Front-end cycles	33.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	10.50
P3 cycles	10.25
P4 cycles	33.00
P5 cycles	10.25
P6 cycles	69.00
P7 cycles	69.00
P8 cycles	50.00
P9 cycles	50.00
P10 cycles	31.50
P11 cycles	31.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	13.99 - 28.17
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	266.00
Nb uops	266.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	8.93
Nb FLOP add-sub	64.00
Nb FLOP mul	128.00
Nb FLOP fma	208.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.22
Bytes prefetched	0.00
Bytes loaded	1824.00
Bytes stored	192.00
Stride 0	0.00
Stride 1	0.00
Stride n	26.00
Stride unknown	8.00
Stride indirect	4.00
Vectorization ratio all	86.70
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	22.86
Vector-efficiency ratio all	98.18
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	89.46

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	stl_vector.h:1147-1147,BsplineFunctor.h:305-336
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	69.00
CQA cycles if no scalar integer	69.00
CQA cycles if FP arith vectorized	69.00
CQA cycles if fully vectorized	68.03
Front-end cycles	33.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	10.50
P3 cycles	10.25
P4 cycles	33.00
P5 cycles	10.25
P6 cycles	69.00
P7 cycles	69.00
P8 cycles	50.00
P9 cycles	50.00
P10 cycles	31.50
P11 cycles	31.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	13.99 - 28.17
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	266.00
Nb uops	266.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	8.93
Nb FLOP add-sub	64.00
Nb FLOP mul	128.00
Nb FLOP fma	208.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.22
Bytes prefetched	0.00
Bytes loaded	1824.00
Bytes stored	192.00
Stride 0	0.00
Stride 1	0.00
Stride n	26.00
Stride unknown	8.00
Stride indirect	4.00
Vectorization ratio all	86.70
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	22.86
Vector-efficiency ratio all	98.18
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	89.46

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	BsplineFunctor.h:305-336
Module	exec

The loop is defined in:

/usr/include/c++/14/bits/stl_vector.h:1147
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305-336

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 98% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 69.00 to 68.03 cycles (1.01x speedup).

Details

86% of VPU instructions are used in vector version (process two or more data elements in vector registers):

22% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 208 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)
Constant non-unit stride: 26 occurrence(s)
Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 616 FP arithmetical operations:

272: addition or subtraction (208 inside FMA instructions)
336: multiply (208 inside FMA instructions)
8: divide

The binary loop is loading 1824 bytes. The binary loop is storing 192 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	266
nb uops	266
loop length	1064
used w registers	2
used x registers	14
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	0.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	33.25 cycles
front end	33.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	10.50	10.25	33.00	10.25	69.00	69.00	3.00	3.00	31.50	31.50	0.00	0.00	0.00
cycles	0.50	0.50	10.50	10.25	33.00	10.25	69.00	69.00	50.00	50.00	31.50	31.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	13.99-28.17
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	33.25
Dispatch	69.00
DIV/SQRT	13.99-28.17
Data deps.	1.00
Overall L1	69.00

Vectorization ratios

INT

all	73%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	66%

INT+FP

all	86%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	22%

Vector efficiency ratios

INT

all	98%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	93%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	67%

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	89%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 69.00 cycles. At this rate:

27% of peak load performance is reached (26.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 426860

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUNPKLO P5.H, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	vect (12.5%)
PUNPKHI P6.H, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	vect (12.5%)
LD1D {Z27.D}, P5/Z, [X11, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z24.D}, P6/Z, [X13, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z15.D, Z27.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z31.D, Z24.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z17, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FCVTZS Z17.S, P7/M, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
MOVPRFX Z18, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FCVTZS Z18.S, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
MOVPRFX Z20, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FRINTZ Z20.D, P7/M, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
UZP1 Z21.S, Z17.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z30.D, Z15.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
ADD Z22.S, Z22.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z28, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z28.D, P7/M, Z30.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
SUNPKLO Z25.D, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
LD1D {Z13.D}, P5/Z, [X4, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z12.D, Z13.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z26, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
ADD Z26.S, Z26.S, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SUNPKHI Z23.D, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SUNPKLO Z16.D, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SUNPKLO Z22.D, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
LD1D {Z14.D}, P5/Z, [X4, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z28, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
ADD Z28.S, Z28.S, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z29, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z29.D, P7/M, Z30.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
SUNPKHI Z26.D, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMAD Z29.D, P7/M, Z14.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
SUNPKHI Z12.D, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SUNPKLO Z21.D, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
LD1D {Z15.D}, P5/Z, [X4, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADDVL X30, SP, #21	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
LD1D {Z22.D}, P6/Z, [X4, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z26.D}, P5/Z, [X4, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z21, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FRINTZ Z21.D, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
LD1D {Z17.D}, P6/Z, [X4, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z31.D, Z31.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SUNPKHI Z16.D, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MOVPRFX Z21, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z21.D, P7/M, Z31.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADD X30, X30, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z20, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z25, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z25.D, P7/M, Z30.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ORR Z18.D, Z20.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADDVL X8, SP, #24	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMLA Z18.D, P7/M, Z30.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z20.D, P7/M, Z31.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z23.D, Z15.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z25.D, P7/M, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z29.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z18.D}, P6/Z, [X4, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P6/Z, [X4, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1W {Z25.S}, P4/Z, [X12, X5,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X8, X8, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z12, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUNPKLO Z16.D, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z28.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADDVL X17, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ST1D {Z28.D}, P5, [X10, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FMUL Z29.D, Z22.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z20.D, Z17.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDUP Z21.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (3.1%)
SUNPKHI Z25.D, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X30, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVPRFX Z28, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z28.D, P7/M, Z31.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FDIVR Z27.D, P7/M, Z27.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMAD Z28.D, P7/M, Z23.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADDVL X16, SP, #11	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
MOVPRFX Z29, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z29.D, P7/M, Z31.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADDVL X6, SP, #8	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMAD Z29.D, P7/M, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z28.D, Z29.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z12.D, Z28.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z12.D}, P6, [X10, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LDR Z20, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z21, [X30, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z28.D, Z30.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADD X8, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z12, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z29, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z12.D, P7/M, Z30.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z29.D, P7/M, Z30.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
INCB X30, ALL, MUL #9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
LDR Z20, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z21, [X8, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z12.D, P7/M, Z28.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z29.D, P7/M, Z28.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z21.D, Z15.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LDR Z12, [X8, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z20, [X8, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMAD Z29.D, P7/M, Z26.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z20.D, P7/M, Z30.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z21, [X8, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z12, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z20.D, P7/M, Z28.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADDVL X16, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
LDR Z21, [X8, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z20.D, Z13.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z21.D, P7/M, Z30.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z12, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z27.D, Z27.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z21.D, P7/M, Z28.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z21.D, P7/M, Z14.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z29.D, Z29.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z27.D, Z29.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ST1D {Z27.D}, P5, [X9, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LDR Z20, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X6, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FDUP Z21.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (3.1%)
LDR Z27, [X6, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADDVL X17, SP, #8	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMUL Z29.D, Z31.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADD X30, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
INCB X8, ALL, MUL #11	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
LDR Z12, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMLA Z12.D, P7/M, Z31.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
INCB X6, ALL, MUL #9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FDIVR Z24.D, P7/M, Z24.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LDR Z21, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z20, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z21.D, P7/M, Z31.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z12.D, P7/M, Z29.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z27, [X30, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z21.D, P7/M, Z29.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z20, [X30, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z27.D, Z22.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LDR Z12, [X30, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMAD Z21.D, P7/M, Z23.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z20.D, P7/M, Z31.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z27, [X30, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z12, [X30, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z20.D, P7/M, Z29.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADDVL X17, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
LDR Z27, [X30, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z20.D, Z17.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z27.D, P7/M, Z31.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z12, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z27.D, P7/M, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z27.D, P7/M, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z21.D, Z27.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADDVL X8, X30, #22	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMUL Z24.D, Z24.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADDVL X16, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMUL Z24.D, Z21.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADDVL X6, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ST1D {Z24.D}, P6, [X9, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LDR Z21, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADDVL X30, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z20, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMLA Z20.D, P7/M, Z30.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z21, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X30, X30, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z12, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z27.D, Z30.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z24.D, Z28.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADDVL X8, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMLA Z24.D, P7/M, Z27.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z21, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADDVL X16, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ADDVL X17, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMUL Z21.D, Z28.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADDVL X6, SP, #23	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ADDVL X30, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FADD Z24.D, Z20.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADD X8, X8, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z20, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMLA Z21.D, P7/M, Z27.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X30, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z20, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z24.D, Z24.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LDR Z13, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADDVL X8, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMLA Z20.D, P7/M, Z30.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADDVL X16, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FADD Z20.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LDR Z21, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMAD Z20.D, P7/M, Z14.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z14, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADDVL X17, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ADDVL X6, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ADDVL X30, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
MOVPRFX Z24, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z24.D, P7/M, Z30.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADD X8, X8, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMUL Z13.D, Z28.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMUL Z28.D, Z28.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X30, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMLA Z13.D, P7/M, Z27.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z27.D, P7/M, Z21.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z28, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z13.D, Z13.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z30.D, P7/M, Z28.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z15.D, Z13.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z30.D, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADDVL X8, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMAD Z26.D, P7/M, Z30.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z27.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z26.D, Z26.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z26.D}, P5, [X18, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LDR Z20, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z24, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z12, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z21, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z16.D, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z12.D, P7/M, Z31.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z27.D, P7/M, Z16.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADDVL X16, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ADDVL X17, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ADDVL X6, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FADD Z13.D, Z12.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADDVL X30, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMUL Z15.D, Z29.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z12.D, Z29.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADD X8, X8, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z28, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z12.D, P7/M, Z16.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z15.D, P7/M, Z16.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z30, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z26, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMLA Z30.D, P7/M, Z31.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADD X30, X30, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z24, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z17.D, Z17.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z20.D, Z30.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z20.D, P7/M, Z18.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z18.D, Z29.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LDR Z14, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z29, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z29.D, P7/M, Z31.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z16.D, P7/M, Z14.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z27.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z31.D, P7/M, Z24.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z22.D, Z22.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z31.D, Z16.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z23.D, P7/M, Z31.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z23.D, Z20.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z23.D}, P6, [X18, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X5, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P4.S, W5, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.NE 426860 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	BsplineFunctor.h:305-336
Module	exec

The loop is defined in:

/usr/include/c++/14/bits/stl_vector.h:1147
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305-336

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

86% of VPU instructions are used in vector version (process two or more data elements in vector registers):

22% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 208 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)
Constant non-unit stride: 26 occurrence(s)
Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 616 FP arithmetical operations:

272: addition or subtraction (208 inside FMA instructions)
336: multiply (208 inside FMA instructions)
8: divide

The binary loop is loading 1824 bytes. The binary loop is storing 192 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	266
nb uops	266
loop length	1064
used w registers	2
used x registers	14
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	0.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	33.25 cycles
front end	33.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	10.50	10.25	33.00	10.25	69.00	69.00	3.00	3.00	31.50	31.50	0.00	0.00	0.00
cycles	0.50	0.50	10.50	10.25	33.00	10.25	69.00	69.00	50.00	50.00	31.50	31.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	13.99-28.17
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	33.25
Dispatch	69.00
DIV/SQRT	13.99-28.17
Data deps.	1.00
Overall L1	69.00

Vectorization ratios

INT

all	73%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	66%

INT+FP

all	86%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	22%

Vector efficiency ratios

INT

all	98%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	93%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	67%

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	89%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 69.00 cycles. At this rate:

27% of peak load performance is reached (26.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 426860

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUNPKLO P5.H, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	vect (12.5%)
PUNPKHI P6.H, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	vect (12.5%)
LD1D {Z27.D}, P5/Z, [X11, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z24.D}, P6/Z, [X13, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z15.D, Z27.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z31.D, Z24.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z17, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FCVTZS Z17.S, P7/M, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
MOVPRFX Z18, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FCVTZS Z18.S, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
MOVPRFX Z20, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FRINTZ Z20.D, P7/M, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
UZP1 Z21.S, Z17.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z30.D, Z15.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
ADD Z22.S, Z22.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z28, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z28.D, P7/M, Z30.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
SUNPKLO Z25.D, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
LD1D {Z13.D}, P5/Z, [X4, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z12.D, Z13.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z26, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
ADD Z26.S, Z26.S, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SUNPKHI Z23.D, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SUNPKLO Z16.D, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SUNPKLO Z22.D, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
LD1D {Z14.D}, P5/Z, [X4, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z28, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
ADD Z28.S, Z28.S, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z29, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z29.D, P7/M, Z30.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
SUNPKHI Z26.D, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMAD Z29.D, P7/M, Z14.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
SUNPKHI Z12.D, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SUNPKLO Z21.D, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
LD1D {Z15.D}, P5/Z, [X4, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADDVL X30, SP, #21	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
LD1D {Z22.D}, P6/Z, [X4, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z26.D}, P5/Z, [X4, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z21, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FRINTZ Z21.D, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
LD1D {Z17.D}, P6/Z, [X4, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z31.D, Z31.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SUNPKHI Z16.D, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MOVPRFX Z21, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z21.D, P7/M, Z31.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADD X30, X30, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z20, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z25, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z25.D, P7/M, Z30.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ORR Z18.D, Z20.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADDVL X8, SP, #24	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMLA Z18.D, P7/M, Z30.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z20.D, P7/M, Z31.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z23.D, Z15.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z25.D, P7/M, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z29.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z18.D}, P6/Z, [X4, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P6/Z, [X4, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1W {Z25.S}, P4/Z, [X12, X5,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X8, X8, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z12, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUNPKLO Z16.D, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z28.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADDVL X17, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ST1D {Z28.D}, P5, [X10, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FMUL Z29.D, Z22.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z20.D, Z17.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDUP Z21.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (3.1%)
SUNPKHI Z25.D, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X30, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVPRFX Z28, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z28.D, P7/M, Z31.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FDIVR Z27.D, P7/M, Z27.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMAD Z28.D, P7/M, Z23.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADDVL X16, SP, #11	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
MOVPRFX Z29, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z29.D, P7/M, Z31.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADDVL X6, SP, #8	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMAD Z29.D, P7/M, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z28.D, Z29.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z12.D, Z28.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z12.D}, P6, [X10, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LDR Z20, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z21, [X30, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z28.D, Z30.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADD X8, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z12, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z29, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z12.D, P7/M, Z30.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z29.D, P7/M, Z30.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
INCB X30, ALL, MUL #9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
LDR Z20, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z21, [X8, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z12.D, P7/M, Z28.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z29.D, P7/M, Z28.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z21.D, Z15.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LDR Z12, [X8, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z20, [X8, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMAD Z29.D, P7/M, Z26.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z20.D, P7/M, Z30.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z21, [X8, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z12, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z20.D, P7/M, Z28.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADDVL X16, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
LDR Z21, [X8, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z20.D, Z13.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z21.D, P7/M, Z30.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z12, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z27.D, Z27.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z21.D, P7/M, Z28.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z21.D, P7/M, Z14.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z29.D, Z29.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z27.D, Z29.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ST1D {Z27.D}, P5, [X9, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LDR Z20, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X6, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FDUP Z21.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (3.1%)
LDR Z27, [X6, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADDVL X17, SP, #8	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMUL Z29.D, Z31.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADD X30, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
INCB X8, ALL, MUL #11	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
LDR Z12, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMLA Z12.D, P7/M, Z31.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
INCB X6, ALL, MUL #9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FDIVR Z24.D, P7/M, Z24.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LDR Z21, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z20, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z21.D, P7/M, Z31.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z12.D, P7/M, Z29.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z27, [X30, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z21.D, P7/M, Z29.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z20, [X30, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z27.D, Z22.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LDR Z12, [X30, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMAD Z21.D, P7/M, Z23.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z20.D, P7/M, Z31.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z27, [X30, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z12, [X30, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z20.D, P7/M, Z29.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADDVL X17, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
LDR Z27, [X30, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z20.D, Z17.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z27.D, P7/M, Z31.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z12, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z27.D, P7/M, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z27.D, P7/M, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z21.D, Z27.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADDVL X8, X30, #22	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMUL Z24.D, Z24.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADDVL X16, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMUL Z24.D, Z21.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADDVL X6, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ST1D {Z24.D}, P6, [X9, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LDR Z21, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADDVL X30, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z20, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMLA Z20.D, P7/M, Z30.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z21, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X30, X30, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z12, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z27.D, Z30.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z24.D, Z28.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADDVL X8, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMLA Z24.D, P7/M, Z27.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z21, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADDVL X16, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ADDVL X17, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMUL Z21.D, Z28.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADDVL X6, SP, #23	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ADDVL X30, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FADD Z24.D, Z20.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADD X8, X8, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z20, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMLA Z21.D, P7/M, Z27.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X30, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z20, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z24.D, Z24.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LDR Z13, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADDVL X8, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMLA Z20.D, P7/M, Z30.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADDVL X16, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FADD Z20.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LDR Z21, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMAD Z20.D, P7/M, Z14.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z14, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADDVL X17, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ADDVL X6, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ADDVL X30, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
MOVPRFX Z24, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z24.D, P7/M, Z30.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADD X8, X8, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMUL Z13.D, Z28.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMUL Z28.D, Z28.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X30, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMLA Z13.D, P7/M, Z27.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z27.D, P7/M, Z21.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z28, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z13.D, Z13.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z30.D, P7/M, Z28.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z15.D, Z13.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z30.D, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADDVL X8, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMAD Z26.D, P7/M, Z30.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z27.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z26.D, Z26.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z26.D}, P5, [X18, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LDR Z20, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z24, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z12, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z21, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z16.D, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z12.D, P7/M, Z31.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z27.D, P7/M, Z16.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADDVL X16, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ADDVL X17, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ADDVL X6, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FADD Z13.D, Z12.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADDVL X30, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
FMUL Z15.D, Z29.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z12.D, Z29.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADD X8, X8, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z28, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z12.D, P7/M, Z16.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z15.D, P7/M, Z16.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADD X16, X16, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z30, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X17, X17, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z26, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X6, X6, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMLA Z30.D, P7/M, Z31.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADD X30, X30, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z24, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z17.D, Z17.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z20.D, Z30.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z20.D, P7/M, Z18.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z18.D, Z29.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LDR Z14, [X6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z29, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z29.D, P7/M, Z31.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z16.D, P7/M, Z14.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z27.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z31.D, P7/M, Z24.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z22.D, Z22.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z31.D, Z16.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z23.D, P7/M, Z31.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z23.D, Z20.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z23.D}, P6, [X18, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X5, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P4.S, W5, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.NE 426860 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code