OV - exec - Loop 58

	Loop Id: 58	Module: exec	Source: NonLocalPP.hpp:126-135 [...]	Coverage: 0.08%

0x41475c ADD	X23, X23, #1

0x414760 CMP	X23, X5

0x414764 B.CS	414924

0x414768 LDR	X11, [X27, #24]

0x41476c UBFM	X10, X23, #61, #31

0x414770 ORR	W14, WZR, W23

0x414774 LDR	D31, [X28, #64]

0x414778 LDR	D1, [X11, X10]

0x41477c ADD	X12, X11, X10

0x414780 FCMPE	D1, D31

0x414784 B.GE	41475c

0x414788 LDP	X5, X0, [X26, #40]

0x41478c ORR	X13, XZR, #0xaa

0x414790 MOVK	X13, #43691

0x414794 SUB	X30, X0, X5

0x414798 SBFM	X4, X30, #3, #63

0x41479c MUL	X8, X4, X13

0x4147a0 CMP	W8, #0

0x4147a4 B.LE	4148d4

0x4147a8 LDR	X1, [SP, #200]

0x4147ac SUB	W15, W8, #1

0x4147b0 ORR	X2, XZR, X19

0x4147b4 ADD	X9, X15, #1

0x4147b8 LDR	X18, [X21, #64]

0x4147bc ADD	X7, X9, X9,LSL #1

0x4147c0 LDR	X0, [SP, #400]

0x4147c4 ADD	X16, X19, X7,LSL #3

0x4147c8 LDRSW	X6, [X1, #8]

0x4147cc LDR	X15, [X1, #24]

0x4147d0 ADD	X1, X18, X24

0x4147d4 ADD	X3, X6, X23

0x4147d8 ADD	X5, X6, X3

0x4147dc UBFM	X30, X3, #61, #60

0x4147e0 ADD	X4, X15, X5,LSL #3

0x4147e4 UBFM	X9, X5, #61, #60

0x4147e8 ADD	X13, X15, X10

0x4147ec ADD	X8, X15, X3,LSL #3

0x4147f0 TBNZ	W7, #0, 414888

0x4147f4 LDR	D7, [X15, X10]

0x4147f8 ADD	X0, X0, #24

0x4147fc LDR	D26, [X18, X24]

0x414800 LDR	D24, [X15, X30]

0x414804 LDP	D28, D12, [X1, #8]

0x414808 LDR	D16, [X15, X9]

0x41480c FADD	D3, D7, D26

0x414810 LDR	D11, [X19, #16]

0x414814 FADD	D2, D28, D24

0x414818 LDR	Q22, [X2], #24

0x41481c FADD	D30, D16, D12

0x414820 MOV	V3.D[1], V2.D[0]

0x414824 FMADD	D29, D11, D1, D30

0x414828 FMLA	V3.2D, V22.2D, V1.D[0]

0x41482c STUR	D29, [X0, #504]

0x414830 STUR	Q3, [X0, #488]

0x414834 LDR	D1, [X11, X10]

0x414838 B	414888

  (59) 0x41483c LDR	D24, [X8]

  (59) 0x414840 ADD	X2, X2, #48

  (59) 0x414844 ADD	X0, X0, #48

  (59) 0x414848 LDR	D12, [X13]

  (59) 0x41484c LDP	D23, D19, [X1]

  (59) 0x414850 LDR	D7, [X4]

  (59) 0x414854 LDR	D18, [X1, #16]

  (59) 0x414858 FADD	D16, D19, D24

  (59) 0x41485c FADD	D2, D12, D23

  (59) 0x414860 LDUR	Q22, [X2, #488]

  (59) 0x414864 LDR	D3, [X12]

  (59) 0x414868 LDR	D31, [X10, #16]

  (59) 0x41486c FADD	D26, D7, D18

  (59) 0x414870 MOV	V2.D[1], V16.D[0]

  (59) 0x414874 FMADD	D28, D31, D3, D26

  (59) 0x414878 FMLA	V2.2D, V22.2D, V3.D[0]

  (59) 0x41487c STUR	Q2, [X0, #488]

  (59) 0x414880 STR	D28, [X11, #16]

  (59) 0x414884 LDR	D1, [X12]

  (59) 0x414888 ORR	X10, XZR, X2

  (59) 0x41488c ADD	X11, X0, #24

  (59) 0x414890 LDR	D4, [X8]

  (59) 0x414894 LDR	D14, [X13]

  (59) 0x414898 LDP	D20, D10, [X1]

  (59) 0x41489c LDR	D0, [X4]

  (59) 0x4148a0 LDR	D6, [X1, #16]

  (59) 0x4148a4 FADD	D5, D10, D4

  (59) 0x4148a8 FADD	D27, D14, D20

  (59) 0x4148ac LDR	D17, [X2, #16]

  (59) 0x4148b0 LDR	Q21, [X10], #24

  (59) 0x4148b4 FADD	D13, D0, D6

  (59) 0x4148b8 MOV	V27.D[1], V5.D[0]

  (59) 0x4148bc FMADD	D25, D17, D1, D13

  (59) 0x4148c0 FMLA	V27.2D, V21.2D, V1.D[0]

  (59) 0x4148c4 STR	Q27, [X0]

  (59) 0x4148c8 STR	D25, [X0, #16]

  (59) 0x4148cc CMP	X10, X16

  (59) 0x4148d0 B.NE	41483c

0x4148d4 LDR	X17, [X17, #24]

0x4148d8 ORR	W5, WZR, W23

0x4148dc MOVZ	W4, #1

0x4148e0 ADD	X3, SP, #400

0x4148e4 ORR	X1, XZR, X21

0x4148e8 LDR	X12, [X26, #64]

0x4148ec LDR	W2, [SP, #168]

0x4148f0 LDRSW	X14, [X17, X14,LSL #2]

0x4148f4 LDR	X0, [X12, X14,LSL #3]

0x4148f8 STR	X0, [SP, #144]

0x4148fc BL	4a0a00

0x414900 LDR	X1, [SP, #144]

0x414904 ADD	X2, SP, #432

0x414908 ORR	X0, XZR, X22

0x41490c BL	41c290

0x414910 LDR	X17, [X28, #5208]

0x414914 ADD	X23, X23, #1

0x414918 LDR	X5, [X17, #608]

0x41491c CMP	X23, X5

0x414920 B.CC	414768

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 43 - 63

--------------------------------------------------------------------------------

43:     return (a + b);

[...]

63:     return (a * b);

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 145 - 145

--------------------------------------------------------------------------------

145:       X[i] = base[i * offset];

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp: 126 - 135

--------------------------------------------------------------------------------

126:       for (int iat = 0; iat < ions_ref.getTotalNum(); ++iat)

127:       {

128:         //due to < Rmax condition, the actually iteration iat is [0,2] in a real simulation

129:         if (dist[iat] < Rmax)

130:         {

131:           for (int k = 0; k < size(); k++)

132:             virtualPos[k] = dist[iat] * rOnSphere[k] + displ[iat] + els.R[jel];

133:           auto& VP = *VPs[ions_ref.GroupID[iat]];

134:           VP.makeMoves(els, jel, virtualPos, true, iat);

135:           wf.evaluateRatios(VP, ratios);

/usr/include/c++/14/bits/stl_vector.h: 992 - 1131

--------------------------------------------------------------------------------

992:       size() const _GLIBCXX_NOEXCEPT

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1131: 	return *(this->_M_impl._M_start + __n);

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 229 - 229

--------------------------------------------------------------------------------

229:     return X[i];

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 231

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 277 - 277

--------------------------------------------------------------------------------

277:   inline size_t getTotalNum() const { return TotalNum; }

/usr/include/c++/14/bits/unique_ptr.h: 193 - 193

--------------------------------------------------------------------------------

193:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

Coverage (%)	Name	Module
►98.69+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.04
CQA speedup if FP arith vectorized	1.63
CQA speedup if fully vectorized	1.39
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	micro-operation queue, P10,
Function	main._omp_fn.1
Source	OperatorTags.h:43-43,OperatorTags.h:63-63,TinyVector.h:145-145,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135,stl_vector.h:993-993,stl_vector.h:1131-1131,OhmmsVector.h:229-229,VectorSoAContainer.h:231-231,ParticleSet.h:277-277,unique_ptr.h:193-193
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	5.83
CQA cycles if fully vectorized	6.81
Front-end cycles	9.50
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	9.00
P3 cycles	9.00
P4 cycles	9.00
P5 cycles	9.00
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	9.50
P11 cycles	9.17
P12 cycles	9.33
P13 cycles	0.50
P14 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	76.00
Nb loads	NA
Nb stores	3.00
Nb stack references	5.00
FLOP/cycle	0.95
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.95
Bytes prefetched	0.00
Bytes loaded	9.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	11.43
Vectorization ratio load	18.18
Vectorization ratio store	33.33
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	28.93
Vector-efficiency ratio load	28.41
Vector-efficiency ratio store	33.33
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	37.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	31.25

Metric	Value
CQA speedup if no scalar integer	2.04
CQA speedup if FP arith vectorized	1.63
CQA speedup if fully vectorized	1.39
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	micro-operation queue, P10,
Function	main._omp_fn.1
Source	OperatorTags.h:43-43,OperatorTags.h:63-63,TinyVector.h:145-145,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135,stl_vector.h:993-993,stl_vector.h:1131-1131,OhmmsVector.h:229-229,VectorSoAContainer.h:231-231,ParticleSet.h:277-277,unique_ptr.h:193-193
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	5.83
CQA cycles if fully vectorized	6.81
Front-end cycles	9.50
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	9.00
P3 cycles	9.00
P4 cycles	9.00
P5 cycles	9.00
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	9.50
P11 cycles	9.17
P12 cycles	9.33
P13 cycles	0.50
P14 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	76.00
Nb loads	NA
Nb stores	3.00
Nb stack references	5.00
FLOP/cycle	0.95
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.95
Bytes prefetched	0.00
Bytes loaded	9.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	11.43
Vectorization ratio load	18.18
Vectorization ratio store	33.33
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	28.93
Vector-efficiency ratio load	28.41
Vector-efficiency ratio store	33.33
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	37.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	31.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.1
Source file and lines	NonLocalPP.hpp:126-135
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135
/usr/include/c++/14/bits/stl_vector.h:992-993,1131
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:277
/usr/include/c++/14/bits/unique_ptr.h:193

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=6
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 6 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 4.67 cycles (2.04x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 9.50 to 6.81 cycles (1.39x speedup).

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

18% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
50% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

qmcplusplus::VirtualParticleSet::makeMoves(qmcplusplus::ParticleSet const&, int, std::vector
, std::allocator
> > const&, bool, int): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:134
qmcplusplus::WaveFunction::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector
>&): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:135

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 9 FP arithmetical operations:

6: addition or subtraction (3 inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 9 bytes.

Arithmetic intensity

Arithmetic intensity is 1.00 FP operations per loaded or stored byte.

General properties

nb instructions	76
nb uops	76
loop length	304
used w registers	9
used x registers	29
used b registers	0
used h registers	0
used s registers	1
used d registers	13
used q registers	2
used v registers	4
used z registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	9.00	9.00	9.00	9.00	2.25	2.25	2.25	2.25	9.50	9.17	9.33	0.50	0.50
cycles	4.00	4.00	9.00	9.00	9.00	9.00	2.25	2.25	2.25	2.25	9.50	9.17	9.33	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.50
Dispatch	9.50
Overall L1	9.50

Vectorization ratios

INT

all	10%
load	18%
store	33%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	16%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	11%
load	18%
store	33%
mul	0%
add-sub	0%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	28%
load	28%
store	33%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	32%

all	29%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	37%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	28%
load	28%
store	33%
mul	25%
add-sub	25%
fma	37%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.50 cycles. At this rate:

0% of peak load performance is reached (0.95 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 414768

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X23, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 414924 <main._omp_fn.1+0x11fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X27, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X10, X23, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W14, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X28, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X11, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X12, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FCMPE D1, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 41475c <main._omp_fn.1+0x1034>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X5, X0, [X26, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X13, XZR, #0xaa	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK X13, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X30, X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X4, X30, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
MUL X8, X4, X13	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
CMP W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 4148d4 <main._omp_fn.1+0x11ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W15, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X9, X9,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X19, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDRSW X6, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X15, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X18, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X6, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X30, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X15, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X9, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X15, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X15, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
TBNZ W7, #0, 414888 <main._omp_fn.1+0x1160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D7, [X15, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D26, [X18, X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D24, [X15, X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP D28, D12, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR D16, [X15, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D3, D7, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D11, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D2, D28, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR Q22, [X2], #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FADD D30, D16, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOV V3.D[1], V2.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMADD D29, D11, D1, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMLA V3.2D, V22.2D, V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
STUR D29, [X0, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STUR Q3, [X0, #488]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR D1, [X11, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
B 414888 <main._omp_fn.1+0x1160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X17, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W5, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X3, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X26, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDRSW X14, [X17, X14,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4a0a00 <_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, SP, #432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 41c290 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X28, #5208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X17, #608]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X23, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 414768 <main._omp_fn.1+0x1040>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main._omp_fn.1
Source file and lines	NonLocalPP.hpp:126-135
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135
/usr/include/c++/14/bits/stl_vector.h:992-993,1131
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:277
/usr/include/c++/14/bits/unique_ptr.h:193

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=6
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 4.67 cycles (2.04x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

18% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
50% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

qmcplusplus::VirtualParticleSet::makeMoves(qmcplusplus::ParticleSet const&, int, std::vector
, std::allocator
> > const&, bool, int): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:134
qmcplusplus::WaveFunction::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector
>&): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:135

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 9 FP arithmetical operations:

6: addition or subtraction (3 inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 9 bytes.

Arithmetic intensity

Arithmetic intensity is 1.00 FP operations per loaded or stored byte.

General properties

nb instructions	76
nb uops	76
loop length	304
used w registers	9
used x registers	29
used b registers	0
used h registers	0
used s registers	1
used d registers	13
used q registers	2
used v registers	4
used z registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	9.00	9.00	9.00	9.00	2.25	2.25	2.25	2.25	9.50	9.17	9.33	0.50	0.50
cycles	4.00	4.00	9.00	9.00	9.00	9.00	2.25	2.25	2.25	2.25	9.50	9.17	9.33	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.50
Dispatch	9.50
Overall L1	9.50

Vectorization ratios

INT

all	10%
load	18%
store	33%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	16%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	11%
load	18%
store	33%
mul	0%
add-sub	0%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	28%
load	28%
store	33%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	32%

all	29%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	37%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	28%
load	28%
store	33%
mul	25%
add-sub	25%
fma	37%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.50 cycles. At this rate:

0% of peak load performance is reached (0.95 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 414768

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X23, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 414924 <main._omp_fn.1+0x11fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X27, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X10, X23, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W14, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X28, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X11, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X12, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FCMPE D1, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 41475c <main._omp_fn.1+0x1034>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X5, X0, [X26, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X13, XZR, #0xaa	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK X13, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X30, X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X4, X30, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
MUL X8, X4, X13	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
CMP W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 4148d4 <main._omp_fn.1+0x11ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W15, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X9, X9,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X19, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDRSW X6, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X15, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X18, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X6, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X30, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X15, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X9, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X15, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X15, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
TBNZ W7, #0, 414888 <main._omp_fn.1+0x1160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D7, [X15, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D26, [X18, X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D24, [X15, X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP D28, D12, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR D16, [X15, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D3, D7, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D11, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D2, D28, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR Q22, [X2], #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FADD D30, D16, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOV V3.D[1], V2.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMADD D29, D11, D1, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMLA V3.2D, V22.2D, V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
STUR D29, [X0, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STUR Q3, [X0, #488]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR D1, [X11, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
B 414888 <main._omp_fn.1+0x1160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X17, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W5, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X3, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X26, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDRSW X14, [X17, X14,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4a0a00 <_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, SP, #432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 41c290 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X28, #5208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X17, #608]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X23, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 414768 <main._omp_fn.1+0x1040>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

CALL instructions

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

CALL instructions

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code