OV - exec - Function qmcplusplus::BsplineFunctor<double>::evaluateV(int, int, int, double const*, double*) const

	Function: qmcplusplus::BsplineFunctor<double>::evaluateV(int, int, int, double const, double) cons ...	Module: exec	Source: BsplineFunctor.h:233-262 [...]	Coverage (incl. loops): 0.04% \| (excl. loops): 0.01%

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h: 1150 - 1150

--------------------------------------------------------------------------------

1150: 	return *(this->_M_impl._M_start + __n);

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 233 - 262

--------------------------------------------------------------------------------

233:   const int iLimit = iEnd - iStart;

234:

235: #pragma vector always

236:   for (int jat = 0; jat < iLimit; jat++)

237:   {

238:     real_type r = distArray[jat];

239:     // pick the distances smaller than the cutoff and avoid the reference atom

240:     if (r < cutoff_radius && iStart + jat != iat)

241:       distArrayCompressed[iCount++] = distArray[jat];

242:   }

243:

244:   real_type d = 0.0;

245:   //#pragma omp simd reduction(+:d)

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

261:   }

262:   return d;

0x422d60 SUB	W9, W3, W2

0x422d64 MOVI	D0, #0

0x422d68 CMP	W9, #1

0x422d6c B.LT	423018

0x422d70 STP	D15, D14, [SP, #944]!

0x422d74 STP	D13, D12, [SP, #16]

0x422d78 STP	D11, D10, [SP, #32]

0x422d7c STP	D9, D8, [SP, #48]

0x422d80 STR	X29, [SP, #64]

0x422d84 ADDVL	SP, SP, #51

0x422d88 LDR	D1, [X0, #8]

0x422d8c ADD	X10, X4, W2,SXTW #3

0x422d90 SUB	W11, W1, W2

0x422d94 ORR	W8, WZR, WZR

0x422d98 B	422dac

0x422d9c HINT	#0

(277) 0x422da0 SUB	W11, W11, #1

(277) 0x422da4 SUBS	X9, X9, #1

(277) 0x422da8 B.EQ	422dc8

(277) 0x422dac LDR	D2, [X10], #8

(277) 0x422db0 FCMP	D2, D1

(277) 0x422db4 CCMP	W11, #0, #4, #11

(277) 0x422db8 B.EQ	422da0

(277) 0x422dbc STR	D2, [X5, W8,SXTW #3]

(277) 0x422dc0 ADD	W8, W8, #1

(277) 0x422dc4 B	422da0

0x422dc8 CMP	W8, #1

0x422dcc B.LT	423000

0x422dd0 LDR	D19, [X0, #568]

0x422dd4 LDP	D20, D21, [X0, #24]

0x422dd8 LDP	D28, D29, [X0, #40]

0x422ddc ORR	W9, WZR, W8

0x422de0 CNTD	X11, ALL

0x422de4 CMP	X11, X9

0x422de8 LDP	D30, D31, [X0, #56]

0x422dec LDP	D8, D9, [X0, #72]

0x422df0 LDP	D10, D11, [X0, #88]

0x422df4 LDP	D12, D13, [X0, #104]

0x422df8 LDP	D22, D23, [X0, #120]

0x422dfc LDP	D24, D25, [X0, #136]

0x422e00 LDR	X8, [X0, #536]

0x422e04 B.LS	422e14

0x422e08 ORR	X10, XZR, XZR

0x422e0c MOVI	D0, #0

0x422e10 B	422f78

0x422e14 DUP	Z0.D, Z19.D[0]

0x422e18 SUB	X10, XZR, X11

0x422e1c DUP	Z26.D, Z20.D[0]

0x422e20 STR	Z28, [SP, #9, MUL VL]

0x422e24 STR	Z29, [SP, #8, MUL VL]

0x422e28 MOVI	V15.2D, #0

0x422e2c DUP	Z27.D, Z21.D[0]

0x422e30 DUP	Z28.D, Z28.D[0]

0x422e34 STR	Z30, [SP, #7, MUL VL]

0x422e38 STR	Z31, [SP, #6, MUL VL]

0x422e3c PTRUE	P0.D, ALL

0x422e40 AND	X10, X10, X9

0x422e44 DUP	Z29.D, Z29.D[0]

0x422e48 DUP	Z30.D, Z30.D[0]

0x422e4c STR	Z8, [SP, #5, MUL VL]

0x422e50 STR	Z9, [SP, #4, MUL VL]

0x422e54 ORR	X12, XZR, XZR

0x422e58 DUP	Z31.D, Z31.D[0]

0x422e5c DUP	Z8.D, Z8.D[0]

0x422e60 STR	Z10, [SP, #3, MUL VL]

0x422e64 STR	Z11, [SP, #2, MUL VL]

0x422e68 DUP	Z9.D, Z9.D[0]

0x422e6c DUP	Z10.D, Z10.D[0]

0x422e70 DUP	Z11.D, Z11.D[0]

0x422e74 STR	Z12, [SP, #1, MUL VL]

0x422e78 STR	Z13, [SP, MUL VL]

0x422e7c STR	Z19, [SP, #12, MUL VL]

0x422e80 DUP	Z12.D, Z12.D[0]

0x422e84 DUP	Z13.D, Z13.D[0]

0x422e88 STR	Z20, [SP, #11, MUL VL]

0x422e8c STR	Z21, [SP, #10, MUL VL]

0x422e90 DUP	Z14.D, Z22.D[0]

0x422e94 DUP	Z1.D, Z23.D[0]

0x422e98 DUP	Z2.D, Z24.D[0]

0x422e9c DUP	Z3.D, Z25.D[0]

(275) 0x422ea0 LD1D	{Z4.D}, P0/Z, [X5, X12,LSL #3]

(275) 0x422ea4 DUP	Z17.D, X8

(275) 0x422ea8 ADD	X12, X12, X11

(275) 0x422eac CMP	X10, X12

(275) 0x422eb0 FMUL	Z6.D, Z0.D, Z4.D

(275) 0x422eb4 MOVPRFX	Z5, Z6

(275) 0x422eb8 FCVTZS	Z5.D, P0/M, Z6.D

(275) 0x422ebc MOVPRFX	Z4, Z5

(275) 0x422ec0 SCVTF	Z4.D, P0/M, Z5.D

(275) 0x422ec4 FSUB	Z4.D, Z6.D, Z4.D

(275) 0x422ec8 LD1D	{Z16.D}, P0/Z, [X8, Z5.D,LSL #3]

(275) 0x422ecc ADR	Z5.D, [Z17, Z5.D,LSL #3]

(275) 0x422ed0 FMUL	Z6.D, Z4.D, Z4.D

(275) 0x422ed4 MOVPRFX	Z17, Z29

(275) 0x422ed8 FMLA	Z17.D, P0/M, Z6.D, Z27.D

(275) 0x422edc FMUL	Z21.D, Z6.D, Z4.D

(275) 0x422ee0 LD1D	{Z18.D}, P0/Z, [V5, #1.D]

(275) 0x422ee4 LD1D	{Z20.D}, P0/Z, [V5, #2.D]

(275) 0x422ee8 LD1D	{Z5.D}, P0/Z, [V5, #3.D]

(275) 0x422eec FMLA	Z17.D, P0/M, Z28.D, Z4.D

(275) 0x422ef0 MOVPRFX	Z7, Z9

(275) 0x422ef4 FMLA	Z7.D, P0/M, Z30.D, Z21.D

(275) 0x422ef8 MOVPRFX	Z19, Z13

(275) 0x422efc FMLA	Z19.D, P0/M, Z10.D, Z21.D

(275) 0x422f00 FMLA	Z17.D, P0/M, Z21.D, Z26.D

(275) 0x422f04 FMAD	Z21.D, P0/M, Z14.D, Z3.D

(275) 0x422f08 FMLA	Z7.D, P0/M, Z31.D, Z6.D

(275) 0x422f0c FMLA	Z19.D, P0/M, Z11.D, Z6.D

(275) 0x422f10 FMLA	Z7.D, P0/M, Z8.D, Z4.D

(275) 0x422f14 FMLA	Z19.D, P0/M, Z12.D, Z4.D

(275) 0x422f18 FMAD	Z16.D, P0/M, Z17.D, Z15.D

(275) 0x422f1c FMAD	Z6.D, P0/M, Z1.D, Z21.D

(275) 0x422f20 FMAD	Z7.D, P0/M, Z18.D, Z16.D

(275) 0x422f24 FMAD	Z4.D, P0/M, Z2.D, Z6.D

(275) 0x422f28 FMLA	Z7.D, P0/M, Z19.D, Z20.D

(275) 0x422f2c MOVPRFX	Z15, Z7

(275) 0x422f30 FMLA	Z15.D, P0/M, Z4.D, Z5.D

(275) 0x422f34 B.NE	422ea0

0x422f38 FADDV	D0, P0, Z15.D

0x422f3c LDR	Z19, [SP, #12, MUL VL]

0x422f40 LDR	Z20, [SP, #11, MUL VL]

0x422f44 LDR	Z21, [SP, #10, MUL VL]

0x422f48 LDR	Z28, [SP, #9, MUL VL]

0x422f4c LDR	Z29, [SP, #8, MUL VL]

0x422f50 CMP	X10, X9

0x422f54 LDR	Z30, [SP, #7, MUL VL]

0x422f58 LDR	Z31, [SP, #6, MUL VL]

0x422f5c LDR	Z8, [SP, #5, MUL VL]

0x422f60 LDR	Z9, [SP, #4, MUL VL]

0x422f64 LDR	Z10, [SP, #3, MUL VL]

0x422f68 LDR	Z11, [SP, #2, MUL VL]

0x422f6c LDR	Z12, [SP, #1, MUL VL]

0x422f70 LDR	Z13, [SP, MUL VL]

0x422f74 B.EQ	423000

0x422f78 ADD	X11, X5, X10,LSL #3

0x422f7c SUB	X9, X9, X10

(276) 0x422f80 LDR	D1, [X11], #8

(276) 0x422f84 SUBS	X9, X9, #1

(276) 0x422f88 FMUL	D1, D19, D1

(276) 0x422f8c FRINTZ	D2, D1

(276) 0x422f90 FCVTZS	W10, D1

(276) 0x422f94 FSUB	D1, D1, S2

(276) 0x422f98 ADD	X10, X8, W10,SXTW #3

(276) 0x422f9c FMUL	D2, D1, D1

(276) 0x422fa0 LDP	D5, D6, [X10]

(276) 0x422fa4 LDP	D17, D18, [X10, #16]

(276) 0x422fa8 FMUL	D4, D2, D21

(276) 0x422fac FMUL	D3, D2, D1

(276) 0x422fb0 FMADD	D4, D28, D1, D4

(276) 0x422fb4 FMUL	D7, D30, D3

(276) 0x422fb8 FMUL	D16, D10, D3

(276) 0x422fbc FMADD	D7, D31, D2, D7

(276) 0x422fc0 FMADD	D16, D11, D2, D16

(276) 0x422fc4 FADD	D4, D4, D29

(276) 0x422fc8 FMADD	D7, D8, D1, D7

(276) 0x422fcc FMADD	D16, D12, D1, D16

(276) 0x422fd0 FMADD	D4, D3, D20, D4

(276) 0x422fd4 FMUL	D3, D22, D3

(276) 0x422fd8 FMADD	D2, D23, D2, D3

(276) 0x422fdc FADD	D7, D7, D9

(276) 0x422fe0 FMADD	D1, D24, D1, D2

(276) 0x422fe4 FADD	D16, D16, D13

(276) 0x422fe8 FMADD	D0, D4, D5, D0

(276) 0x422fec FMADD	D0, D7, D6, D0

(276) 0x422ff0 FADD	D1, D1, D25

(276) 0x422ff4 FMADD	D0, D16, D17, D0

(276) 0x422ff8 FMADD	D0, D1, D18, D0

(276) 0x422ffc B.NE	422f80

0x423000 ADDVL	SP, SP, #13

0x423004 LDP	D9, D8, [SP, #48]

0x423008 LDP	D11, D10, [SP, #32]

0x42300c LDP	D13, D12, [SP, #16]

0x423010 LDR	X29, [SP, #64]

0x423014 LDP	D15, D14, [SP], #80

0x423018 RET

0x42301c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.91+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:135	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:272	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:126	exec
○	main.omp_outlined.62	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.09+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:135	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:272	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:126	exec
○	main.omp_outlined.62	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:409	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:172	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run armclang_1

Source file and lines	BsplineFunctor.h:233-262
Module	exec

The function is defined in:

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h:1150
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:233-262

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.83 to 15.00 cycles (1.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 68% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 15.83 to 14.12 cycles (1.12x speedup).

Details

70% of VPU instructions are used in vector version (process two or more data elements in vector registers):

86% of VPU loads are used in vector version.
94% of VPU stores are used in vector version.
14% of VPU addition or subtraction instructions are used in vector version.
54% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary function is loading 416 bytes. The binary function is storing 416 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	96
nb uops	94
loop length	384
used w registers	7
used x registers	10
used b registers	0
used h registers	0
used s registers	1
used d registers	21
used q registers	0
used v registers	1
used z registers	25
nb stack references	36

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.75 cycles
front end	11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	5.25	5.25	5.25	5.25	11.00	11.00	8.50	8.50	15.83	15.50	15.67	0.50	0.50
cycles	3.50	3.50	5.25	5.25	5.25	5.25	11.00	11.00	8.50	8.50	15.83	15.50	15.67	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.75
Dispatch	15.83
Overall L1	15.83

Vectorization ratios

INT

all	70%
load	86%
store	94%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	54%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	70%
load	86%
store	94%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	54%

Vector efficiency ratios

INT

all	68%
load	68%
store	84%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	68%
load	68%
store	84%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	32%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	66%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.83 cycles. At this rate:

27% of peak load performance is reached (26.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
54% of peak store performance is reached (26.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 422d60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB W9, W3, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 423018 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D15, D14, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STR X29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADDVL SP, SP, #51	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR D1, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X10, X4, W2,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
SUB W11, W1, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR W8, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 422dac <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
CMP W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 423000 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D19, [X0, #568]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP D20, D21, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D28, D29, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
ORR W9, WZR, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDP D30, D31, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D8, D9, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D10, D11, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D12, D13, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D22, D23, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D24, D25, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR X8, [X0, #536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B.LS 422e14 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 422f78 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP Z0.D, Z19.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
SUB X10, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z26.D, Z20.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z28, [SP, #9, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z29, [SP, #8, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVI V15.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUP Z27.D, Z21.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z28.D, Z28.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z30, [SP, #7, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z31, [SP, #6, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
AND X10, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z29.D, Z29.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z30.D, Z30.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z8, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z9, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z31.D, Z31.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z8.D, Z8.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z10, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z11, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z9.D, Z9.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z10.D, Z10.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z11.D, Z11.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z12, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z13, [SP, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z19, [SP, #12, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z12.D, Z12.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z13.D, Z13.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z20, [SP, #11, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z21, [SP, #10, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z14.D, Z22.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, Z23.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z2.D, Z24.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z3.D, Z25.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FADDV D0, P0, Z15.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2	vect (100.0%)
LDR Z19, [SP, #12, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z20, [SP, #11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z21, [SP, #10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z28, [SP, #9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z29, [SP, #8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
CMP X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR Z30, [SP, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z31, [SP, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z8, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z9, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z10, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z11, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z12, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z13, [SP, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
B.EQ 423000 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X5, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADDVL SP, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR X29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP D15, D14, [SP], #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run armclang_1

Source file and lines	BsplineFunctor.h:233-262
Module	exec

The function is defined in:

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h:1150
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:233-262

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

70% of VPU instructions are used in vector version (process two or more data elements in vector registers):

86% of VPU loads are used in vector version.
94% of VPU stores are used in vector version.
14% of VPU addition or subtraction instructions are used in vector version.
54% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary function is loading 416 bytes. The binary function is storing 416 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	96
nb uops	94
loop length	384
used w registers	7
used x registers	10
used b registers	0
used h registers	0
used s registers	1
used d registers	21
used q registers	0
used v registers	1
used z registers	25
nb stack references	36

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.75 cycles
front end	11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	5.25	5.25	5.25	5.25	11.00	11.00	8.50	8.50	15.83	15.50	15.67	0.50	0.50
cycles	3.50	3.50	5.25	5.25	5.25	5.25	11.00	11.00	8.50	8.50	15.83	15.50	15.67	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.75
Dispatch	15.83
Overall L1	15.83

Vectorization ratios

INT

all	70%
load	86%
store	94%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	54%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	70%
load	86%
store	94%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	54%

Vector efficiency ratios

INT

all	68%
load	68%
store	84%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	68%
load	68%
store	84%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	32%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	66%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.83 cycles. At this rate:

27% of peak load performance is reached (26.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
54% of peak store performance is reached (26.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 422d60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB W9, W3, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 423018 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D15, D14, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STR X29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADDVL SP, SP, #51	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR D1, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X10, X4, W2,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
SUB W11, W1, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR W8, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 422dac <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
CMP W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 423000 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D19, [X0, #568]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP D20, D21, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D28, D29, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
ORR W9, WZR, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDP D30, D31, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D8, D9, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D10, D11, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D12, D13, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D22, D23, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D24, D25, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR X8, [X0, #536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B.LS 422e14 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 422f78 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP Z0.D, Z19.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
SUB X10, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z26.D, Z20.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z28, [SP, #9, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z29, [SP, #8, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVI V15.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUP Z27.D, Z21.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z28.D, Z28.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z30, [SP, #7, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z31, [SP, #6, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
AND X10, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z29.D, Z29.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z30.D, Z30.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z8, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z9, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z31.D, Z31.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z8.D, Z8.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z10, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z11, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z9.D, Z9.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z10.D, Z10.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z11.D, Z11.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z12, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z13, [SP, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z19, [SP, #12, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z12.D, Z12.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z13.D, Z13.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z20, [SP, #11, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z21, [SP, #10, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z14.D, Z22.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, Z23.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z2.D, Z24.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z3.D, Z25.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FADDV D0, P0, Z15.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2	vect (100.0%)
LDR Z19, [SP, #12, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z20, [SP, #11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z21, [SP, #10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z28, [SP, #9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z29, [SP, #8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
CMP X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR Z30, [SP, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z31, [SP, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z8, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z9, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z10, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z11, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z12, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z13, [SP, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
B.EQ 423000 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X5, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADDVL SP, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR X29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP D15, D14, [SP], #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼qmcplusplus::BsplineFunctor::evaluateV(int, int, int, double const, double) const–	0.04	0.07
○Loop 277 - BsplineFunctor.h:236-241 - exec	0.04	0.05
○Loop 275 - BsplineFunctor.h:246-260 - exec	0.00	0.00
○Loop 276 - BsplineFunctor.h:246-260 - exec	0.00	0.00

Report Configuration

Code clean check

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Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code