OV - exec - Function void qmcplusplus::DTD_BConds<double, 3u, 40>::computeDistances<qmcplusplus::TinyVector<double, 3u>, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 32ul> >, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 32ul> > >(qmcplusplus::TinyVector<double, 3u> const&, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 32ul> > const&, double*, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 32ul> >&, int, int, int) const

	Function: void qmcplusplus::DTD_BConds<double, 3u, 40>::computeDistances<qmcplusplus::TinyVector<dou ...	Module: exec	Source: ParticleBConds3DSoa.h:234-257	Coverage (incl. loops): 1.47% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 234 - 257

--------------------------------------------------------------------------------

234: #pragma omp simd aligned(temp_r, px, py, pz, dx, dy, dz: QMC_SIMD_ALIGNMENT)

235:     for (int iat = first; iat < last; ++iat)

236:     {

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

256:     }

257:   }

0x45e720 SUBS	W16, W6, W5

0x45e724 B.LE	45e994

0x45e728 LDP	D0, D1, [X1]

0x45e72c LDR	D2, [X1, #16]

0x45e730 LDR	X8, [X2, #24]

0x45e734 SUB	W14, W6, #1

0x45e738 CMP	W14, W5

0x45e73c LDR	X10, [X2, #8]

0x45e740 LDR	X11, [X4, #24]

0x45e744 LDR	X13, [X4, #8]

0x45e748 ADD	X9, X8, X10,LSL #3

0x45e74c ADD	X10, X8, X10,LSL #4

0x45e750 ADD	X12, X11, X13,LSL #3

0x45e754 ADD	X13, X11, X13,LSL #4

0x45e758 B.GE	45e83c

0x45e75c HINT	#0

(1263) 0x45e760 LDR	D3, [X8, W5,SXTW #3]

(1263) 0x45e764 LDR	D4, [X9, W5,SXTW #3]

(1263) 0x45e768 LDP	D6, D7, [X0, #72]

(1263) 0x45e76c FSUB	D3, D3, S0

(1263) 0x45e770 FSUB	D4, D4, S1

(1263) 0x45e774 LDR	D5, [X10, W5,SXTW #3]

(1263) 0x45e778 FSUB	D5, D5, S2

(1263) 0x45e77c FMUL	D6, D6, D3

(1263) 0x45e780 FMADD	D6, D7, D4, D6

(1263) 0x45e784 LDP	D7, D16, [X0, #88]

(1263) 0x45e788 FMADD	D6, D7, D5, D6

(1263) 0x45e78c FMUL	D7, D16, D3

(1263) 0x45e790 LDP	D16, D17, [X0, #104]

(1263) 0x45e794 FMADD	D7, D16, D4, D7

(1263) 0x45e798 FMADD	D7, D17, D5, D7

(1263) 0x45e79c LDP	D16, D17, [X0, #120]

(1263) 0x45e7a0 FMUL	D3, D16, D3

(1263) 0x45e7a4 FMADD	D3, D17, D4, D3

(1263) 0x45e7a8 LDR	D4, [X0, #136]

(1263) 0x45e7ac FMADD	D3, D4, D5, D3

(1263) 0x45e7b0 FRINTA	D4, D6

(1263) 0x45e7b4 FRINTA	D5, D7

(1263) 0x45e7b8 FSUB	D4, D6, S4

(1263) 0x45e7bc FSUB	D5, D7, S5

(1263) 0x45e7c0 FRINTA	D6, D3

(1263) 0x45e7c4 FSUB	D3, D3, S6

(1263) 0x45e7c8 LDP	D6, D7, [X0]

(1263) 0x45e7cc FMUL	D6, D6, D4

(1263) 0x45e7d0 FMADD	D6, D7, D5, D6

(1263) 0x45e7d4 LDR	D7, [X0, #16]

(1263) 0x45e7d8 FMADD	D6, D3, D7, D6

(1263) 0x45e7dc STR	D6, [X11, W5,SXTW #3]

(1263) 0x45e7e0 LDP	D6, D7, [X0, #24]

(1263) 0x45e7e4 FMUL	D6, D6, D4

(1263) 0x45e7e8 FMADD	D6, D7, D5, D6

(1263) 0x45e7ec LDR	D7, [X0, #40]

(1263) 0x45e7f0 FMADD	D6, D7, D3, D6

(1263) 0x45e7f4 STR	D6, [X12, W5,SXTW #3]

(1263) 0x45e7f8 LDP	D6, D7, [X0, #48]

(1263) 0x45e7fc FMUL	D4, D6, D4

(1263) 0x45e800 FMADD	D4, D7, D5, D4

(1263) 0x45e804 LDR	D5, [X0, #64]

(1263) 0x45e808 FMADD	D3, D5, D3, D4

(1263) 0x45e80c STR	D3, [X13, W5,SXTW #3]

(1263) 0x45e810 LDR	D4, [X11, W5,SXTW #3]

(1263) 0x45e814 LDR	D5, [X12, W5,SXTW #3]

(1263) 0x45e818 FMUL	D4, D4, D4

(1263) 0x45e81c FMADD	D3, D3, D3, D4

(1263) 0x45e820 FMADD	D3, D5, D5, D3

(1263) 0x45e824 FSQRT	D3, D3

(1263) 0x45e828 STR	D3, [X3, W5,SXTW #3]

(1263) 0x45e82c ADD	W5, W5, #1

(1263) 0x45e830 CMP	W6, W5

(1263) 0x45e834 B.NE	45e760

0x45e838 B	45e994

0x45e83c CNTD	X14, ALL

0x45e840 DUP	Z0.D, Z0.D[0]

0x45e844 DUP	Z1.D, Z1.D[0]

0x45e848 DUP	Z2.D, Z2.D[0]

0x45e84c PTRUE	P1.D, ALL

0x45e850 SUBS	W15, W16, W14

0x45e854 CSEL	W15, WZR, W15, #3

0x45e858 WHILELO	P0.D, WZR, W16

0x45e85c SUB	X16, XZR, X14

(1262) 0x45e860 SBFM	X17, X5, #0, #31

(1262) 0x45e864 LDP	D6, D7, [X0, #72]

(1262) 0x45e868 DUP	Z7.D, Z7.D[0]

(1262) 0x45e86c ADD	W16, W16, W14

(1262) 0x45e870 ADD	W5, W5, W14

(1262) 0x45e874 LD1D	{Z3.D}, P0/Z, [X8, X17,LSL #3]

(1262) 0x45e878 LD1D	{Z4.D}, P0/Z, [X9, X17,LSL #3]

(1262) 0x45e87c LD1D	{Z5.D}, P0/Z, [X10, X17,LSL #3]

(1262) 0x45e880 DUP	Z6.D, Z6.D[0]

(1262) 0x45e884 FSUB	Z3.D, Z3.D, Z0.D

(1262) 0x45e888 FSUB	Z4.D, Z4.D, Z1.D

(1262) 0x45e88c FSUB	Z5.D, Z5.D, Z2.D

(1262) 0x45e890 FMUL	Z6.D, Z6.D, Z3.D

(1262) 0x45e894 FMLA	Z6.D, P1/M, Z7.D, Z4.D

(1262) 0x45e898 LDP	D7, D16, [X0, #88]

(1262) 0x45e89c DUP	Z7.D, Z7.D[0]

(1262) 0x45e8a0 FMLA	Z6.D, P1/M, Z7.D, Z5.D

(1262) 0x45e8a4 DUP	Z7.D, Z16.D[0]

(1262) 0x45e8a8 LDP	D16, D17, [X0, #104]

(1262) 0x45e8ac FMUL	Z7.D, Z7.D, Z3.D

(1262) 0x45e8b0 DUP	Z16.D, Z16.D[0]

(1262) 0x45e8b4 FMLA	Z7.D, P1/M, Z16.D, Z4.D

(1262) 0x45e8b8 DUP	Z16.D, Z17.D[0]

(1262) 0x45e8bc FMLA	Z7.D, P1/M, Z16.D, Z5.D

(1262) 0x45e8c0 LDP	D16, D17, [X0, #120]

(1262) 0x45e8c4 DUP	Z16.D, Z16.D[0]

(1262) 0x45e8c8 FMUL	Z3.D, Z16.D, Z3.D

(1262) 0x45e8cc DUP	Z16.D, Z17.D[0]

(1262) 0x45e8d0 FMLA	Z3.D, P1/M, Z16.D, Z4.D

(1262) 0x45e8d4 LDR	D4, [X0, #136]

(1262) 0x45e8d8 DUP	Z4.D, Z4.D[0]

(1262) 0x45e8dc FMLA	Z3.D, P1/M, Z4.D, Z5.D

(1262) 0x45e8e0 MOVPRFX	Z4, Z6

(1262) 0x45e8e4 FRINTA	Z4.D, P1/M, Z6.D

(1262) 0x45e8e8 MOVPRFX	Z5, Z7

(1262) 0x45e8ec FRINTA	Z5.D, P1/M, Z7.D

(1262) 0x45e8f0 FSUB	Z4.D, Z6.D, Z4.D

(1262) 0x45e8f4 FSUB	Z5.D, Z7.D, Z5.D

(1262) 0x45e8f8 MOVPRFX	Z6, Z3

(1262) 0x45e8fc FRINTA	Z6.D, P1/M, Z3.D

(1262) 0x45e900 FSUB	Z3.D, Z3.D, Z6.D

(1262) 0x45e904 LDP	D6, D7, [X0]

(1262) 0x45e908 DUP	Z7.D, Z7.D[0]

(1262) 0x45e90c DUP	Z6.D, Z6.D[0]

(1262) 0x45e910 FMUL	Z6.D, Z6.D, Z4.D

(1262) 0x45e914 FMLA	Z6.D, P1/M, Z7.D, Z5.D

(1262) 0x45e918 LDR	D7, [X0, #16]

(1262) 0x45e91c DUP	Z7.D, Z7.D[0]

(1262) 0x45e920 FMLA	Z6.D, P1/M, Z3.D, Z7.D

(1262) 0x45e924 ST1D	{Z6.D}, P0, [X11, X17,LSL #3]

(1262) 0x45e928 LDP	D6, D7, [X0, #24]

(1262) 0x45e92c DUP	Z7.D, Z7.D[0]

(1262) 0x45e930 DUP	Z6.D, Z6.D[0]

(1262) 0x45e934 FMUL	Z6.D, Z6.D, Z4.D

(1262) 0x45e938 FMLA	Z6.D, P1/M, Z7.D, Z5.D

(1262) 0x45e93c LDR	D7, [X0, #40]

(1262) 0x45e940 DUP	Z7.D, Z7.D[0]

(1262) 0x45e944 FMLA	Z6.D, P1/M, Z7.D, Z3.D

(1262) 0x45e948 ST1D	{Z6.D}, P0, [X12, X17,LSL #3]

(1262) 0x45e94c LDP	D6, D7, [X0, #48]

(1262) 0x45e950 DUP	Z6.D, Z6.D[0]

(1262) 0x45e954 FMUL	Z4.D, Z6.D, Z4.D

(1262) 0x45e958 DUP	Z6.D, Z7.D[0]

(1262) 0x45e95c FMLA	Z4.D, P1/M, Z6.D, Z5.D

(1262) 0x45e960 LDR	D5, [X0, #64]

(1262) 0x45e964 DUP	Z5.D, Z5.D[0]

(1262) 0x45e968 FMAD	Z3.D, P1/M, Z5.D, Z4.D

(1262) 0x45e96c ST1D	{Z3.D}, P0, [X13, X17,LSL #3]

(1262) 0x45e970 LD1D	{Z4.D}, P0/Z, [X11, X17,LSL #3]

(1262) 0x45e974 LD1D	{Z5.D}, P0/Z, [X12, X17,LSL #3]

(1262) 0x45e978 FMUL	Z4.D, Z4.D, Z4.D

(1262) 0x45e97c FMAD	Z3.D, P1/M, Z3.D, Z4.D

(1262) 0x45e980 FMLA	Z3.D, P1/M, Z5.D, Z5.D

(1262) 0x45e984 FSQRT	Z3.D, P1/M, Z3.D

(1262) 0x45e988 ST1D	{Z3.D}, P0, [X3, X17,LSL #3]

(1262) 0x45e98c WHILELO	P0.D, W16, W15

(1262) 0x45e990 B.MI	45e860

0x45e994 RET

0x45e998 HINT	#0

0x45e99c HINT	#0

Coverage (%)	Name	Source Location	Module
►93.98+	qmcplusplus::ParticleSet::comp[...]	stl_vector.h:993	exec
○	main.omp_outlined.62	miniqmc.cpp:437	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►4.33+	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:993	exec
○	main.omp_outlined	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.66+	qmcplusplus::ParticleSet::comp[...]	stl_vector.h:993	exec
○	main.omp_outlined.62	miniqmc.cpp:437	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:409	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:172	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	ParticleBConds3DSoa.h:234-257
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:234-257.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.25 to 2.00 cycles (1.62x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 41% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.25 to 3.00 cycles (1.08x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	29
nb uops	26
loop length	116
used w registers	6
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	3
used q registers	0
used v registers	0
used z registers	3
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.25	3.25	3.25	3.25	1.50	1.50	0.00	0.00	2.00	2.00	2.00	0.00	0.00
cycles	2.00	2.00	3.25	3.25	3.25	3.25	1.50	1.50	0.00	0.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.25
Dispatch	3.25
Overall L1	3.25

Vectorization ratios

all	23%
load	16%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

all	41%
load	29%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	70%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.25 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.25 to 2.00 cycles (1.63x speedup).

ASM code

In the binary file, the address of the function is: 45e720

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUBS W16, W6, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 45e994 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D0, D1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR D2, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X8, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W14, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W14, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LDR X10, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X9, X8, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X8, X10,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X11, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X11, X13,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.GE 45e83c <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
B 45e994 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
DUP Z0.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, Z1.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z2.D, Z2.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUBS W15, W16, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W15, WZR, W15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
SUB X16, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	ParticleBConds3DSoa.h:234-257
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:234-257.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.25 to 2.00 cycles (1.62x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	29
nb uops	26
loop length	116
used w registers	6
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	3
used q registers	0
used v registers	0
used z registers	3
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.25	3.25	3.25	3.25	1.50	1.50	0.00	0.00	2.00	2.00	2.00	0.00	0.00
cycles	2.00	2.00	3.25	3.25	3.25	3.25	1.50	1.50	0.00	0.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.25
Dispatch	3.25
Overall L1	3.25

Vectorization ratios

all	23%
load	16%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

all	41%
load	29%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	70%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.25 cycles.

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 45e720

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUBS W16, W6, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 45e994 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D0, D1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR D2, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X8, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W14, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W14, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LDR X10, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X9, X8, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X8, X10,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X11, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X11, X13,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.GE 45e83c <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
B 45e994 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
DUP Z0.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, Z1.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z2.D, Z2.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUBS W15, W16, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W15, WZR, W15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
SUB X16, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer–	1.47	2.24
○Loop 1262 - ParticleBConds3DSoa.h:235-255 - exec	1.47	2.21
○Loop 1263 - ParticleBConds3DSoa.h:234-255 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code