OV - exec - Function qmcplusplus::WaveFunction::evalGrad(qmcplusplus::ParticleSet&, int)

	Function: qmcplusplus::WaveFunction::evalGrad(qmcplusplus::ParticleSet&, int)	Module: exec	Source: WaveFunction.cpp:182-190 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 94 - 94

--------------------------------------------------------------------------------

94:     (const_cast<T1&>(a) += b);

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp: 182 - 190

--------------------------------------------------------------------------------

182: {

183:   posT grad_iat = (iat < nelup ? Det_up->evalGrad(P, iat) : Det_dn->evalGrad(P, iat));

184:

185:   for (size_t i = 0; i < Jastrows.size(); i++)

186:   {

187:     ScopedTimer local_timer(jastrow_timers[i]);

188:     grad_iat += Jastrows[i]->evalGrad(P, iat);

189:   }

190:   return grad_iat;

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/refwrap.h: 351 - 351

--------------------------------------------------------------------------------

351:       { return *_M_data; }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h: 993 - 1131

--------------------------------------------------------------------------------

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1131: 	return *(this->_M_impl._M_start + __n);

0x4196d0 STP	D13, D12, [SP, #912]!

0x4196d4 STP	D11, D10, [SP, #16]

0x4196d8 STP	D9, D8, [SP, #32]

0x4196dc STP	X29, X30, [SP, #48]

0x4196e0 STR	X23, [SP, #64]

0x4196e4 STP	X22, X21, [SP, #80]

0x4196e8 STP	X20, X19, [SP, #96]

0x4196ec ADD	X29, SP, #48

0x4196f0 LDR	W8, [X0, #52]

0x4196f4 ADD	X9, X0, #8

0x4196f8 ORR	X21, XZR, X0

0x4196fc ORR	W19, WZR, W2

0x419700 ORR	X20, XZR, X1

0x419704 CMP	W2, W8

0x419708 CSEL	X8, X0, X9, #11

0x41970c LDR	X0, [X8]

0x419710 LDR	X8, [X0]

0x419714 LDR	X8, [X8, #24]

0x419718 BLR	X8

0x41971c LDP	X9, X8, [X21, #16]

0x419720 FMOV	D10, D0

0x419724 FMOV	D9, D1

0x419728 FMOV	D8, D2

0x41972c CMP	X8, X9

0x419730 B.EQ	4197a0

0x419734 ORR	X23, XZR, XZR

0x419738 HINT	#0

0x41973c HINT	#0

(114) 0x419740 LDR	X8, [X21, #88]

(114) 0x419744 LDR	X22, [X8, X23,LSL #3]

(114) 0x419748 ORR	X0, XZR, X22

(114) 0x41974c BL	474220

(114) 0x419750 LDR	X8, [X21, #16]

(114) 0x419754 LDR	X0, [X8, X23,LSL #3]

(114) 0x419758 LDR	X8, [X0]

(114) 0x41975c LDR	X8, [X8, #24]

(114) 0x419760 ORR	X1, XZR, X20

(114) 0x419764 ORR	W2, WZR, W19

(114) 0x419768 BLR	X8

(114) 0x41976c FMOV	D11, D0

(114) 0x419770 FMOV	D12, D1

(114) 0x419774 FMOV	D13, D2

(114) 0x419778 ORR	X0, XZR, X22

(114) 0x41977c BL	474340

(114) 0x419780 LDP	X9, X8, [X21, #16]

(114) 0x419784 FADD	D8, D13, D8

(114) 0x419788 FADD	D9, D12, D9

(114) 0x41978c FADD	D10, D11, D10

(114) 0x419790 ADD	X23, X23, #1

(114) 0x419794 SUB	X8, X8, X9

(114) 0x419798 CMP	X23, X8,ASR #3

(114) 0x41979c B.CC	419740

0x4197a0 FMOV	D0, D10

0x4197a4 FMOV	D1, D9

0x4197a8 FMOV	D2, D8

0x4197ac LDP	D9, D8, [SP, #32]

0x4197b0 LDP	D11, D10, [SP, #16]

0x4197b4 LDP	X20, X19, [SP, #96]

0x4197b8 LDR	X23, [SP, #64]

0x4197bc LDP	X22, X21, [SP, #80]

0x4197c0 LDP	X29, X30, [SP, #48]

0x4197c4 LDP	D13, D12, [SP], #112

0x4197c8 RET

0x4197cc ORR	X19, XZR, X0

0x4197d0 ORR	X0, XZR, X22

0x4197d4 BL	474340

0x4197d8 ORR	X0, XZR, X19

0x4197dc BL	410490

0x4197e0 BL	4158a0

0x4197e4 BL	4158a0

0x4197e8 HINT	#0

0x4197ec HINT	#0

Coverage (%)	Name	Source Location	Module
►96.24+	main.omp_outlined.62	miniqmc.cpp:433	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.82+	main.omp_outlined.62	miniqmc.cpp:433	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:409	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:172	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	WaveFunction.cpp:182-190
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:94
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:182-190
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/refwrap.h:351
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h:993,1131

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 3.17 cycles (2.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 35% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 6.50 to 2.25 cycles (2.89x speedup).

Details

24% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
42% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__clang_call_terminate: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249
unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:183
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	48
nb uops	44
loop length	192
used w registers	4
used x registers	12
used b registers	0
used h registers	0
used s registers	1
used d registers	9
used q registers	0
used v registers	0
used z registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	4.75	4.75	4.75	4.75	2.25	2.25	2.25	2.25	6.50	6.17	6.33	2.00	2.00
cycles	3.50	3.50	4.75	4.75	4.75	4.75	2.25	2.25	2.25	2.25	6.50	6.17	6.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.50
Dispatch	6.50
Overall L1	6.50

Vectorization ratios

INT

all	31%
load	50%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	24%
load	50%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	38%
load	45%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	35%
load	45%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.50 cycles. At this rate:

0% of peak load performance is reached (0.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4196d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D13, D12, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W8, [X0, #52]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W19, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W2, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL X8, X0, X9, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BLR X8	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
FMOV D10, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D9, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D8, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 4197a0 <_ZN11qmcplusplus12WaveFunction8evalGradERNS_11ParticleSetEi+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
FMOV D0, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D1, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D2, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D13, D12, [SP], #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 474340 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410490 <@plt_start@+0x470>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4158a0 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4158a0 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	WaveFunction.cpp:182-190
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:94
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:182-190
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/refwrap.h:351
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h:993,1131

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 3.17 cycles (2.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

24% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
42% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

__clang_call_terminate: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249
unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:183
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	48
nb uops	44
loop length	192
used w registers	4
used x registers	12
used b registers	0
used h registers	0
used s registers	1
used d registers	9
used q registers	0
used v registers	0
used z registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	4.75	4.75	4.75	4.75	2.25	2.25	2.25	2.25	6.50	6.17	6.33	2.00	2.00
cycles	3.50	3.50	4.75	4.75	4.75	4.75	2.25	2.25	2.25	2.25	6.50	6.17	6.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.50
Dispatch	6.50
Overall L1	6.50

Vectorization ratios

INT

all	31%
load	50%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	24%
load	50%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	38%
load	45%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	35%
load	45%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.50 cycles. At this rate:

0% of peak load performance is reached (0.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4196d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D13, D12, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W8, [X0, #52]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W19, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W2, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL X8, X0, X9, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BLR X8	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
FMOV D10, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D9, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D8, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 4197a0 <_ZN11qmcplusplus12WaveFunction8evalGradERNS_11ParticleSetEi+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
FMOV D0, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D1, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D2, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D13, D12, [SP], #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 474340 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410490 <@plt_start@+0x470>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4158a0 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4158a0 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼qmcplusplus::WaveFunction::evalGrad(qmcplusplus::ParticleSet&, int)–	0.01	0.02
○Loop 114 - WaveFunction.cpp:185-188 - exec	0.01	0.02

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code