OV - exec - Loop 801

	Loop Id: 801	Module: exec	Source: einspline_spo_ref.hpp:223-227 [...]	Coverage: 0.31%

0x43aca0 LDR	X11, [X22, #784]    [11]

0x43aca4 MUL	X13, X9, X8

0x43aca8 LDR	X11, [X11, X13]    [9]

0x43acac ADD	X13, X9, X9,LSL #2

0x43acb0 LDR	D0, [X11, X12]    [8]

0x43acb4 LDR	X11, [X21, #24]    [10]

0x43acb8 STR	D0, [X11, X14,LSL #3]    [7]

0x43acbc LDR	X11, [X22, #808]    [11]

0x43acc0 ADD	X11, X11, X13,LSL #3

0x43acc4 LDR	X16, [X11, #24]    [6]

0x43acc8 LDR	X11, [X11, #8]    [6]

0x43accc ADD	X16, X16, X12

0x43acd0 SBFM	X17, X11, #61, #31

0x43acd4 SBFM	X11, X11, #60, #31

0x43acd8 LDR	D0, [X16]    [12]

0x43acdc LDR	D1, [X16, X17]    [12]

0x43ace0 LDR	D2, [X16, X11]    [12]

0x43ace4 LDR	X11, [X20, #24]    [5]

0x43ace8 ADD	X11, X11, X15

0x43acec ADD	X15, X15, #24

0x43acf0 STP	D0, D1, [X11]    [4]

0x43acf4 STR	D2, [X11, #16]    [4]

0x43acf8 LDR	X11, [X22, #832]    [11]

0x43acfc ADD	X11, X11, X13,LSL #3

0x43ad00 LDR	W13, [X22, #8]    [11]

0x43ad04 LDR	X11, [X11, #24]    [3]

0x43ad08 LDR	D0, [X11, X12]    [2]

0x43ad0c LDR	X11, [X19, #24]    [13]

0x43ad10 ADD	X12, X12, #8

0x43ad14 STR	D0, [X11, X14,LSL #3]    [1]

0x43ad18 LDR	W11, [X22, #64]    [11]

0x43ad1c ADD	X14, X14, #1

0x43ad20 MUL	W16, W11, W10

0x43ad24 CMP	W13, W16

0x43ad28 CSEL	W16, W13, W16, #11

0x43ad2c CMP	X14, W16,SXTW

0x43ad30 B.LT	43aca0

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 145 - 145

--------------------------------------------------------------------------------

145:       X[i] = base[i * offset];

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 223 - 227

--------------------------------------------------------------------------------

223:       for (int j = first; j < std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize); j++)

224:       {

225:         psi_v[j]   = psi[i][j - first];

226:         dpsi_v[j]  = grad[i][j - first];

227:         d2psi_v[j] = hess[i].data(0)[j - first];

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 223

--------------------------------------------------------------------------------

223:     return X[i];

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 271

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

[...]

271:   inline T* restrict data(size_t i) { return myData + i * nGhosts; }

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h: 1131 - 1131

--------------------------------------------------------------------------------

1131: 	return *(this->_M_impl._M_start + __n);

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_algobase.h: 238 - 238

--------------------------------------------------------------------------------

238:       if (__b < __a)

Coverage (%)	Name	Source Location	Module
►82.43+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:993	exec
○	main.omp_outlined.62	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►7.94+	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:210	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►7.94+	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:210	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.46+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:993	exec
○	main.omp_outlined.62	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:409	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:172	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.51
Bottlenecks	P10, P11, P12,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source	TinyVector.h:145-145,einspline_spo_ref.hpp:223-227,OhmmsVector.h:223-223,VectorSoAContainer.h:231-231,VectorSoAContainer.h:271-271,stl_vector.h:1131-1131,stl_algobase.h:238-238
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	1.33
Front-end cycles	4.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.75
P5 cycles	3.75
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	7.00
P11 cycles	7.00
P12 cycles	7.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.86
Bytes prefetched	0.00
Bytes loaded	6.00
Bytes stored	0.00
Stride 0	4.00
Stride 1	0.00
Stride n	4.00
Stride unknown	5.00
Stride indirect	0.00
Vectorization ratio all	9.09
Vectorization ratio load	0.00
Vectorization ratio store	25.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	26.14
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	31.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	2.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.51
Bottlenecks	P10, P11, P12,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source	TinyVector.h:145-145,einspline_spo_ref.hpp:223-227,OhmmsVector.h:223-223,VectorSoAContainer.h:231-231,VectorSoAContainer.h:271-271,stl_vector.h:1131-1131,stl_algobase.h:238-238
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	1.33
Front-end cycles	4.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.75
P5 cycles	3.75
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	7.00
P11 cycles	7.00
P12 cycles	7.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.86
Bytes prefetched	0.00
Bytes loaded	6.00
Bytes stored	0.00
Stride 0	4.00
Stride 1	0.00
Stride n	4.00
Stride unknown	5.00
Stride indirect	0.00
Vectorization ratio all	9.09
Vectorization ratio load	0.00
Vectorization ratio store	25.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	26.14
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	31.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:223-227
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:223-227
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,271
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h:1131
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_algobase.h:238

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 3.00 cycles (2.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 26% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.00 to 1.33 cycles (5.25x speedup).

Details

9% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 5 occurrence(s)
Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 6 bytes.

General properties

nb instructions	37
nb uops	37
loop length	148
used w registers	4
used x registers	13
used b registers	0
used h registers	0
used s registers	0
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.63 cycles
front end	4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.75	3.75	3.75	3.75	2.00	2.00	0.00	0.00	7.00	7.00	7.00	0.00	0.00
cycles	0.50	0.50	3.75	3.75	3.75	3.75	2.00	2.00	0.00	0.00	7.00	7.00	7.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.63
Dispatch	7.00
Data deps.	1.00
Overall L1	7.00

Vectorization ratios

all	9%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	26%
load	25%
store	31%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

0% of peak load performance is reached (0.86 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 43aca0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR X11, [X22, #784]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL X13, X9, X8	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
LDR X11, [X11, X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X13, X9, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D0, [X11, X12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR X11, [X21, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
STR D0, [X11, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
LDR X11, [X22, #808]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X11, X11, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X11, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X11, [X11, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X16, X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SBFM X17, X11, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SBFM X11, X11, #60, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D0, [X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D1, [X16, X17]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D2, [X16, X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR X11, [X20, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X11, X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X15, X15, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP D0, D1, [X11]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR D2, [X11, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
LDR X11, [X22, #832]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X11, X11, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR W13, [X22, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X11, [X11, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D0, [X11, X12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR X11, [X19, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR D0, [X11, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
LDR W11, [X22, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MUL W16, W11, W10	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
CMP W13, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W16, W13, W16, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X14, W16,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
B.LT 43aca0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:223-227
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:223-227
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,271
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_vector.h:1131
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/stl_algobase.h:238

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 3.00 cycles (2.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

9% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 5 occurrence(s)
Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 6 bytes.

General properties

nb instructions	37
nb uops	37
loop length	148
used w registers	4
used x registers	13
used b registers	0
used h registers	0
used s registers	0
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.63 cycles
front end	4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.75	3.75	3.75	3.75	2.00	2.00	0.00	0.00	7.00	7.00	7.00	0.00	0.00
cycles	0.50	0.50	3.75	3.75	3.75	3.75	2.00	2.00	0.00	0.00	7.00	7.00	7.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.63
Dispatch	7.00
Data deps.	1.00
Overall L1	7.00

Vectorization ratios

all	9%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	26%
load	25%
store	31%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

0% of peak load performance is reached (0.86 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 43aca0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR X11, [X22, #784]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL X13, X9, X8	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
LDR X11, [X11, X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X13, X9, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D0, [X11, X12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR X11, [X21, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
STR D0, [X11, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
LDR X11, [X22, #808]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X11, X11, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X11, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X11, [X11, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X16, X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SBFM X17, X11, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SBFM X11, X11, #60, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D0, [X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D1, [X16, X17]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D2, [X16, X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR X11, [X20, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X11, X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X15, X15, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP D0, D1, [X11]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR D2, [X11, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
LDR X11, [X22, #832]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X11, X11, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR W13, [X22, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X11, [X11, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D0, [X11, X12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR X11, [X19, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR D0, [X11, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
LDR W11, [X22, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MUL W16, W11, W10	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
CMP W13, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W16, W13, W16, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X14, W16,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
B.LT 43aca0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code