OV - exec - Function miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector<double, std::allocator<double> >&)

	Function: miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios( ...	Module: exec	Source: TwoBodyJastrowRef.h:105-132 [...]	Coverage (incl. loops): 1.42% \| (excl. loops): 0.00%

/usr/include/c++/14/bits/refwrap.h: 351 - 351

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351:       { return *_M_data; }

/usr/include/c++/14/bits/stl_vector.h: 993 - 1147

--------------------------------------------------------------------------------

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1147:       operator[](size_type __n) const _GLIBCXX_NOEXCEPT

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 249

--------------------------------------------------------------------------------

223:     return X[i];

[...]

249:   inline const_pointer data() const { return X; }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 105 - 132

--------------------------------------------------------------------------------

105:   void evaluateRatios(VirtualParticleSet& VP, std::vector<ValueType>& ratios)

106:   {

107:     for (int k = 0; k < ratios.size(); ++k)

108:       ratios[k] = std::exp(Uat[VP.refPtcl] - computeU(VP.getRefPS(), VP.refPtcl, VP.getDistTableAB(myTableID).getDistRow(k).data()));

109:   }

[...]

125:     valT curUat(0);

126:     const int igt = P.GroupID[iat] * NumGroups;

127:     for (int jg = 0; jg < NumGroups; ++jg)

128:     {

129:       const FuncType& f2(*F[igt + jg]);

130:       int iStart = P.first(jg);

131:       int iEnd   = P.last(jg);

132:       curUat += f2.evaluateV(iat, iStart, iEnd, dist, DistCompressed.data());

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 313 - 316

--------------------------------------------------------------------------------

313:   inline int first(int igroup) const { return (*group_offsets_)[igroup]; }

314:

315:   ///return the last index of a group i

316:   inline int last(int igroup) const { return (*group_offsets_)[igroup + 1]; }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 231 - 260

--------------------------------------------------------------------------------

231:   ASSUME_ALIGNED(distArrayCompressed);

232:   int iCount       = 0;

233:   const int iLimit = iEnd - iStart;

234:

235: #pragma vector always

236:   for (int jat = 0; jat < iLimit; jat++)

237:   {

238:     real_type r = distArray[jat];

239:     // pick the distances smaller than the cutoff and avoid the reference atom

240:     if (r < cutoff_radius && iStart + jat != iat)

241:       distArrayCompressed[iCount++] = distArray[jat];

242:   }

243:

244:   real_type d = 0.0;

245:   //#pragma omp simd reduction(+:d)

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

/usr/include/c++/14/optional: 991 - 993

--------------------------------------------------------------------------------

991: 	if (this->_M_is_engaged())

992: 	  return this->_M_get();

993: 	__throw_bad_optional_access();

0x42be80 STP	X29, X30, [SP, #864]!

0x42be84 ADD	X29, SP, #0

0x42be88 STP	X21, X22, [SP, #32]

0x42be8c ORR	X21, XZR, X2

0x42be90 STP	X25, X26, [SP, #64]

0x42be94 ORR	X26, XZR, X0

0x42be98 LDR	X2, [X2]

0x42be9c LDR	X0, [X21, #8]

0x42bea0 CMP	X2, X0

0x42bea4 B.EQ	42c418

0x42bea8 MOVZ	X25, #0

0x42beac ADD	X22, X1, #656

0x42beb0 STP	X19, X20, [SP, #16]

0x42beb4 ORR	X19, XZR, X1

0x42beb8 MOVZ	X20, #0

0x42bebc STP	X23, X24, [SP, #48]

0x42bec0 ADD	X23, X26, #192

0x42bec4 STP	X27, X28, [SP, #80]

0x42bec8 STP	D8, D9, [SP, #96]

0x42becc STP	D10, D11, [SP, #112]

0x42bed0 STP	D12, D13, [SP, #128]

0x42bed4 STP	D14, D15, [SP, #144]

0x42bed8 HINT	#0

0x42bedc HINT	#0

(293) 0x42bee0 LDR	X1, [X23, #24]

(293) 0x42bee4 LDR	W24, [X19, #672]

(293) 0x42bee8 LDRB	W3, [X22, #8]

(293) 0x42beec LDR	D15, [X1, W24,SXTW #3]

(293) 0x42bef0 SBFM	X28, X24, #0, #31

(293) 0x42bef4 TBZ	W3, #0, 42c428

(293) 0x42bef8 ORR	X0, XZR, X19

(293) 0x42befc LDR	X27, [X19, #656]

(293) 0x42bf00 LDR	W1, [X26, #584]

(293) 0x42bf04 BL	48ffa0

(293) 0x42bf08 LDR	X5, [X0, #72]

(293) 0x42bf0c ADD	X4, X25, X25,LSL #2

(293) 0x42bf10 LDR	X7, [X27, #24]

(293) 0x42bf14 LDR	X13, [X26, #160]

(293) 0x42bf18 ADD	X6, X5, X4

(293) 0x42bf1c LDR	X14, [X6, #24]

(293) 0x42bf20 LDR	W8, [X7, X28,LSL #2]

(293) 0x42bf24 MUL	W9, W8, W13

(293) 0x42bf28 CBZ	X13, 42c3d8

(293) 0x42bf2c LDR	X11, [X27, #616]

(293) 0x42bf30 MOVI	D2, #0

(293) 0x42bf34 MOVZ	X8, #0

(293) 0x42bf38 CNTW	X7, ALL

(293) 0x42bf3c PTRUE	P7.B, ALL

(293) 0x42bf40 LDR	X4, [X26, #464]

(293) 0x42bf44 LDR	X10, [X26, #512]

(293) 0x42bf48 ADD	X12, X10, W9,SXTW #3

(293) 0x42bf4c LDR	X11, [X11, #24]

(293) 0x42bf50 ADDVL	X6, X4, #1

(293) 0x42bf54 HINT	#0

(293) 0x42bf58 HINT	#0

(293) 0x42bf5c HINT	#0

  (294) 0x42bf60 LDR	X16, [X12, X8,LSL #3]

  (294) 0x42bf64 LDR	W17, [X11, X8,LSL #2]

  (294) 0x42bf68 ADD	X8, X8, #1

  (294) 0x42bf6c LDR	W18, [X11, X8,LSL #2]

  (294) 0x42bf70 CMP	W18, W17

  (294) 0x42bf74 B.LE	42c3cc

  (294) 0x42bf78 SUB	W30, W18, W17

  (294) 0x42bf7c SBFM	X15, X17, #61, #31

  (294) 0x42bf80 LDR	D31, [X16, #8]

  (294) 0x42bf84 ANDS	W3, W30, #0x7

  (294) 0x42bf88 ADD	X0, X14, X15

  (294) 0x42bf8c MOVZ	W2, #0

  (294) 0x42bf90 ORR	W30, WZR, W17

  (294) 0x42bf94 B.EQ	42c0cc

  (294) 0x42bf98 CMP	W3, #1

  (294) 0x42bf9c B.EQ	42c0a0

  (294) 0x42bfa0 CMP	W3, #2

  (294) 0x42bfa4 B.EQ	42c07c

  (294) 0x42bfa8 CMP	W3, #3

  (294) 0x42bfac B.EQ	42c058

  (294) 0x42bfb0 CMP	W3, #4

  (294) 0x42bfb4 B.EQ	42c034

  (294) 0x42bfb8 CMP	W3, #5

  (294) 0x42bfbc B.EQ	42c010

  (294) 0x42bfc0 CMP	W3, #6

  (294) 0x42bfc4 B.EQ	42bfec

  (294) 0x42bfc8 LDR	D30, [X14, X15]

  (294) 0x42bfcc FCMPE	D31, D30

  (294) 0x42bfd0 B.LS	42bfe4

  (294) 0x42bfd4 CMP	W24, W17

  (294) 0x42bfd8 B.EQ	42bfe4

  (294) 0x42bfdc MOVZ	W2, #1

  (294) 0x42bfe0 STR	D30, [X4]

  (294) 0x42bfe4 ADD	X0, X0, #8

  (294) 0x42bfe8 ADD	W30, W17, #1

  (294) 0x42bfec LDR	D0, [X0]

  (294) 0x42bff0 FCMPE	D31, D0

  (294) 0x42bff4 B.LS	42c008

  (294) 0x42bff8 CMP	W24, W30

  (294) 0x42bffc B.EQ	42c008

  (294) 0x42c000 STR	D0, [X4, W2,UXTW #3]

  (294) 0x42c004 ADD	W2, W2, #1

  (294) 0x42c008 ADD	X0, X0, #8

  (294) 0x42c00c ADD	W30, W30, #1

  (294) 0x42c010 LDR	D1, [X0]

  (294) 0x42c014 FCMPE	D31, D1

  (294) 0x42c018 B.LS	42c02c

  (294) 0x42c01c CMP	W24, W30

  (294) 0x42c020 B.EQ	42c02c

  (294) 0x42c024 STR	D1, [X4, W2,UXTW #3]

  (294) 0x42c028 ADD	W2, W2, #1

  (294) 0x42c02c ADD	X0, X0, #8

  (294) 0x42c030 ADD	W30, W30, #1

  (294) 0x42c034 LDR	D3, [X0]

  (294) 0x42c038 FCMPE	D31, D3

  (294) 0x42c03c B.LS	42c050

  (294) 0x42c040 CMP	W24, W30

  (294) 0x42c044 B.EQ	42c050

  (294) 0x42c048 STR	D3, [X4, W2,UXTW #3]

  (294) 0x42c04c ADD	W2, W2, #1

  (294) 0x42c050 ADD	X0, X0, #8

  (294) 0x42c054 ADD	W30, W30, #1

  (294) 0x42c058 LDR	D4, [X0]

  (294) 0x42c05c FCMPE	D31, D4

  (294) 0x42c060 B.LS	42c074

  (294) 0x42c064 CMP	W24, W30

  (294) 0x42c068 B.EQ	42c074

  (294) 0x42c06c STR	D4, [X4, W2,UXTW #3]

  (294) 0x42c070 ADD	W2, W2, #1

  (294) 0x42c074 ADD	X0, X0, #8

  (294) 0x42c078 ADD	W30, W30, #1

  (294) 0x42c07c LDR	D5, [X0]

  (294) 0x42c080 FCMPE	D31, D5

  (294) 0x42c084 B.LS	42c098

  (294) 0x42c088 CMP	W24, W30

  (294) 0x42c08c B.EQ	42c098

  (294) 0x42c090 STR	D5, [X4, W2,UXTW #3]

  (294) 0x42c094 ADD	W2, W2, #1

  (294) 0x42c098 ADD	X0, X0, #8

  (294) 0x42c09c ADD	W30, W30, #1

  (294) 0x42c0a0 LDR	D6, [X0]

  (294) 0x42c0a4 FCMPE	D31, D6

  (294) 0x42c0a8 B.LS	42c0bc

  (294) 0x42c0ac CMP	W24, W30

  (294) 0x42c0b0 B.EQ	42c0bc

  (294) 0x42c0b4 STR	D6, [X4, W2,UXTW #3]

  (294) 0x42c0b8 ADD	W2, W2, #1

  (294) 0x42c0bc ADD	W30, W30, #1

  (294) 0x42c0c0 ADD	X0, X0, #8

  (294) 0x42c0c4 CMP	W18, W30

  (294) 0x42c0c8 B.EQ	42c1dc

    (295) 0x42c0cc LDR	D7, [X0]

    (295) 0x42c0d0 FCMPE	D31, D7

    (295) 0x42c0d4 B.LS	42c0e8

    (295) 0x42c0d8 CMP	W24, W30

    (295) 0x42c0dc B.EQ	42c0e8

    (295) 0x42c0e0 STR	D7, [X4, W2,UXTW #3]

    (295) 0x42c0e4 ADD	W2, W2, #1

    (295) 0x42c0e8 LDR	D8, [X0, #8]

    (295) 0x42c0ec ADD	W28, W30, #1

    (295) 0x42c0f0 ADD	X0, X0, #8

    (295) 0x42c0f4 FCMPE	D31, D8

    (295) 0x42c0f8 B.LS	42c10c

    (295) 0x42c0fc CMP	W24, W28

    (295) 0x42c100 B.EQ	42c10c

    (295) 0x42c104 STR	D8, [X4, W2,UXTW #3]

    (295) 0x42c108 ADD	W2, W2, #1

    (295) 0x42c10c LDR	D9, [X0, #8]

    (295) 0x42c110 ADD	W1, W28, #1

    (295) 0x42c114 FCMPE	D31, D9

    (295) 0x42c118 B.LS	42c12c

    (295) 0x42c11c CMP	W24, W1

    (295) 0x42c120 B.EQ	42c12c

    (295) 0x42c124 STR	D9, [X4, W2,UXTW #3]

    (295) 0x42c128 ADD	W2, W2, #1

    (295) 0x42c12c LDR	D10, [X0, #16]

    (295) 0x42c130 ADD	W27, W28, #2

    (295) 0x42c134 FCMPE	D31, D10

    (295) 0x42c138 B.LS	42c14c

    (295) 0x42c13c CMP	W24, W27

    (295) 0x42c140 B.EQ	42c14c

    (295) 0x42c144 STR	D10, [X4, W2,UXTW #3]

    (295) 0x42c148 ADD	W2, W2, #1

    (295) 0x42c14c LDR	D11, [X0, #24]

    (295) 0x42c150 ADD	W5, W28, #3

    (295) 0x42c154 FCMPE	D31, D11

    (295) 0x42c158 B.LS	42c16c

    (295) 0x42c15c CMP	W24, W5

    (295) 0x42c160 B.EQ	42c16c

    (295) 0x42c164 STR	D11, [X4, W2,UXTW #3]

    (295) 0x42c168 ADD	W2, W2, #1

    (295) 0x42c16c LDR	D12, [X0, #32]

    (295) 0x42c170 ADD	W9, W28, #4

    (295) 0x42c174 FCMPE	D31, D12

    (295) 0x42c178 B.LS	42c18c

    (295) 0x42c17c CMP	W24, W9

    (295) 0x42c180 B.EQ	42c18c

    (295) 0x42c184 STR	D12, [X4, W2,UXTW #3]

    (295) 0x42c188 ADD	W2, W2, #1

    (295) 0x42c18c LDR	D13, [X0, #40]

    (295) 0x42c190 ADD	W10, W28, #5

    (295) 0x42c194 FCMPE	D31, D13

    (295) 0x42c198 B.LS	42c1ac

    (295) 0x42c19c CMP	W24, W10

    (295) 0x42c1a0 B.EQ	42c1ac

    (295) 0x42c1a4 STR	D13, [X4, W2,UXTW #3]

    (295) 0x42c1a8 ADD	W2, W2, #1

    (295) 0x42c1ac LDR	D14, [X0, #48]

    (295) 0x42c1b0 ADD	W17, W28, #6

    (295) 0x42c1b4 FCMPE	D31, D14

    (295) 0x42c1b8 B.LS	42c1cc

    (295) 0x42c1bc CMP	W24, W17

    (295) 0x42c1c0 B.EQ	42c1cc

    (295) 0x42c1c4 STR	D14, [X4, W2,UXTW #3]

    (295) 0x42c1c8 ADD	W2, W2, #1

    (295) 0x42c1cc ADD	W30, W28, #7

    (295) 0x42c1d0 ADD	X0, X0, #56

    (295) 0x42c1d4 CMP	W18, W30

    (295) 0x42c1d8 B.NE	42c0cc

  (294) 0x42c1dc CBZ	W2, 42c3cc

  (294) 0x42c1e0 ADD	X18, X16, #568

  (294) 0x42c1e4 LD1RD	{Z4.D}, P7/Z, [X16, #3]

  (294) 0x42c1e8 LD1RD	{Z5.D}, P7/Z, [X16, #4]

  (294) 0x42c1ec LD1RD	{Z6.D}, P7/Z, [X16, #5]

  (294) 0x42c1f0 LD1RD	{Z7.D}, P7/Z, [X16, #6]

  (294) 0x42c1f4 LD1RD	{Z16.D}, P7/Z, [X16, #7]

  (294) 0x42c1f8 LD1RD	{Z17.D}, P7/Z, [X16, #8]

  (294) 0x42c1fc LD1RD	{Z18.D}, P7/Z, [X16, #9]

  (294) 0x42c200 LD1RD	{Z19.D}, P7/Z, [X16, #10]

  (294) 0x42c204 LD1RD	{Z20.D}, P7/Z, [X16, #11]

  (294) 0x42c208 LD1RD	{Z21.D}, P7/Z, [X16, #12]

  (294) 0x42c20c LD1RD	{Z22.D}, P7/Z, [X16, #13]

  (294) 0x42c210 LD1RD	{Z23.D}, P7/Z, [X16, #14]

  (294) 0x42c214 LD1RD	{Z24.D}, P7/Z, [X16, #15]

  (294) 0x42c218 LD1RD	{Z25.D}, P7/Z, [X16, #16]

  (294) 0x42c21c LD1RD	{Z26.D}, P7/Z, [X16, #17]

  (294) 0x42c220 LD1RD	{Z27.D}, P7/Z, [X16, #18]

  (294) 0x42c224 LDR	X16, [X16, #536]

  (294) 0x42c228 MOVZ	X3, #0

  (294) 0x42c22c ORR	W15, WZR, W2

  (294) 0x42c230 DUP	Z1.D, #0

  (294) 0x42c234 UQDECD	W15, ALL

  (294) 0x42c238 LD1RD	{Z3.D}, P7/Z, [X18]

  (294) 0x42c23c WHILELO	P5.D, WZR, W15

  (294) 0x42c240 ORR	Z28.D, Z1.D, Z1.D

  (294) 0x42c244 WHILELO	P6.D, WZR, W2

    (296) 0x42c248 LD1D	{Z29.D}, P5/Z, [X6, X3,LSL #3]

    (296) 0x42c24c LD1D	{Z30.D}, P6/Z, [X4, X3,LSL #3]

    (296) 0x42c250 FMUL	Z31.D, Z3.D, Z29.D

    (296) 0x42c254 FMUL	Z13.D, Z3.D, Z30.D

    (296) 0x42c258 MOVPRFX	Z8, Z31

    (296) 0x42c25c FCVTZS	Z8.S, P7/M, Z31.D

    (296) 0x42c260 MOVPRFX	Z9, Z13

    (296) 0x42c264 FCVTZS	Z9.S, P7/M, Z13.D

    (296) 0x42c268 MOVPRFX	Z0, Z31

    (296) 0x42c26c FRINTZ	Z0.D, P7/M, Z31.D

    (296) 0x42c270 UZP1	Z30.S, Z9.S, Z8.S

    (296) 0x42c274 FSUB	Z31.D, Z31.D, Z0.D

    (296) 0x42c278 MOVPRFX	Z12, Z30

    (296) 0x42c27c ADD	Z12.S, Z12.S, #1

    (296) 0x42c280 FMUL	Z29.D, Z31.D, Z31.D

    (296) 0x42c284 SUNPKHI	Z8.D, Z12

    (296) 0x42c288 FMUL	Z14.D, Z29.D, Z31.D

    (296) 0x42c28c LD1D	{Z9.D}, P5/Z, [X16, Z8.D,LSL #3]

    (296) 0x42c290 FMUL	Z10.D, Z17.D, Z29.D

    (296) 0x42c294 FMLA	Z10.D, P7/M, Z16.D, Z14.D

    (296) 0x42c298 MOVPRFX	Z11, Z19

    (296) 0x42c29c FMLA	Z11.D, P7/M, Z18.D, Z31.D

    (296) 0x42c2a0 FADD	Z0.D, Z10.D, Z11.D

    (296) 0x42c2a4 FMUL	Z10.D, Z5.D, Z29.D

    (296) 0x42c2a8 FMUL	Z0.D, Z0.D, Z9.D

    (296) 0x42c2ac FMLA	Z10.D, P7/M, Z4.D, Z14.D

    (296) 0x42c2b0 SUNPKHI	Z9.D, Z30

    (296) 0x42c2b4 LD1D	{Z8.D}, P5/Z, [X16, Z9.D,LSL #3]

    (296) 0x42c2b8 MOVPRFX	Z11, Z7

    (296) 0x42c2bc FMLA	Z11.D, P7/M, Z6.D, Z31.D

    (296) 0x42c2c0 FADD	Z11.D, Z11.D, Z10.D

    (296) 0x42c2c4 FMUL	Z10.D, Z21.D, Z29.D

    (296) 0x42c2c8 FMAD	Z11.D, P7/M, Z8.D, Z0.D

    (296) 0x42c2cc FMLA	Z10.D, P7/M, Z14.D, Z20.D

    (296) 0x42c2d0 MOVPRFX	Z0, Z23

    (296) 0x42c2d4 FMLA	Z0.D, P7/M, Z31.D, Z22.D

    (296) 0x42c2d8 FMUL	Z29.D, Z29.D, Z25.D

    (296) 0x42c2dc FADD	Z8.D, Z10.D, Z0.D

    (296) 0x42c2e0 FMAD	Z14.D, P7/M, Z24.D, Z29.D

    (296) 0x42c2e4 MOVPRFX	Z10, Z30

    (296) 0x42c2e8 ADD	Z10.S, Z10.S, #2

    (296) 0x42c2ec FADD	Z1.D, P5/M, Z1.D, Z11.D

    (296) 0x42c2f0 FMAD	Z31.D, P7/M, Z26.D, Z27.D

    (296) 0x42c2f4 MOVPRFX	Z11, Z30

    (296) 0x42c2f8 ADD	Z11.S, Z11.S, #3

    (296) 0x42c2fc FADD	Z31.D, Z31.D, Z14.D

    (296) 0x42c300 SUNPKHI	Z0.D, Z11

    (296) 0x42c304 SUNPKHI	Z14.D, Z10

    (296) 0x42c308 LD1D	{Z29.D}, P5/Z, [X16, Z0.D,LSL #3]

    (296) 0x42c30c LD1D	{Z9.D}, P5/Z, [X16, Z14.D,LSL #3]

    (296) 0x42c310 SUNPKLO	Z30.D, Z30

    (296) 0x42c314 FMLA	Z1.D, P5/M, Z9.D, Z8.D

    (296) 0x42c318 SUNPKLO	Z8.D, Z10

    (296) 0x42c31c FMLA	Z1.D, P5/M, Z29.D, Z31.D

    (296) 0x42c320 LD1D	{Z14.D}, P6/Z, [X16, Z8.D,LSL #3]

    (296) 0x42c324 SUNPKLO	Z31.D, Z11

    (296) 0x42c328 MOVPRFX	Z9, Z13

    (296) 0x42c32c FRINTZ	Z9.D, P7/M, Z13.D

    (296) 0x42c330 LD1D	{Z11.D}, P6/Z, [X16, Z30.D,LSL #3]

    (296) 0x42c334 FSUB	Z8.D, Z13.D, Z9.D

    (296) 0x42c338 SUNPKLO	Z12.D, Z12

    (296) 0x42c33c FMUL	Z29.D, Z8.D, Z8.D

    (296) 0x42c340 FMUL	Z30.D, Z29.D, Z8.D

    (296) 0x42c344 FMUL	Z13.D, Z17.D, Z29.D

    (296) 0x42c348 FMLA	Z13.D, P7/M, Z16.D, Z30.D

    (296) 0x42c34c LD1D	{Z10.D}, P6/Z, [X16, Z12.D,LSL #3]

    (296) 0x42c350 ADD	X3, X3, X7

    (296) 0x42c354 MOVPRFX	Z12, Z19

    (296) 0x42c358 FMLA	Z12.D, P7/M, Z18.D, Z8.D

    (296) 0x42c35c WHILELO	P5.D, W3, W15

    (296) 0x42c360 FADD	Z9.D, Z12.D, Z13.D

    (296) 0x42c364 MOVPRFX	Z13, Z7

    (296) 0x42c368 FMLA	Z13.D, P7/M, Z6.D, Z8.D

    (296) 0x42c36c LD1D	{Z0.D}, P6/Z, [X16, Z31.D,LSL #3]

    (296) 0x42c370 FMUL	Z12.D, Z9.D, Z10.D

    (296) 0x42c374 FMUL	Z31.D, Z5.D, Z29.D

    (296) 0x42c378 FMUL	Z10.D, Z21.D, Z29.D

    (296) 0x42c37c FMLA	Z31.D, P7/M, Z4.D, Z30.D

    (296) 0x42c380 MOVPRFX	Z9, Z23

    (296) 0x42c384 FMLA	Z9.D, P7/M, Z8.D, Z22.D

    (296) 0x42c388 FADD	Z31.D, Z13.D, Z31.D

    (296) 0x42c38c FMUL	Z29.D, Z29.D, Z25.D

    (296) 0x42c390 FMAD	Z31.D, P7/M, Z11.D, Z12.D

    (296) 0x42c394 FMAD	Z8.D, P7/M, Z26.D, Z27.D

    (296) 0x42c398 MOVPRFX	Z11, Z10

    (296) 0x42c39c FMLA	Z11.D, P7/M, Z30.D, Z20.D

    (296) 0x42c3a0 FADD	Z28.D, P6/M, Z28.D, Z31.D

    (296) 0x42c3a4 FMAD	Z30.D, P7/M, Z24.D, Z29.D

    (296) 0x42c3a8 FADD	Z13.D, Z9.D, Z11.D

    (296) 0x42c3ac FMLA	Z28.D, P6/M, Z14.D, Z13.D

    (296) 0x42c3b0 FADD	Z14.D, Z30.D, Z8.D

    (296) 0x42c3b4 FMLA	Z28.D, P6/M, Z0.D, Z14.D

    (296) 0x42c3b8 WHILELO	P6.D, W3, W2

    (296) 0x42c3bc B.NE	42c248

  (294) 0x42c3c0 FADD	Z3.D, Z28.D, Z1.D

  (294) 0x42c3c4 FADDV	D1, P7, Z3.D

  (294) 0x42c3c8 FADD	D2, D2, D1

  (294) 0x42c3cc CMP	X13, X8

  (294) 0x42c3d0 B.NE	42bf60

(293) 0x42c3d4 FSUB	D15, D15, S2

(293) 0x42c3d8 FMOV	D0, D15

(293) 0x42c3dc ADD	X20, X20, #1

(293) 0x42c3e0 BL	410490

(293) 0x42c3e4 LDP	X28, X1, [X21]

(293) 0x42c3e8 SUB	X27, X1, X28

(293) 0x42c3ec STR	D0, [X28, X25]

(293) 0x42c3f0 ADD	X25, X25, #8

(293) 0x42c3f4 CMP	X20, X27,ASR #3

(293) 0x42c3f8 B.CC	42bee0

0x42c3fc LDP	D8, D9, [SP, #96]

0x42c400 LDP	X19, X20, [SP, #16]

0x42c404 LDP	X23, X24, [SP, #48]

0x42c408 LDP	X27, X28, [SP, #80]

0x42c40c LDP	D10, D11, [SP, #112]

0x42c410 LDP	D12, D13, [SP, #128]

0x42c414 LDP	D14, D15, [SP, #144]

0x42c418 LDP	X21, X22, [SP, #32]

0x42c41c LDP	X25, X26, [SP, #64]

0x42c420 LDP	X29, X30, [SP], #160

0x42c424 RET

0x42c428 BL	410880

0x42c42c HINT	#0

0x42c430 HINT	#0

0x42c434 HINT	#0

0x42c438 HINT	#0

0x42c43c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.38+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:993	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	TwoBodyJastrowRef.h:105-132
Module	exec

The function is defined in:

/usr/include/c++/14/bits/refwrap.h:351
/usr/include/c++/14/bits/stl_vector.h:993,1147
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,249
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:105-109,125-132
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:231-260
/usr/include/c++/14/optional:991-993

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.33 to 3.33 cycles (2.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 42% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 7.33 to 3.25 cycles (2.26x speedup).

Details

33% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
40% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

std::__throw_bad_optional_access(): 1 occurrences►
- /usr/include/c++/14/optional:993

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	41
nb uops	34
loop length	164
used w registers	0
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	8
used q registers	0
used v registers	0
used z registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.75	2.75	2.75	2.75	2.00	2.00	0.00	0.00	7.33	7.33	7.33	3.00	3.00
cycles	1.50	1.50	2.75	2.75	2.75	2.75	2.00	2.00	0.00	0.00	7.33	7.33	7.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.25
Dispatch	7.33
Overall L1	7.33

Vectorization ratios

all	33%
load	50%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	42%
load	46%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.33 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42be80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X21, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 42c418 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x598>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X22, X1, #656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X23, X26, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
HINT #0																			N/A
HINT #0																			N/A
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #160	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 410880 <_ZSt27__throw_bad_optional_accessv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	TwoBodyJastrowRef.h:105-132
Module	exec

The function is defined in:

/usr/include/c++/14/bits/refwrap.h:351
/usr/include/c++/14/bits/stl_vector.h:993,1147
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,249
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:105-109,125-132
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:231-260
/usr/include/c++/14/optional:991-993

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.33 to 3.33 cycles (2.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

33% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
40% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

std::__throw_bad_optional_access(): 1 occurrences►
- /usr/include/c++/14/optional:993

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	41
nb uops	34
loop length	164
used w registers	0
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	8
used q registers	0
used v registers	0
used z registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.75	2.75	2.75	2.75	2.00	2.00	0.00	0.00	7.33	7.33	7.33	3.00	3.00
cycles	1.50	1.50	2.75	2.75	2.75	2.75	2.00	2.00	0.00	0.00	7.33	7.33	7.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.25
Dispatch	7.33
Overall L1	7.33

Vectorization ratios

all	33%
load	50%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	42%
load	46%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.33 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42be80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X21, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 42c418 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x598>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X22, X1, #656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X23, X26, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
HINT #0																			N/A
HINT #0																			N/A
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #160	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 410880 <_ZSt27__throw_bad_optional_accessv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)–	1.42	2.17
▼Loop 293 - TwoBodyJastrowRef.h:107-132 - exec–	0.02	0.03
▼Loop 294 - TwoBodyJastrowRef.h:127-132 - exec–	0.01	0.03
○Loop 295 - BsplineFunctor.h:236-241 - exec	1.35	2.05
○Loop 296 - BsplineFunctor.h:246-260 - exec	0.03	0.05

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ASM code