OV - exec - Function miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::computeU3(qmcplusplus::ParticleSet const&, int, double const*, double*, double*, double*, bool)

	Function: miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::computeU3(qmcpl ...	Module: exec	Source: TwoBodyJastrowRef.h:254-279 [...]	Coverage (incl. loops): 0.14% \| (excl. loops): 0.01%

/usr/include/c++/14/bits/stl_algobase.h: 238 - 1151

--------------------------------------------------------------------------------

238:       if (__b < __a)

[...]

952: 	*__first = __tmp;

[...]

1146:       if (__n <= 0)

1147: 	return __first;

1148:

1149:       __glibcxx_requires_can_increment(__first, __n);

1150:

1151:       std::__fill_a(__first, __first + __n, __value);

/usr/include/c++/14/bits/stl_vector.h: 1147 - 1147

--------------------------------------------------------------------------------

1147:       operator[](size_type __n) const _GLIBCXX_NOEXCEPT

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 223

--------------------------------------------------------------------------------

223:     return X[i];

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 254 - 279

--------------------------------------------------------------------------------

254: inline void TwoBodyJastrowRef<FT>::computeU3(const ParticleSet& P,

[...]

262:   const int jelmax = triangle ? iat : N;

[...]

268:   const int igt = P.GroupID[iat] * NumGroups;

269:   for (int jg = 0; jg < NumGroups; ++jg)

270:   {

271:     const FuncType& f2(*F[igt + jg]);

[...]

279: }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 313 - 316

--------------------------------------------------------------------------------

313:   inline int first(int igroup) const { return (*group_offsets_)[igroup]; }

314:

315:   ///return the last index of a group i

316:   inline int last(int igroup) const { return (*group_offsets_)[igroup + 1]; }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 276 - 336

--------------------------------------------------------------------------------

276:   real_type dSquareDeltaRinv = DeltaRInv * DeltaRInv;

277:   constexpr real_type cOne(1);

278:

279:   //    START_MARK_FIRST();

280:

281:   ASSUME_ALIGNED(distIndices);

282:   ASSUME_ALIGNED(distArrayCompressed);

283:   int iCount                 = 0;

284:   int iLimit                 = iEnd - iStart;

[...]

291:   for (int jat = 0; jat < iLimit; jat++)

292:   {

293:     real_type r = distArray[jat];

294:     if (r < cutoff_radius && iStart + jat != iat)

295:     {

296:       distIndices[iCount]         = jat;

297:       distArrayCompressed[iCount] = r;

298:       iCount++;

[...]

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

0x441c20 ADDVL	SP, SP, #39

0x441c24 SUB	SP, SP, #160

0x441c28 STP	X29, X30, [SP]

0x441c2c ADD	X29, SP, #0

0x441c30 STP	X19, X20, [SP, #16]

0x441c34 ORR	W19, WZR, W2

0x441c38 ORR	W20, WZR, W2

0x441c3c STP	X21, X22, [SP, #32]

0x441c40 ORR	X21, XZR, X3

0x441c44 ORR	X22, XZR, X4

0x441c48 STP	X23, X24, [SP, #48]

0x441c4c ORR	X23, XZR, X5

0x441c50 ORR	X24, XZR, X6

0x441c54 STP	X25, X26, [SP, #64]

0x441c58 ORR	X25, XZR, X0

0x441c5c ORR	X26, XZR, X1

0x441c60 TBNZ	W7, #0, 441c68

0x441c64 LDR	W20, [X0, #144]

0x441c68 CMP	W20, #0

0x441c6c B.LE	441cac

0x441c70 STR	X27, [SP, #80]

0x441c74 UBFM	X27, X20, #61, #31

0x441c78 MOVZ	W1, #0

0x441c7c ORR	X2, XZR, X27

0x441c80 ORR	X0, XZR, X22

0x441c84 BL	4104e0

0x441c88 ORR	X2, XZR, X27

0x441c8c MOVZ	W1, #0

0x441c90 ORR	X0, XZR, X23

0x441c94 BL	4104e0

0x441c98 ORR	X2, XZR, X27

0x441c9c ORR	X0, XZR, X24

0x441ca0 MOVZ	W1, #0

0x441ca4 BL	4104e0

0x441ca8 LDR	X27, [SP, #80]

0x441cac LDR	X0, [X26, #24]

0x441cb0 LDR	X15, [X25, #160]

0x441cb4 LDR	W1, [X0, W19,SXTW #2]

0x441cb8 MUL	W2, W1, W15

0x441cbc CBZ	X15, 4425ac

0x441cc0 STP	D8, D9, [SP, #96]

0x441cc4 MOVZ	X5, #0

0x441cc8 CNTW	X4, ALL

0x441ccc STP	D10, D11, [SP, #112]

0x441cd0 PTRUE	P7.B, ALL

0x441cd4 STP	D12, D13, [SP, #128]

0x441cd8 STP	D14, D15, [SP, #144]

0x441cdc LDR	X6, [X26, #616]

0x441ce0 LDR	X12, [X25, #464]

0x441ce4 LDR	X13, [X25, #488]

0x441ce8 LDR	X6, [X6, #24]

0x441cec ADDVL	X3, X12, #1

0x441cf0 LDR	X7, [X25, #512]

0x441cf4 ADD	X14, X7, W2,SXTW #3

0x441cf8 HINT	#0

0x441cfc HINT	#0

(524) 0x441d00 LDR	X17, [X14, X5,LSL #3]

(524) 0x441d04 LDR	W18, [X6, X5,LSL #2]

(524) 0x441d08 ADD	X5, X5, #1

(524) 0x441d0c LDR	W8, [X6, X5,LSL #2]

(524) 0x441d10 LDR	D19, [X17, #568]

(524) 0x441d14 CMP	W8, W20

(524) 0x441d18 CSEL	W9, W8, W20, #13

(524) 0x441d1c SUB	W16, W9, W18

(524) 0x441d20 FMUL	D12, D19, D19

(524) 0x441d24 CMP	W16, #0

(524) 0x441d28 B.LE	442594

(524) 0x441d2c SBFM	X30, X18, #61, #31

(524) 0x441d30 ANDS	X11, X16, #0x7

(524) 0x441d34 LDR	D31, [X17, #8]

(524) 0x441d38 ADD	X10, X21, X30

(524) 0x441d3c SBFM	X25, X16, #0, #31

(524) 0x441d40 MOVZ	X0, #0

(524) 0x441d44 MOVZ	W8, #0

(524) 0x441d48 B.EQ	441e84

(524) 0x441d4c CMP	X11, #1

(524) 0x441d50 B.EQ	441e54

(524) 0x441d54 CMP	X11, #2

(524) 0x441d58 B.EQ	441e2c

(524) 0x441d5c CMP	X11, #3

(524) 0x441d60 B.EQ	441e04

(524) 0x441d64 CMP	X11, #4

(524) 0x441d68 B.EQ	441ddc

(524) 0x441d6c CMP	X11, #5

(524) 0x441d70 B.EQ	441db4

(524) 0x441d74 CMP	X11, #6

(524) 0x441d78 B.EQ	441d8c

(524) 0x441d7c LDR	D30, [X21, X30]

(524) 0x441d80 FCMPE	D31, D30

(524) 0x441d84 B.GT	4425cc

(524) 0x441d88 MOVZ	X0, #1

(524) 0x441d8c LDR	D0, [X10, X0,LSL #3]

(524) 0x441d90 FCMPE	D31, D0

(524) 0x441d94 B.LS	441db0

(524) 0x441d98 ADD	W1, W18, W0

(524) 0x441d9c CMP	W19, W1

(524) 0x441da0 B.EQ	441db0

(524) 0x441da4 STR	W0, [X13, W8,UXTW #2]

(524) 0x441da8 STR	D0, [X12, W8,UXTW #3]

(524) 0x441dac ADD	W8, W8, #1

(524) 0x441db0 ADD	X0, X0, #1

(524) 0x441db4 LDR	D1, [X10, X0,LSL #3]

(524) 0x441db8 FCMPE	D31, D1

(524) 0x441dbc B.LS	441dd8

(524) 0x441dc0 ADD	W2, W18, W0

(524) 0x441dc4 CMP	W19, W2

(524) 0x441dc8 B.EQ	441dd8

(524) 0x441dcc STR	W0, [X13, W8,UXTW #2]

(524) 0x441dd0 STR	D1, [X12, W8,UXTW #3]

(524) 0x441dd4 ADD	W8, W8, #1

(524) 0x441dd8 ADD	X0, X0, #1

(524) 0x441ddc LDR	D2, [X10, X0,LSL #3]

(524) 0x441de0 FCMPE	D31, D2

(524) 0x441de4 B.LS	441e00

(524) 0x441de8 ADD	W7, W18, W0

(524) 0x441dec CMP	W19, W7

(524) 0x441df0 B.EQ	441e00

(524) 0x441df4 STR	W0, [X13, W8,UXTW #2]

(524) 0x441df8 STR	D2, [X12, W8,UXTW #3]

(524) 0x441dfc ADD	W8, W8, #1

(524) 0x441e00 ADD	X0, X0, #1

(524) 0x441e04 LDR	D3, [X10, X0,LSL #3]

(524) 0x441e08 FCMPE	D31, D3

(524) 0x441e0c B.LS	441e28

(524) 0x441e10 ADD	W9, W18, W0

(524) 0x441e14 CMP	W19, W9

(524) 0x441e18 B.EQ	441e28

(524) 0x441e1c STR	W0, [X13, W8,UXTW #2]

(524) 0x441e20 STR	D3, [X12, W8,UXTW #3]

(524) 0x441e24 ADD	W8, W8, #1

(524) 0x441e28 ADD	X0, X0, #1

(524) 0x441e2c LDR	D4, [X10, X0,LSL #3]

(524) 0x441e30 FCMPE	D31, D4

(524) 0x441e34 B.LS	441e50

(524) 0x441e38 ADD	W16, W18, W0

(524) 0x441e3c CMP	W19, W16

(524) 0x441e40 B.EQ	441e50

(524) 0x441e44 STR	W0, [X13, W8,UXTW #2]

(524) 0x441e48 STR	D4, [X12, W8,UXTW #3]

(524) 0x441e4c ADD	W8, W8, #1

(524) 0x441e50 ADD	X0, X0, #1

(524) 0x441e54 LDR	D5, [X10, X0,LSL #3]

(524) 0x441e58 FCMPE	D31, D5

(524) 0x441e5c B.LS	441e78

(524) 0x441e60 ADD	W11, W18, W0

(524) 0x441e64 CMP	W19, W11

(524) 0x441e68 B.EQ	441e78

(524) 0x441e6c STR	W0, [X13, W8,UXTW #2]

(524) 0x441e70 STR	D5, [X12, W8,UXTW #3]

(524) 0x441e74 ADD	W8, W8, #1

(524) 0x441e78 ADD	X0, X0, #1

(524) 0x441e7c CMP	X25, X0

(524) 0x441e80 B.EQ	441fcc

  (525) 0x441e84 LDR	D6, [X10, X0,LSL #3]

  (525) 0x441e88 FCMPE	D31, D6

  (525) 0x441e8c B.LS	441ea8

  (525) 0x441e90 ADD	W26, W18, W0

  (525) 0x441e94 CMP	W19, W26

  (525) 0x441e98 B.EQ	441ea8

  (525) 0x441e9c STR	W0, [X13, W8,UXTW #2]

  (525) 0x441ea0 STR	D6, [X12, W8,UXTW #3]

  (525) 0x441ea4 ADD	W8, W8, #1

  (525) 0x441ea8 ADD	X0, X0, #1

  (525) 0x441eac LDR	D7, [X10, X0,LSL #3]

  (525) 0x441eb0 FCMPE	D31, D7

  (525) 0x441eb4 B.LS	441ed0

  (525) 0x441eb8 ADD	W1, W18, W0

  (525) 0x441ebc CMP	W19, W1

  (525) 0x441ec0 B.EQ	441ed0

  (525) 0x441ec4 STR	W0, [X13, W8,UXTW #2]

  (525) 0x441ec8 STR	D7, [X12, W8,UXTW #3]

  (525) 0x441ecc ADD	W8, W8, #1

  (525) 0x441ed0 ADD	X2, X0, #1

  (525) 0x441ed4 LDR	D8, [X10, X2,LSL #3]

  (525) 0x441ed8 FCMPE	D31, D8

  (525) 0x441edc B.LS	441ef8

  (525) 0x441ee0 ADD	W7, W18, W2

  (525) 0x441ee4 CMP	W19, W7

  (525) 0x441ee8 B.EQ	441ef8

  (525) 0x441eec STR	W2, [X13, W8,UXTW #2]

  (525) 0x441ef0 STR	D8, [X12, W8,UXTW #3]

  (525) 0x441ef4 ADD	W8, W8, #1

  (525) 0x441ef8 ADD	X9, X0, #2

  (525) 0x441efc LDR	D9, [X10, X9,LSL #3]

  (525) 0x441f00 FCMPE	D31, D9

  (525) 0x441f04 B.LS	441f20

  (525) 0x441f08 ADD	W16, W18, W9

  (525) 0x441f0c CMP	W19, W16

  (525) 0x441f10 B.EQ	441f20

  (525) 0x441f14 STR	W9, [X13, W8,UXTW #2]

  (525) 0x441f18 STR	D9, [X12, W8,UXTW #3]

  (525) 0x441f1c ADD	W8, W8, #1

  (525) 0x441f20 ADD	X11, X0, #3

  (525) 0x441f24 LDR	D10, [X10, X11,LSL #3]

  (525) 0x441f28 FCMPE	D31, D10

  (525) 0x441f2c B.LS	441f48

  (525) 0x441f30 ADD	W26, W18, W11

  (525) 0x441f34 CMP	W19, W26

  (525) 0x441f38 B.EQ	441f48

  (525) 0x441f3c STR	W11, [X13, W8,UXTW #2]

  (525) 0x441f40 STR	D10, [X12, W8,UXTW #3]

  (525) 0x441f44 ADD	W8, W8, #1

  (525) 0x441f48 ADD	X1, X0, #4

  (525) 0x441f4c LDR	D11, [X10, X1,LSL #3]

  (525) 0x441f50 FCMPE	D31, D11

  (525) 0x441f54 B.LS	441f70

  (525) 0x441f58 ADD	W2, W18, W1

  (525) 0x441f5c CMP	W19, W2

  (525) 0x441f60 B.EQ	441f70

  (525) 0x441f64 STR	W1, [X13, W8,UXTW #2]

  (525) 0x441f68 STR	D11, [X12, W8,UXTW #3]

  (525) 0x441f6c ADD	W8, W8, #1

  (525) 0x441f70 ADD	X7, X0, #5

  (525) 0x441f74 LDR	D13, [X10, X7,LSL #3]

  (525) 0x441f78 FCMPE	D31, D13

  (525) 0x441f7c B.LS	441f98

  (525) 0x441f80 ADD	W9, W18, W7

  (525) 0x441f84 CMP	W19, W9

  (525) 0x441f88 B.EQ	441f98

  (525) 0x441f8c STR	W7, [X13, W8,UXTW #2]

  (525) 0x441f90 STR	D13, [X12, W8,UXTW #3]

  (525) 0x441f94 ADD	W8, W8, #1

  (525) 0x441f98 ADD	X11, X0, #6

  (525) 0x441f9c LDR	D14, [X10, X11,LSL #3]

  (525) 0x441fa0 FCMPE	D31, D14

  (525) 0x441fa4 B.LS	441fc0

  (525) 0x441fa8 ADD	W16, W18, W11

  (525) 0x441fac CMP	W19, W16

  (525) 0x441fb0 B.EQ	441fc0

  (525) 0x441fb4 STR	W11, [X13, W8,UXTW #2]

  (525) 0x441fb8 STR	D14, [X12, W8,UXTW #3]

  (525) 0x441fbc ADD	W8, W8, #1

  (525) 0x441fc0 ADD	X0, X0, #7

  (525) 0x441fc4 CMP	X25, X0

  (525) 0x441fc8 B.NE	441e84

(524) 0x441fcc CBZ	W8, 442594

(524) 0x441fd0 ADDVL	X25, SP, #21

(524) 0x441fd4 ADDVL	X26, SP, #11

(524) 0x441fd8 LDR	X16, [X17, #536]

(524) 0x441fdc ADD	X11, SP, #160

(524) 0x441fe0 ADD	X25, X25, #160

(524) 0x441fe4 LD1RD	{Z16.D}, P7/Z, [X17, #50]

(524) 0x441fe8 ADD	X26, X26, #160

(524) 0x441fec ADDVL	X2, SP, #10

(524) 0x441ff0 LD1RD	{Z17.D}, P7/Z, [X17, #20]

(524) 0x441ff4 ADDVL	X7, SP, #9

(524) 0x441ff8 ADDVL	X9, SP, #8

(524) 0x441ffc LD1RD	{Z18.D}, P7/Z, [X17, #21]

(524) 0x442000 LD1RD	{Z20.D}, P7/Z, [X17, #22]

(524) 0x442004 LD1RD	{Z21.D}, P7/Z, [X17, #24]

(524) 0x442008 LD1RD	{Z22.D}, P7/Z, [X17, #25]

(524) 0x44200c LD1RD	{Z23.D}, P7/Z, [X17, #26]

(524) 0x442010 LD1RD	{Z24.D}, P7/Z, [X17, #28]

(524) 0x442014 LD1RD	{Z25.D}, P7/Z, [X17, #29]

(524) 0x442018 LD1RD	{Z26.D}, P7/Z, [X17, #30]

(524) 0x44201c LD1RD	{Z27.D}, P7/Z, [X17, #32]

(524) 0x442020 LD1RD	{Z28.D}, P7/Z, [X17, #33]

(524) 0x442024 ADD	X2, X2, #160

(524) 0x442028 ADD	X7, X7, #160

(524) 0x44202c LD1RD	{Z0.D}, P7/Z, [X17, #37]

(524) 0x442030 ADD	X9, X9, #160

(524) 0x442034 LD1RD	{Z1.D}, P7/Z, [X17, #38]

(524) 0x442038 LD1RD	{Z2.D}, P7/Z, [X17, #41]

(524) 0x44203c LD1RD	{Z3.D}, P7/Z, [X17, #42]

(524) 0x442040 LD1RD	{Z4.D}, P7/Z, [X17, #45]

(524) 0x442044 LD1RD	{Z5.D}, P7/Z, [X17, #46]

(524) 0x442048 LD1RD	{Z6.D}, P7/Z, [X17, #49]

(524) 0x44204c STR	Z22, [X11, #7, MUL VL]

(524) 0x442050 STR	Z23, [X11, #6, MUL VL]

(524) 0x442054 STR	Z24, [X11, #5, MUL VL]

(524) 0x442058 STR	Z25, [X11, #4, MUL VL]

(524) 0x44205c STR	Z26, [X11, #3, MUL VL]

(524) 0x442060 STR	Z27, [X11, #2, MUL VL]

(524) 0x442064 STR	Z28, [X11, #1, MUL VL]

(524) 0x442068 ADDVL	X0, SP, #13

(524) 0x44206c STR	Z16, [X25, MUL VL]

(524) 0x442070 ADDVL	X25, SP, #14

(524) 0x442074 STR	Z17, [X26, MUL VL]

(524) 0x442078 ADDVL	X26, SP, #15

(524) 0x44207c STR	Z18, [X2, MUL VL]

(524) 0x442080 STR	Z20, [X7, MUL VL]

(524) 0x442084 STR	Z21, [X9, MUL VL]

(524) 0x442088 LD1RD	{Z29.D}, P7/Z, [X17, #34]

(524) 0x44208c STR	Z29, [X11, MUL VL]

(524) 0x442090 INCB	X11, ALL, MUL #12

(524) 0x442094 LD1RD	{Z7.D}, P7/Z, [X17, #6]

(524) 0x442098 LD1RD	{Z8.D}, P7/Z, [X17, #7]

(524) 0x44209c LD1RD	{Z9.D}, P7/Z, [X17, #8]

(524) 0x4420a0 LD1RD	{Z10.D}, P7/Z, [X17, #9]

(524) 0x4420a4 LD1RD	{Z11.D}, P7/Z, [X17, #10]

(524) 0x4420a8 ADD	X0, X0, #160

(524) 0x4420ac ADD	X25, X25, #160

(524) 0x4420b0 DUP	Z15.D, Z12.D[0]

(524) 0x4420b4 ADD	X26, X26, #160

(524) 0x4420b8 LD1RD	{Z12.D}, P7/Z, [X17, #3]

(524) 0x4420bc ADD	X18, X24, X30

(524) 0x4420c0 ADD	X10, X23, X30

(524) 0x4420c4 ADDVL	X2, SP, #16

(524) 0x4420c8 STR	Z12, [X11, MUL VL]

(524) 0x4420cc ADDVL	X7, SP, #22

(524) 0x4420d0 ADDVL	X9, SP, #17

(524) 0x4420d4 LD1RD	{Z31.D}, P7/Z, [X17, #4]

(524) 0x4420d8 ADDVL	X11, SP, #18

(524) 0x4420dc MOVZ	X1, #0

(524) 0x4420e0 LD1RD	{Z30.D}, P7/Z, [X17, #5]

(524) 0x4420e4 ADD	X30, X22, X30

(524) 0x4420e8 LD1RD	{Z13.D}, P7/Z, [X17, #11]

(524) 0x4420ec LD1RD	{Z14.D}, P7/Z, [X17, #12]

(524) 0x4420f0 LD1RD	{Z16.D}, P7/Z, [X17, #13]

(524) 0x4420f4 ADD	X2, X2, #160

(524) 0x4420f8 ADD	X7, X7, #160

(524) 0x4420fc ADD	X9, X9, #160

(524) 0x442100 ADD	X11, X11, #160

(524) 0x442104 STR	Z7, [X26, MUL VL]

(524) 0x442108 LD1RD	{Z7.D}, P7/Z, [X17, #14]

(524) 0x44210c ADDVL	X26, SP, #20

(524) 0x442110 STR	Z31, [X0, MUL VL]

(524) 0x442114 ADDVL	X0, SP, #19

(524) 0x442118 STR	Z30, [X25, MUL VL]

(524) 0x44211c ADDVL	X25, SP, #23

(524) 0x442120 STR	Z8, [X2, MUL VL]

(524) 0x442124 LD1RD	{Z8.D}, P7/Z, [X17, #15]

(524) 0x442128 STR	Z9, [X7, MUL VL]

(524) 0x44212c LD1RD	{Z9.D}, P7/Z, [X17, #16]

(524) 0x442130 STR	Z10, [X9, MUL VL]

(524) 0x442134 LD1RD	{Z10.D}, P7/Z, [X17, #17]

(524) 0x442138 STR	Z11, [X11, MUL VL]

(524) 0x44213c LD1RD	{Z11.D}, P7/Z, [X17, #18]

(524) 0x442140 ADDVL	X17, SP, #24

(524) 0x442144 ADD	X0, X0, #160

(524) 0x442148 ADD	X25, X25, #160

(524) 0x44214c DUP	Z19.D, Z19.D[0]

(524) 0x442150 ADD	X26, X26, #160

(524) 0x442154 ADD	X17, X17, #160

(524) 0x442158 WHILELO	P4.S, WZR, W8

(524) 0x44215c STR	Z13, [X0, MUL VL]

(524) 0x442160 STR	Z14, [X25, MUL VL]

(524) 0x442164 STR	Z16, [X26, MUL VL]

(524) 0x442168 STR	Z15, [X17, MUL VL]

  (526) 0x44216c PUNPKLO	P5.H, P4.B

  (526) 0x442170 PUNPKHI	P6.H, P4.B

  (526) 0x442174 LD1D	{Z27.D}, P5/Z, [X12, X1,LSL #3]

  (526) 0x442178 LD1D	{Z25.D}, P6/Z, [X3, X1,LSL #3]

  (526) 0x44217c FMUL	Z15.D, Z19.D, Z27.D

  (526) 0x442180 FMUL	Z31.D, Z19.D, Z25.D

  (526) 0x442184 MOVPRFX	Z17, Z15

  (526) 0x442188 FCVTZS	Z17.S, P7/M, Z15.D

  (526) 0x44218c MOVPRFX	Z18, Z31

  (526) 0x442190 FCVTZS	Z18.S, P7/M, Z31.D

  (526) 0x442194 MOVPRFX	Z20, Z15

  (526) 0x442198 FRINTZ	Z20.D, P7/M, Z15.D

  (526) 0x44219c UZP1	Z21.S, Z17.S, Z18.S

  (526) 0x4421a0 FSUB	Z30.D, Z15.D, Z20.D

  (526) 0x4421a4 MOVPRFX	Z22, Z21

  (526) 0x4421a8 ADD	Z22.S, Z22.S, #1

  (526) 0x4421ac MOVPRFX	Z28, Z3

  (526) 0x4421b0 FMLA	Z28.D, P7/M, Z2.D, Z30.D

  (526) 0x4421b4 MOVPRFX	Z29, Z21

  (526) 0x4421b8 ADD	Z29.S, Z29.S, #3

  (526) 0x4421bc SUNPKHI	Z23.D, Z22

  (526) 0x4421c0 SUNPKLO	Z24.D, Z22

  (526) 0x4421c4 SUNPKLO	Z16.D, Z21

  (526) 0x4421c8 LD1D	{Z13.D}, P5/Z, [X16, Z24.D,LSL #3]

  (526) 0x4421cc SUNPKLO	Z22.D, Z29

  (526) 0x4421d0 FMUL	Z12.D, Z28.D, Z13.D

  (526) 0x4421d4 SUNPKHI	Z29.D, Z29

  (526) 0x4421d8 MOVPRFX	Z28, Z21

  (526) 0x4421dc ADD	Z28.S, Z28.S, #2

  (526) 0x4421e0 ADDVL	X2, SP, #21

  (526) 0x4421e4 LD1D	{Z14.D}, P5/Z, [X16, Z16.D,LSL #3]

  (526) 0x4421e8 LD1D	{Z17.D}, P6/Z, [X16, Z23.D,LSL #3]

  (526) 0x4421ec LD1D	{Z15.D}, P5/Z, [X16, Z22.D,LSL #3]

  (526) 0x4421f0 LD1D	{Z23.D}, P6/Z, [X16, Z29.D,LSL #3]

  (526) 0x4421f4 SUNPKHI	Z16.D, Z21

  (526) 0x4421f8 SUNPKHI	Z29.D, Z28

  (526) 0x4421fc SUNPKLO	Z21.D, Z28

  (526) 0x442200 ADD	X2, X2, #160

  (526) 0x442204 LDR	Z20, [X2, MUL VL]

  (526) 0x442208 LD1D	{Z22.D}, P5/Z, [X16, Z21.D,LSL #3]

  (526) 0x44220c MOVPRFX	Z26, Z1

  (526) 0x442210 FMLA	Z26.D, P7/M, Z0.D, Z30.D

  (526) 0x442214 ORR	Z18.D, Z20.D, Z20.D

  (526) 0x442218 FMAD	Z26.D, P7/M, Z14.D, Z12.D

  (526) 0x44221c FMLA	Z18.D, P7/M, Z6.D, Z30.D

  (526) 0x442220 MOVPRFX	Z12, Z5

  (526) 0x442224 FMLA	Z12.D, P7/M, Z4.D, Z30.D

  (526) 0x442228 FMUL	Z24.D, Z18.D, Z15.D

  (526) 0x44222c ADDVL	X7, SP, #24

  (526) 0x442230 FMAD	Z12.D, P7/M, Z22.D, Z24.D

  (526) 0x442234 FADD	Z28.D, Z12.D, Z26.D

  (526) 0x442238 LD1D	{Z24.D}, P6/Z, [X16, Z29.D,LSL #3]

  (526) 0x44223c ADD	X7, X7, #160

  (526) 0x442240 LDR	Z12, [X7, MUL VL]

  (526) 0x442244 MOVPRFX	Z29, Z31

  (526) 0x442248 FRINTZ	Z29.D, P7/M, Z31.D

  (526) 0x44224c FMUL	Z21.D, Z28.D, Z12.D

  (526) 0x442250 FSUB	Z31.D, Z31.D, Z29.D

  (526) 0x442254 FMLA	Z20.D, P7/M, Z6.D, Z31.D

  (526) 0x442258 FMUL	Z28.D, Z20.D, Z23.D

  (526) 0x44225c LD1D	{Z18.D}, P6/Z, [X16, Z16.D,LSL #3]

  (526) 0x442260 LD1W	{Z26.S}, P4/Z, [X13, X1,LSL #2]

  (526) 0x442264 MOVPRFX	Z29, Z5

  (526) 0x442268 FMLA	Z29.D, P7/M, Z4.D, Z31.D

  (526) 0x44226c SUNPKLO	Z16.D, Z26

  (526) 0x442270 FMAD	Z29.D, P7/M, Z24.D, Z28.D

  (526) 0x442274 ST1D	{Z21.D}, P5, [X18, Z16.D,LSL #3]

  (526) 0x442278 MOVPRFX	Z28, Z1

  (526) 0x44227c FMLA	Z28.D, P7/M, Z0.D, Z31.D

  (526) 0x442280 MOVPRFX	Z21, Z3

  (526) 0x442284 FMLA	Z21.D, P7/M, Z2.D, Z31.D

  (526) 0x442288 FMUL	Z20.D, Z21.D, Z17.D

  (526) 0x44228c FMAD	Z28.D, P7/M, Z18.D, Z20.D

  (526) 0x442290 FADD	Z29.D, Z29.D, Z28.D

  (526) 0x442294 FMUL	Z12.D, Z29.D, Z12.D

  (526) 0x442298 ADD	X9, SP, #160

  (526) 0x44229c SUNPKHI	Z26.D, Z26

  (526) 0x4422a0 FDUP	Z21.D, #112

  (526) 0x4422a4 ST1D	{Z12.D}, P6, [X18, Z26.D,LSL #3]

  (526) 0x4422a8 LDR	Z12, [X9, #4, MUL VL]

  (526) 0x4422ac LDR	Z20, [X9, #1, MUL VL]

  (526) 0x4422b0 FDIVR	Z27.D, P7/M, Z27.D, Z21.D

  (526) 0x4422b4 LDR	Z21, [X9, #3, MUL VL]

  (526) 0x4422b8 FMLA	Z21.D, P7/M, Z12.D, Z30.D

  (526) 0x4422bc LDR	Z12, [X9, #5, MUL VL]

  (526) 0x4422c0 LDR	Z29, [X9, MUL VL]

  (526) 0x4422c4 FMUL	Z28.D, Z30.D, Z30.D

  (526) 0x4422c8 FMLA	Z29.D, P7/M, Z20.D, Z30.D

  (526) 0x4422cc FMLA	Z21.D, P7/M, Z12.D, Z28.D

  (526) 0x4422d0 LDR	Z20, [X9, #2, MUL VL]

  (526) 0x4422d4 LDR	Z12, [X9, #7, MUL VL]

  (526) 0x4422d8 FMLA	Z29.D, P7/M, Z20.D, Z28.D

  (526) 0x4422dc ADDVL	X0, SP, #10

  (526) 0x4422e0 FMUL	Z29.D, Z29.D, Z15.D

  (526) 0x4422e4 LDR	Z20, [X9, #6, MUL VL]

  (526) 0x4422e8 FMAD	Z21.D, P7/M, Z22.D, Z29.D

  (526) 0x4422ec FMLA	Z20.D, P7/M, Z12.D, Z30.D

  (526) 0x4422f0 INCB	X9, ALL, MUL #8

  (526) 0x4422f4 LDR	Z29, [X9, MUL VL]

  (526) 0x4422f8 ADD	X0, X0, #160

  (526) 0x4422fc LDR	Z12, [X0, MUL VL]

  (526) 0x442300 ADDVL	X11, SP, #9

  (526) 0x442304 ADDVL	X25, SP, #11

  (526) 0x442308 FMLA	Z20.D, P7/M, Z29.D, Z28.D

  (526) 0x44230c ADD	X11, X11, #160

  (526) 0x442310 LDR	Z29, [X11, MUL VL]

  (526) 0x442314 FMUL	Z20.D, Z20.D, Z13.D

  (526) 0x442318 FMLA	Z29.D, P7/M, Z12.D, Z30.D

  (526) 0x44231c ADD	X25, X25, #160

  (526) 0x442320 LDR	Z12, [X25, MUL VL]

  (526) 0x442324 FMUL	Z27.D, Z27.D, Z19.D

  (526) 0x442328 FMLA	Z29.D, P7/M, Z12.D, Z28.D

  (526) 0x44232c FMAD	Z29.D, P7/M, Z14.D, Z20.D

  (526) 0x442330 FADD	Z21.D, Z29.D, Z21.D

  (526) 0x442334 FMUL	Z27.D, Z21.D, Z27.D

  (526) 0x442338 ADD	X26, SP, #160

  (526) 0x44233c ST1D	{Z27.D}, P5, [X10, Z16.D,LSL #3]

  (526) 0x442340 FDUP	Z29.D, #112

  (526) 0x442344 LDR	Z27, [X26, #4, MUL VL]

  (526) 0x442348 LDR	Z20, [X26, #1, MUL VL]

  (526) 0x44234c LDR	Z12, [X26, MUL VL]

  (526) 0x442350 LDR	Z21, [X26, #3, MUL VL]

  (526) 0x442354 FMLA	Z12.D, P7/M, Z20.D, Z31.D

  (526) 0x442358 FMLA	Z21.D, P7/M, Z27.D, Z31.D

  (526) 0x44235c LDR	Z20, [X26, #2, MUL VL]

  (526) 0x442360 FDIVR	Z25.D, P7/M, Z25.D, Z29.D

  (526) 0x442364 LDR	Z27, [X26, #5, MUL VL]

  (526) 0x442368 FMUL	Z29.D, Z31.D, Z31.D

  (526) 0x44236c FMLA	Z12.D, P7/M, Z20.D, Z29.D

  (526) 0x442370 FMLA	Z21.D, P7/M, Z27.D, Z29.D

  (526) 0x442374 ADDVL	X2, SP, #10

  (526) 0x442378 FMUL	Z27.D, Z12.D, Z23.D

  (526) 0x44237c LDR	Z12, [X26, #7, MUL VL]

  (526) 0x442380 LDR	Z20, [X26, #6, MUL VL]

  (526) 0x442384 FMAD	Z21.D, P7/M, Z24.D, Z27.D

  (526) 0x442388 FMLA	Z20.D, P7/M, Z12.D, Z31.D

  (526) 0x44238c INCB	X26, ALL, MUL #8

  (526) 0x442390 LDR	Z27, [X26, MUL VL]

  (526) 0x442394 ADD	X2, X2, #160

  (526) 0x442398 LDR	Z12, [X2, MUL VL]

  (526) 0x44239c FMLA	Z20.D, P7/M, Z27.D, Z29.D

  (526) 0x4423a0 ADDVL	X17, SP, #9

  (526) 0x4423a4 FMUL	Z20.D, Z20.D, Z17.D

  (526) 0x4423a8 ADDVL	X7, SP, #11

  (526) 0x4423ac ADDVL	X0, SP, #17

  (526) 0x4423b0 ADD	X17, X17, #160

  (526) 0x4423b4 LDR	Z27, [X17, MUL VL]

  (526) 0x4423b8 ADD	X7, X7, #160

  (526) 0x4423bc FMLA	Z27.D, P7/M, Z12.D, Z31.D

  (526) 0x4423c0 LDR	Z12, [X7, MUL VL]

  (526) 0x4423c4 ADD	X0, X0, #160

  (526) 0x4423c8 FMLA	Z27.D, P7/M, Z12.D, Z29.D

  (526) 0x4423cc ADDVL	X9, SP, #22

  (526) 0x4423d0 FMAD	Z27.D, P7/M, Z18.D, Z20.D

  (526) 0x4423d4 ADDVL	X11, SP, #18

  (526) 0x4423d8 FADD	Z21.D, Z27.D, Z21.D

  (526) 0x4423dc ADDVL	X25, SP, #16

  (526) 0x4423e0 FMUL	Z25.D, Z25.D, Z19.D

  (526) 0x4423e4 FMUL	Z25.D, Z21.D, Z25.D

  (526) 0x4423e8 ST1D	{Z25.D}, P6, [X10, Z26.D,LSL #3]

  (526) 0x4423ec LDR	Z20, [X0, MUL VL]

  (526) 0x4423f0 ADD	X9, X9, #160

  (526) 0x4423f4 ADD	X11, X11, #160

  (526) 0x4423f8 LDR	Z27, [X11, MUL VL]

  (526) 0x4423fc ADD	X25, X25, #160

  (526) 0x442400 FMLA	Z27.D, P7/M, Z30.D, Z20.D

  (526) 0x442404 LDR	Z20, [X25, MUL VL]

  (526) 0x442408 ADDVL	X26, SP, #13

  (526) 0x44240c ADDVL	X17, SP, #12

  (526) 0x442410 ADDVL	X7, SP, #14

  (526) 0x442414 LDR	Z12, [X9, MUL VL]

  (526) 0x442418 FMUL	Z21.D, Z28.D, Z30.D

  (526) 0x44241c FMUL	Z25.D, Z28.D, Z12.D

  (526) 0x442420 ADD	X26, X26, #160

  (526) 0x442424 FMLA	Z25.D, P7/M, Z21.D, Z20.D

  (526) 0x442428 LDR	Z20, [X26, MUL VL]

  (526) 0x44242c ADD	X17, X17, #160

  (526) 0x442430 ADD	X7, X7, #160

  (526) 0x442434 FMUL	Z20.D, Z28.D, Z20.D

  (526) 0x442438 FADD	Z25.D, Z27.D, Z25.D

  (526) 0x44243c LDR	Z27, [X17, MUL VL]

  (526) 0x442440 FMUL	Z25.D, Z25.D, Z13.D

  (526) 0x442444 LDR	Z13, [X7, MUL VL]

  (526) 0x442448 FMLA	Z20.D, P7/M, Z21.D, Z27.D

  (526) 0x44244c ADDVL	X2, SP, #15

  (526) 0x442450 ADDVL	X9, SP, #23

  (526) 0x442454 ADDVL	X11, SP, #19

  (526) 0x442458 ADDVL	X0, SP, #20

  (526) 0x44245c ADDVL	X25, SP, #18

  (526) 0x442460 ADD	X2, X2, #160

  (526) 0x442464 LDR	Z27, [X2, MUL VL]

  (526) 0x442468 ADD	X9, X9, #160

  (526) 0x44246c FMLA	Z27.D, P7/M, Z30.D, Z13.D

  (526) 0x442470 ADD	X11, X11, #160

  (526) 0x442474 ADD	X0, X0, #160

  (526) 0x442478 ADD	X25, X25, #160

  (526) 0x44247c FMUL	Z13.D, Z28.D, Z9.D

  (526) 0x442480 FADD	Z27.D, Z27.D, Z20.D

  (526) 0x442484 LDR	Z20, [X11, MUL VL]

  (526) 0x442488 FMAD	Z27.D, P7/M, Z14.D, Z25.D

  (526) 0x44248c LDR	Z14, [X9, MUL VL]

  (526) 0x442490 MOVPRFX	Z25, Z11

  (526) 0x442494 FMLA	Z25.D, P7/M, Z30.D, Z10.D

  (526) 0x442498 FMUL	Z28.D, Z28.D, Z14.D

  (526) 0x44249c FMLA	Z13.D, P7/M, Z21.D, Z8.D

  (526) 0x4424a0 ADDVL	X26, SP, #17

  (526) 0x4424a4 FMAD	Z21.D, P7/M, Z20.D, Z28.D

  (526) 0x4424a8 ADDVL	X17, SP, #16

  (526) 0x4424ac LDR	Z28, [X0, MUL VL]

  (526) 0x4424b0 FADD	Z13.D, Z25.D, Z13.D

  (526) 0x4424b4 FMAD	Z30.D, P7/M, Z28.D, Z7.D

  (526) 0x4424b8 FMUL	Z15.D, Z13.D, Z15.D

  (526) 0x4424bc FADD	Z30.D, Z30.D, Z21.D

  (526) 0x4424c0 ADD	X26, X26, #160

  (526) 0x4424c4 FMAD	Z22.D, P7/M, Z30.D, Z15.D

  (526) 0x4424c8 FMUL	Z21.D, Z29.D, Z12.D

  (526) 0x4424cc FADD	Z22.D, Z27.D, Z22.D

  (526) 0x4424d0 ADD	X17, X17, #160

  (526) 0x4424d4 ST1D	{Z22.D}, P5, [X30, Z16.D,LSL #3]

  (526) 0x4424d8 LDR	Z12, [X25, MUL VL]

  (526) 0x4424dc LDR	Z27, [X26, MUL VL]

  (526) 0x4424e0 LDR	Z25, [X17, MUL VL]

  (526) 0x4424e4 FMUL	Z16.D, Z29.D, Z31.D

  (526) 0x4424e8 FMLA	Z12.D, P7/M, Z31.D, Z27.D

  (526) 0x4424ec FMLA	Z21.D, P7/M, Z16.D, Z25.D

  (526) 0x4424f0 ADDVL	X2, SP, #13

  (526) 0x4424f4 ADDVL	X7, SP, #12

  (526) 0x4424f8 FADD	Z13.D, Z12.D, Z21.D

  (526) 0x4424fc ADDVL	X9, SP, #15

  (526) 0x442500 ADDVL	X11, SP, #14

  (526) 0x442504 FMUL	Z21.D, Z29.D, Z9.D

  (526) 0x442508 ADDVL	X0, SP, #19

  (526) 0x44250c ADDVL	X25, SP, #20

  (526) 0x442510 FMLA	Z21.D, P7/M, Z16.D, Z8.D

  (526) 0x442514 ADD	X2, X2, #160

  (526) 0x442518 LDR	Z20, [X2, MUL VL]

  (526) 0x44251c ADD	X7, X7, #160

  (526) 0x442520 LDR	Z28, [X7, MUL VL]

  (526) 0x442524 FMUL	Z15.D, Z29.D, Z20.D

  (526) 0x442528 ADD	X9, X9, #160

  (526) 0x44252c LDR	Z30, [X9, MUL VL]

  (526) 0x442530 FMLA	Z15.D, P7/M, Z16.D, Z28.D

  (526) 0x442534 ADD	X11, X11, #160

  (526) 0x442538 LDR	Z22, [X11, MUL VL]

  (526) 0x44253c ADD	X0, X0, #160

  (526) 0x442540 FMLA	Z30.D, P7/M, Z31.D, Z22.D

  (526) 0x442544 ADD	X25, X25, #160

  (526) 0x442548 LDR	Z25, [X25, MUL VL]

  (526) 0x44254c FMUL	Z17.D, Z17.D, Z13.D

  (526) 0x442550 FADD	Z12.D, Z30.D, Z15.D

  (526) 0x442554 FMAD	Z12.D, P7/M, Z18.D, Z17.D

  (526) 0x442558 FMUL	Z18.D, Z29.D, Z14.D

  (526) 0x44255c LDR	Z14, [X0, MUL VL]

  (526) 0x442560 MOVPRFX	Z29, Z11

  (526) 0x442564 FMLA	Z29.D, P7/M, Z31.D, Z10.D

  (526) 0x442568 FMAD	Z16.D, P7/M, Z14.D, Z18.D

  (526) 0x44256c FADD	Z27.D, Z21.D, Z29.D

  (526) 0x442570 FMAD	Z31.D, P7/M, Z25.D, Z7.D

  (526) 0x442574 FMUL	Z23.D, Z23.D, Z27.D

  (526) 0x442578 FADD	Z31.D, Z31.D, Z16.D

  (526) 0x44257c FMAD	Z24.D, P7/M, Z31.D, Z23.D

  (526) 0x442580 FADD	Z24.D, Z12.D, Z24.D

  (526) 0x442584 ST1D	{Z24.D}, P6, [X30, Z26.D,LSL #3]

  (526) 0x442588 ADD	X1, X1, X4

  (526) 0x44258c WHILELO	P4.S, W1, W8

  (526) 0x442590 B.NE	44216c

(524) 0x442594 CMP	X15, X5

(524) 0x442598 B.NE	441d00

0x44259c LDP	D8, D9, [SP, #96]

0x4425a0 LDP	D10, D11, [SP, #112]

0x4425a4 LDP	D12, D13, [SP, #128]

0x4425a8 LDP	D14, D15, [SP, #144]

0x4425ac LDP	X29, X30, [SP]

0x4425b0 LDP	X19, X20, [SP, #16]

0x4425b4 LDP	X21, X22, [SP, #32]

0x4425b8 LDP	X23, X24, [SP, #48]

0x4425bc LDP	X25, X26, [SP, #64]

0x4425c0 ADDVL	SP, SP, #25

0x4425c4 ADD	SP, SP, #160

0x4425c8 RET

(524) 0x4425cc CMP	W19, W18

(524) 0x4425d0 B.EQ	441d88

(524) 0x4425d4 MOVZ	X26, #0

(524) 0x4425d8 MOVZ	W8, #1

(524) 0x4425dc STR	WZR, [X13, X26]

(524) 0x4425e0 STR	D30, [X12, X26]

(524) 0x4425e4 B	441d88

0x4425e8 HINT	#0

0x4425ec HINT	#0

0x4425f0 HINT	#0

0x4425f4 HINT	#0

0x4425f8 HINT	#0

0x4425fc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.39+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:315	exec
○	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_1

Source file and lines	TwoBodyJastrowRef.h:254-279
Module	exec

The function is defined in:

/usr/include/c++/14/bits/stl_algobase.h:238,952,1146-1151
/usr/include/c++/14/bits/stl_vector.h:1147
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:254,262,268-271,279
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:276-284,291-298,305-336

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.67 to 3.00 cycles (3.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 33% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 9.67 to 5.37 cycles (1.80x speedup).

Details

18% of VPU instructions are used in vector version (process two or more data elements in vector registers):

28% of VPU loads are used in vector version.
40% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /usr/include/c++/14/bits/stl_algobase.h:952
- /usr/include/c++/14/bits/stl_algobase.h:952
- /usr/include/c++/14/bits/stl_algobase.h:952

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes.

General properties

nb instructions	74
nb uops	66
loop length	296
used w registers	7
used x registers	24
used b registers	0
used h registers	0
used s registers	1
used d registers	8
used q registers	0
used v registers	0
used z registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.25 cycles
front end	8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	8.25	8.25	8.25	8.25	2.00	2.00	0.00	0.00	9.67	9.67	9.67	3.00	3.00
cycles	3.50	3.50	8.25	8.25	8.25	8.25	2.00	2.00	0.00	0.00	9.67	9.67	9.67	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.25
Dispatch	9.67
Overall L1	9.67

Vectorization ratios

all	18%
load	28%
store	40%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	33%
load	35%
store	47%
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.67 cycles. At this rate:

0% of peak load performance is reached (0.62 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 441c20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADDVL SP, SP, #39	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR W19, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W20, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X21, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X23, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
TBNZ W7, #0, 441c68 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 441cac <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UBFM X27, X20, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X2, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4104e0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4104e0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104e0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X26, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X25, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W1, [X0, W19,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MUL W2, W1, W15	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
CBZ X15, 4425ac <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x98c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
MOVZ X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTW X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR X6, [X26, #616]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X25, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X6, [X6, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADDVL X3, X12, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X7, [X25, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X7, W2,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADDVL SP, SP, #25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_1

Source file and lines	TwoBodyJastrowRef.h:254-279
Module	exec

The function is defined in:

/usr/include/c++/14/bits/stl_algobase.h:238,952,1146-1151
/usr/include/c++/14/bits/stl_vector.h:1147
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:254,262,268-271,279
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:276-284,291-298,305-336

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.67 to 3.00 cycles (3.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

18% of VPU instructions are used in vector version (process two or more data elements in vector registers):

28% of VPU loads are used in vector version.
40% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /usr/include/c++/14/bits/stl_algobase.h:952
- /usr/include/c++/14/bits/stl_algobase.h:952
- /usr/include/c++/14/bits/stl_algobase.h:952

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes.

General properties

nb instructions	74
nb uops	66
loop length	296
used w registers	7
used x registers	24
used b registers	0
used h registers	0
used s registers	1
used d registers	8
used q registers	0
used v registers	0
used z registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.25 cycles
front end	8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	8.25	8.25	8.25	8.25	2.00	2.00	0.00	0.00	9.67	9.67	9.67	3.00	3.00
cycles	3.50	3.50	8.25	8.25	8.25	8.25	2.00	2.00	0.00	0.00	9.67	9.67	9.67	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.25
Dispatch	9.67
Overall L1	9.67

Vectorization ratios

all	18%
load	28%
store	40%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	33%
load	35%
store	47%
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.67 cycles. At this rate:

0% of peak load performance is reached (0.62 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 441c20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADDVL SP, SP, #39	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR W19, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W20, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X21, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X23, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
TBNZ W7, #0, 441c68 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 441cac <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UBFM X27, X20, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X2, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4104e0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4104e0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104e0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X26, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X25, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W1, [X0, W19,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MUL W2, W1, W15	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
CBZ X15, 4425ac <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x98c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
MOVZ X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTW X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR X6, [X26, #616]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X25, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X6, [X6, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADDVL X3, X12, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X7, [X25, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X7, W2,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADDVL SP, SP, #25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)–	0.14	0.21
▼Loop 524 - TwoBodyJastrowRef.h:269-271 - exec–	0.00	0.02
○Loop 525 - BsplineFunctor.h:291-298 - exec	0.11	0.17
○Loop 526 - BsplineFunctor.h:305-336 - exec	0.01	0.03

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code