OV - exec - Function miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector<double, std::allocator<double> >&, qmcplusplus::Vector<qmcplusplus::TinyVector<double, 3u>, std::allocator<qmcplusplus::TinyVector<double, 3u> > >&, qmcplusplus::Vector<double, std::allocator<double> >&)

	Function: miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int ...	Module: exec	Source: einspline_spo_ref.hpp:203-230 [...]	Coverage (incl. loops): 10.43% \| (excl. loops): 0.02%

/usr/include/c++/14/bits/stl_algobase.h: 238 - 952

--------------------------------------------------------------------------------

238:       if (__b < __a)

[...]

951:       for (; __first != __last; ++__first)

952: 	*__first = __tmp;

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp: 53 - 66

--------------------------------------------------------------------------------

53:   if (x < 0)

54:   {

55:     ind = 0;

56:     dx  = T(0);

57:   }

58:   else

59:   {

60:     ind = static_cast<int>(x);

61:     dx = x - ind;

62:     // upper bound

63:     if (ind > nmax)

64:     {

65:       ind = nmax;

66:       dx  = T(1) - std::numeric_limits<T>::epsilon();

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 145 - 145

--------------------------------------------------------------------------------

145:       X[i] = base[i * offset];

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 203 - 230

--------------------------------------------------------------------------------

203:     ScopedTimer local_timer(timer);

204:

205:     auto u = Lattice.toUnit_floor(P.activeR(iat));

206:     for (int i = 0; i < nBlocks; ++i)

207:       MultiBsplineEvalRef::evaluate_vgh(einsplines[i], u[0], u[1], u[2], psi[i].data(), grad[i].data(), hess[i].data(),

208:                                         nSplinesPerBlock);

209:   }

210:

211:   inline void evaluate(const ParticleSet& P,

[...]

219:     for (int i = 0; i < nBlocks; ++i)

220:     {

221:       // in real simulation, phase needs to be applied. Here just fake computation

222:       const int first = i * nBlocks;

223:       for (int j = first; j < std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize); j++)

224:       {

225:         psi_v[j]   = psi[i][j - first];

226:         dpsi_v[j]  = grad[i][j - first];

227:         d2psi_v[j] = hess[i].data(0)[j - first];

228:       }

229:     }

230:   }

/usr/include/c++/14/bits/stl_vector.h: 1131 - 1263

--------------------------------------------------------------------------------

1131: 	return *(this->_M_impl._M_start + __n);

[...]

1263:       { return _M_data_ptr(this->_M_impl._M_start); }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 229

--------------------------------------------------------------------------------

223:     return X[i];

[...]

229:     return X[i];

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 271

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

[...]

265:   inline T* data() { return myData; }

[...]

271:   inline T* restrict data(size_t i) { return myData + i * nGhosts; }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 187 - 286

--------------------------------------------------------------------------------

187:   x -= spline_m->x_grid.start;

188:   y -= spline_m->y_grid.start;

189:   z -= spline_m->z_grid.start;

190:   spline2::getSplineBound(x * spline_m->x_grid.delta_inv, tx, ix, spline_m->x_grid.num - 1);

191:   spline2::getSplineBound(y * spline_m->y_grid.delta_inv, ty, iy, spline_m->y_grid.num - 1);

192:   spline2::getSplineBound(z * spline_m->z_grid.delta_inv, tz, iz, spline_m->z_grid.num - 1);

[...]

199:   const intptr_t ys = spline_m->y_stride;

200:   const intptr_t zs = spline_m->z_stride;

201:

202:   const size_t out_offset = spline_m->num_splines;

203:

204:   T* restrict gx = grads;

205:   T* restrict gy = grads + out_offset;

206:   T* restrict gz = grads + 2 * out_offset;

207:

208:   T* restrict hxx = hess;

209:   T* restrict hxy = hess + out_offset;

210:   T* restrict hxz = hess + 2 * out_offset;

211:   T* restrict hyy = hess + 3 * out_offset;

212:   T* restrict hyz = hess + 4 * out_offset;

213:   T* restrict hzz = hess + 5 * out_offset;

214:

215:   std::fill(vals, vals + num_splines, T());

[...]

226:   for (int i = 0; i < 4; i++)

227:     for (int j = 0; j < 4; j++)

228:     {

229:       const T* restrict coefs    = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs;

230:       const T* restrict coefszs  = coefs + zs;

231:       const T* restrict coefs2zs = coefs + 2 * zs;

232:       const T* restrict coefs3zs = coefs + 3 * zs;

233:

234:       const T pre20 = d2a[i] * b[j];

235:       const T pre10 = da[i] * b[j];

236:       const T pre00 = a[i] * b[j];

237:       const T pre11 = da[i] * db[j];

238:       const T pre01 = a[i] * db[j];

239:       const T pre02 = a[i] * d2b[j];

240:

241:       const int iSplitPoint = num_splines;

242:       for (int n = 0; n < iSplitPoint; n++)

243:       {

244:         T coefsv    = coefs[n];

245:         T coefsvzs  = coefszs[n];

246:         T coefsv2zs = coefs2zs[n];

247:         T coefsv3zs = coefs3zs[n];

248:

249:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

250:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

251:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

252:

253:         hxx[n] += pre20 * sum0;

254:         hxy[n] += pre11 * sum0;

255:         hxz[n] += pre10 * sum1;

256:         hyy[n] += pre02 * sum0;

257:         hyz[n] += pre01 * sum1;

258:         hzz[n] += pre00 * sum2;

259:         gx[n] += pre10 * sum0;

260:         gy[n] += pre01 * sum0;

261:         gz[n] += pre00 * sum1;

262:         vals[n] += pre00 * sum0;

[...]

269:   const T dxx   = dxInv * dxInv;

270:   const T dyy   = dyInv * dyInv;

271:   const T dzz   = dzInv * dzInv;

272:   const T dxy   = dxInv * dyInv;

273:   const T dxz   = dxInv * dzInv;

274:   const T dyz   = dyInv * dzInv;

275:

276:   for (int n = 0; n < num_splines; n++)

277:   {

278:     gx[n] *= dxInv;

279:     gy[n] *= dyInv;

280:     gz[n] *= dzInv;

281:     hxx[n] *= dxx;

282:     hyy[n] *= dyy;

283:     hzz[n] *= dzz;

284:     hxy[n] *= dxy;

285:     hxz[n] *= dxz;

286:     hyz[n] *= dyz;

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h: 168 - 174

--------------------------------------------------------------------------------

168:     val_dot = toUnit(r);

169:     for (int i = 0; i < D; i++)

170:       if (-std::numeric_limits<T1>::epsilon() < val_dot[i] && val_dot[i] < 0)

171:         val_dot[i] = T1(0.0);

172:       else

173:         val_dot[i] -= std::floor(val_dot[i]);

174:     return val_dot;

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 143 - 143

--------------------------------------------------------------------------------

143:     return (active_ptcl_ == iat) ? active_pos_ : R[iat];

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h: 150 - 152

--------------------------------------------------------------------------------

150:     return TinyVector<Type_t, 3>(lhs[0] * rhs[0] + lhs[1] * rhs[3] + lhs[2] * rhs[6],

151:                                  lhs[0] * rhs[1] + lhs[1] * rhs[4] + lhs[2] * rhs[7],

152:                                  lhs[0] * rhs[2] + lhs[1] * rhs[5] + lhs[2] * rhs[8]);

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp: 68 - 79

--------------------------------------------------------------------------------

68:     a[0]   = ((A00 * tx + A01) * tx + A02) * tx + A03;

69:     a[1]   = ((A10 * tx + A11) * tx + A12) * tx + A13;

70:     a[2]   = ((A20 * tx + A21) * tx + A22) * tx + A23;

71:     a[3]   = ((A30 * tx + A31) * tx + A32) * tx + A33;

72:     da[0]  = (dA01 * tx + dA02) * tx + dA03;

73:     da[1]  = (dA11 * tx + dA12) * tx + dA13;

74:     da[2]  = (dA21 * tx + dA22) * tx + dA23;

75:     da[3]  = (dA31 * tx + dA32) * tx + dA33;

76:     d2a[0] = d2A02 * tx + d2A03;

77:     d2a[1] = d2A12 * tx + d2A13;

78:     d2a[2] = d2A22 * tx + d2A23;

79:     d2a[3] = d2A32 * tx + d2A33;

0x45f960 SUB	SP, SP, #656

0x45f964 STP	X29, X30, [SP]

0x45f968 ADD	X29, SP, #0

0x45f96c STP	X19, X20, [SP, #16]

0x45f970 ORR	X20, XZR, X0

0x45f974 ORR	W19, WZR, W2

0x45f978 STP	X21, X22, [SP, #32]

0x45f97c ORR	X22, XZR, X4

0x45f980 ORR	X21, XZR, X5

0x45f984 STP	X23, X24, [SP, #48]

0x45f988 ORR	X23, XZR, X3

0x45f98c STP	X25, X26, [SP, #64]

0x45f990 ORR	X25, XZR, X1

0x45f994 STP	X27, X28, [SP, #80]

0x45f998 LDR	X24, [X0, #856]

0x45f99c ORR	X0, XZR, X24

0x45f9a0 BL	4cf800

0x45f9a4 LDR	W0, [X25, #292]

0x45f9a8 ADD	X4, X25, #296

0x45f9ac CMP	W19, W0

0x45f9b0 B.EQ	45f9c0

0x45f9b4 LDR	X2, [X25, #64]

0x45f9b8 MOVZ	W1, #24

0x45f9bc SMADDL	X4, W19, W1, X2

0x45f9c0 LDP	D28, D27, [X4]

0x45f9c4 PTRUE	P7.B, ALL

0x45f9c8 MOVZ	W5, #3

0x45f9cc ADD	X18, SP, #624

0x45f9d0 WHILELO	P4.D, WZR, W5

0x45f9d4 MOVZ	X3, #48304

0x45f9d8 LDP	D26, D6, [X20, #232]

0x45f9dc DUP	Z30.D, X3

0x45f9e0 CNTD	X6, ALL

0x45f9e4 WHILELO	P5.D, W6, W5

0x45f9e8 LDP	D4, D2, [X20, #248]

0x45f9ec LDP	D5, D3, [X20, #216]

0x45f9f0 FMUL	D0, D27, D6

0x45f9f4 LDR	D24, [X4, #16]

0x45f9f8 FMUL	D1, D27, D4

0x45f9fc FMUL	D7, D27, D2

0x45fa00 LDR	D22, [X20, #280]

0x45fa04 LDP	D23, D25, [X20, #264]

0x45fa08 FMADD	D18, D28, D5, D0

0x45fa0c FMADD	D16, D28, D3, D1

0x45fa10 FMADD	D17, D28, D26, D7

0x45fa14 FMADD	D19, D24, D23, D18

0x45fa18 FMADD	D20, D24, D25, D16

0x45fa1c FMADD	D21, D24, D22, D17

0x45fa20 STR	D19, [SP, #624]

0x45fa24 STR	D20, [SP, #632]

0x45fa28 STR	D21, [SP, #640]

0x45fa2c LD1D	{Z29.D}, P4/Z, [X18, MUL VL]

0x45fa30 FCMLT	P6.D, P7/Z, Z29.D, #0.0000000

0x45fa34 MOVPRFX	Z31, Z29

0x45fa38 FRINTM	Z31.D, P7/M, Z29.D

0x45fa3c FCMGT	P0.D, P6/Z, Z29.D, Z30.D

0x45fa40 EOR	P1.B, P7/Z, P0.B, P7.B

0x45fa44 MOVPRFX	Z31.D, P1/Z, Z31.D

0x45fa48 FSUBR	Z31.D, P1/M, Z31.D, Z29.D

0x45fa4c ST1D	{Z31.D}, P4, [X18, MUL VL]

0x45fa50 B.EQ	45fa78

0x45fa54 LD1D	{Z28.D}, P5/Z, [X18, #1, MUL VL]

0x45fa58 FCMLT	P6.D, P7/Z, Z28.D, #0.0000000

0x45fa5c MOVPRFX	Z27, Z28

0x45fa60 FRINTM	Z27.D, P7/M, Z28.D

0x45fa64 FCMGT	P15.D, P6/Z, Z28.D, Z30.D

0x45fa68 EOR	P2.B, P7/Z, P15.B, P7.B

0x45fa6c MOVPRFX	Z27.D, P2/Z, Z27.D

0x45fa70 FSUBR	Z27.D, P2/M, Z27.D, Z28.D

0x45fa74 ST1D	{Z27.D}, P5, [X18, #1, MUL VL]

0x45fa78 ADD	X8, SP, #512

0x45fa7c ADD	X9, SP, #512

0x45fa80 LDR	W12, [X20, #48]

0x45fa84 LDP	X10, X11, [X8, #112]

0x45fa88 STP	X10, X11, [X9, #952]

0x45fa8c LDR	X11, [X18, #16]

0x45fa90 LDR	D30, [SP, #440]

0x45fa94 LDR	D24, [SP, #448]

0x45fa98 STR	X11, [SP, #456]

0x45fa9c LDR	D5, [SP, #456]

0x45faa0 STR	D30, [SP, #344]

0x45faa4 STR	D24, [SP, #352]

0x45faa8 STR	D5, [SP, #360]

0x45faac CMP	W12, #0

0x45fab0 B.LE	460304

0x45fab4 ORR	X13, XZR, #0x55

0x45fab8 STP	D8, D9, [SP, #96]

0x45fabc ORR	X14, XZR, #0x55

0x45fac0 MOVK	X13, #16325

0x45fac4 STP	D10, D11, [SP, #112]

0x45fac8 MOVK	X14, #16357

0x45facc STP	D12, D13, [SP, #128]

0x45fad0 MOVZ	X6, #24

0x45fad4 FMOV	D1, X13

0x45fad8 STP	D14, D15, [SP, #144]

0x45fadc LDR	W16, [X20, #64]

0x45fae0 STR	X21, [SP, #424]

0x45fae4 LDR	X5, [X20, #760]

0x45fae8 ADD	X15, X5, W12,UXTW #3

0x45faec STP	X24, X20, [SP, #392]

0x45faf0 SBFM	X2, X16, #61, #31

0x45faf4 STP	X23, X22, [SP, #408]

0x45faf8 SBFM	X22, X16, #0, #31

0x45fafc LDR	X17, [X20, #784]

0x45fb00 STR	X14, [SP, #208]

0x45fb04 LDR	X21, [X20, #808]

0x45fb08 STR	X15, [SP, #368]

0x45fb0c LDR	X20, [X20, #832]

0x45fb10 STR	X17, [SP, #200]

0x45fb14 STR	W16, [SP, #380]

0x45fb18 STR	X21, [SP, #328]

0x45fb1c STR	X22, [SP, #384]

0x45fb20 STR	X20, [SP, #336]

(945) 0x45fb24 LDR	X9, [X5]

(945) 0x45fb28 LDR	D11, [SP, #344]

(945) 0x45fb2c LDR	D14, [SP, #352]

(945) 0x45fb30 LDR	D8, [X9, #40]

(945) 0x45fb34 LDP	D22, D9, [X9, #72]

(945) 0x45fb38 LDR	D10, [X9, #120]

(945) 0x45fb3c FSUB	D12, D11, S8

(945) 0x45fb40 LDR	D3, [SP, #360]

(945) 0x45fb44 LDR	X23, [SP, #200]

(945) 0x45fb48 FSUB	D15, D14, S9

(945) 0x45fb4c LDR	X24, [SP, #328]

(945) 0x45fb50 FMUL	D13, D12, D22

(945) 0x45fb54 LDR	X26, [SP, #336]

(945) 0x45fb58 FSUB	D7, D3, S10

(945) 0x45fb5c LDR	X28, [X23]

(945) 0x45fb60 LDR	X21, [X24, X6]

(945) 0x45fb64 FCMPE	D13, #0

(945) 0x45fb68 LDR	X20, [X26, X6]

(945) 0x45fb6c B.MI	4605c0

(945) 0x45fb70 LDR	W30, [X9, #56]

(945) 0x45fb74 FCVTZS	W27, D13

(945) 0x45fb78 SUB	W10, W30, #1

(945) 0x45fb7c CMP	W10, W27

(945) 0x45fb80 B.LT	460664

(945) 0x45fb84 ORR	X25, XZR, #0x55

(945) 0x45fb88 FRINTZ	D6, D13

(945) 0x45fb8c FSUB	D29, D13, S6

(945) 0x45fb90 MOVK	X25, #49093

(945) 0x45fb94 FMOV	D4, #0.5000000

(945) 0x45fb98 FMOV	D2, #-1.0000000

(945) 0x45fb9c FMOV	D25, #1.5000000

(945) 0x45fba0 FMOV	D16, #-2.0000000

(945) 0x45fba4 ORR	W10, WZR, W27

(945) 0x45fba8 FMOV	D0, X25

(945) 0x45fbac FMOV	D26, #1.0000000

(945) 0x45fbb0 FMOV	D17, #-0.5000000

(945) 0x45fbb4 FMOV	D18, #3.0000000

(945) 0x45fbb8 FSUB	D23, D6, S13

(945) 0x45fbbc LDR	D13, [SP, #208]

(945) 0x45fbc0 FMADD	D20, D29, D4, D2

(945) 0x45fbc4 FMSUB	D21, D29, D4, D4

(945) 0x45fbc8 FMUL	D28, D29, D29

(945) 0x45fbcc FMADD	D19, D29, D25, D16

(945) 0x45fbd0 FMSUB	D24, D29, D25, D26

(945) 0x45fbd4 FMADD	D27, D29, D18, D16

(945) 0x45fbd8 FMADD	D30, D29, D21, D4

(945) 0x45fbdc FMUL	D5, D29, D0

(945) 0x45fbe0 FADD	D8, D23, D26

(945) 0x45fbe4 FMADD	D9, D29, D24, D4

(945) 0x45fbe8 FMSUB	D26, D29, D18, D26

(945) 0x45fbec FMUL	D21, D28, D4

(945) 0x45fbf0 FMUL	D31, D29, D20

(945) 0x45fbf4 FMADD	D6, D29, D30, D1

(945) 0x45fbf8 FADD	D10, D5, D4

(945) 0x45fbfc FNMUL	D3, D28, D5

(945) 0x45fc00 STR	D8, [SP, #184]

(945) 0x45fc04 FMUL	D11, D29, D19

(945) 0x45fc08 STR	D27, [SP, #192]

(945) 0x45fc0c FMADD	D0, D29, D31, D13

(945) 0x45fc10 FADD	D14, D31, D4

(945) 0x45fc14 STR	D9, [SP, #176]

(945) 0x45fc18 FMADD	D12, D29, D10, D17

(945) 0x45fc1c STR	D11, [SP, #168]

(945) 0x45fc20 FNEG	D27, D14

(945) 0x45fc24 FMADD	D5, D29, D12, D1

(945) 0x45fc28 LDR	D25, [X9, #112]

(945) 0x45fc2c FMUL	D18, D15, D25

(945) 0x45fc30 FCMPE	D18, #0

(945) 0x45fc34 B.MI	460588

(945) 0x45fc38 LDR	W14, [X9, #96]

(945) 0x45fc3c FCVTZS	W13, D18

(945) 0x45fc40 SUB	W8, W14, #1

(945) 0x45fc44 CMP	W8, W13

(945) 0x45fc48 B.LT	4605fc

(945) 0x45fc4c ORR	X16, XZR, #0x55

(945) 0x45fc50 FRINTZ	D23, D18

(945) 0x45fc54 FSUB	D30, D18, S23

(945) 0x45fc58 MOVK	X16, #49093

(945) 0x45fc5c FMOV	D28, #0.5000000

(945) 0x45fc60 FMOV	D20, #-1.0000000

(945) 0x45fc64 FSUB	D10, D23, S18

(945) 0x45fc68 FMOV	D9, #1.0000000

(945) 0x45fc6c ORR	W8, WZR, W13

(945) 0x45fc70 FMOV	D17, X16

(945) 0x45fc74 FMOV	D16, #1.5000000

(945) 0x45fc78 FMOV	D8, #-2.0000000

(945) 0x45fc7c FMOV	D24, #3.0000000

(945) 0x45fc80 FMOV	D15, #-0.5000000

(945) 0x45fc84 FMSUB	D11, D30, D28, D28

(945) 0x45fc88 FMADD	D31, D30, D28, D20

(945) 0x45fc8c FMSUB	D19, D30, D16, D9

(945) 0x45fc90 FMUL	D12, D30, D30

(945) 0x45fc94 FMADD	D14, D30, D16, D8

(945) 0x45fc98 FADD	D18, D10, D9

(945) 0x45fc9c FMADD	D13, D30, D24, D8

(945) 0x45fca0 FMADD	D2, D30, D11, D28

(945) 0x45fca4 FMUL	D4, D30, D17

(945) 0x45fca8 FMSUB	D24, D30, D24, D9

(945) 0x45fcac LDR	D9, [SP, #208]

(945) 0x45fcb0 FMADD	D20, D30, D19, D28

(945) 0x45fcb4 FMADD	D23, D30, D2, D1

(945) 0x45fcb8 FMUL	D16, D30, D31

(945) 0x45fcbc FADD	D17, D4, D28

(945) 0x45fcc0 FNMUL	D4, D12, D4

(945) 0x45fcc4 STP	D18, D13, [SP, #240]

(945) 0x45fcc8 FMADD	D2, D30, D16, D9

(945) 0x45fccc STR	D20, [SP, #232]

(945) 0x45fcd0 FMADD	D8, D30, D17, D15

(945) 0x45fcd4 FMUL	D15, D30, D14

(945) 0x45fcd8 STR	D23, [SP, #216]

(945) 0x45fcdc FMUL	D23, D12, D28

(945) 0x45fce0 FADD	D28, D16, D28

(945) 0x45fce4 FMADD	D19, D30, D8, D1

(945) 0x45fce8 STR	D15, [SP, #224]

(945) 0x45fcec FNEG	D28, D28

(945) 0x45fcf0 LDR	D31, [X9, #152]

(945) 0x45fcf4 FMUL	D7, D7, D31

(945) 0x45fcf8 FCMPE	D7, #0

(945) 0x45fcfc B.MI	460550

(945) 0x45fd00 LDR	W7, [X9, #136]

(945) 0x45fd04 FCVTZS	W19, D7

(945) 0x45fd08 SUB	W12, W7, #1

(945) 0x45fd0c CMP	W12, W19

(945) 0x45fd10 B.LT	4606c8

(945) 0x45fd14 ORR	X4, XZR, #0x55

(945) 0x45fd18 FRINTZ	D12, D7

(945) 0x45fd1c FSUB	D15, D7, S12

(945) 0x45fd20 MOVK	X4, #49093

(945) 0x45fd24 FSUB	D11, D12, S7

(945) 0x45fd28 FMOV	D13, #1.0000000

(945) 0x45fd2c FMOV	D7, #3.0000000

(945) 0x45fd30 FMOV	D16, #1.5000000

(945) 0x45fd34 SBFM	X12, X19, #0, #31

(945) 0x45fd38 FMOV	D10, X4

(945) 0x45fd3c FMOV	D20, #0.5000000

(945) 0x45fd40 FMOV	D14, #-1.0000000

(945) 0x45fd44 FMOV	D9, #-2.0000000

(945) 0x45fd48 FMSUB	D18, D15, D16, D13

(945) 0x45fd4c FMSUB	D12, D15, D7, D13

(945) 0x45fd50 FMUL	D17, D15, D15

(945) 0x45fd54 FADD	D13, D11, D13

(945) 0x45fd58 FMSUB	D8, D15, D20, D20

(945) 0x45fd5c FMADD	D14, D15, D20, D14

(945) 0x45fd60 FMADD	D16, D15, D16, D9

(945) 0x45fd64 FMADD	D9, D15, D7, D9

(945) 0x45fd68 FMUL	D11, D15, D10

(945) 0x45fd6c FMADD	D18, D15, D18, D20

(945) 0x45fd70 FMADD	D7, D15, D8, D20

(945) 0x45fd74 FMUL	D10, D17, D20

(945) 0x45fd78 FADD	D20, D11, D20

(945) 0x45fd7c FNMUL	D17, D17, D11

(945) 0x45fd80 FMOV	D11, #-0.5000000

(945) 0x45fd84 FMUL	D14, D15, D14

(945) 0x45fd88 FMADD	D8, D15, D7, D1

(945) 0x45fd8c LDR	D7, [SP, #208]

(945) 0x45fd90 STR	D16, [SP, #256]

(945) 0x45fd94 LDR	D16, [SP, #256]

(945) 0x45fd98 FMADD	D20, D15, D20, D11

(945) 0x45fd9c FMADD	D7, D15, D14, D7

(945) 0x45fda0 FSUB	D14, D11, S14

(945) 0x45fda4 FMUL	D16, D15, D16

(945) 0x45fda8 FMADD	D11, D15, D20, D1

(945) 0x45fdac LDR	D20, [SP, #216]

(945) 0x45fdb0 ADD	X7, SP, #520

(945) 0x45fdb4 LDRSW	X30, [X9, #232]

(945) 0x45fdb8 STP	D5, D0, [SP, #464]

(945) 0x45fdbc STP	D6, D3, [SP, #480]

(945) 0x45fdc0 STP	D19, D2, [SP, #496]

(945) 0x45fdc4 STR	D20, [SP, #512]

(945) 0x45fdc8 STP	D4, D27, [X7]

(945) 0x45fdcc ADD	X22, X20, X30,LSL #4

(945) 0x45fdd0 UBFM	X4, X30, #61, #60

(945) 0x45fdd4 STP	D21, D28, [X7, #32]

(945) 0x45fdd8 ADD	X25, X21, X30,LSL #3

(945) 0x45fddc LDR	D27, [SP, #168]

(945) 0x45fde0 ADD	X23, X22, X30,LSL #4

(945) 0x45fde4 STR	D26, [SP, #608]

(945) 0x45fde8 ADD	X24, X22, X30,LSL #3

(945) 0x45fdec LDR	D5, [SP, #176]

(945) 0x45fdf0 ADD	X27, X23, X30,LSL #3

(945) 0x45fdf4 STR	D29, [SP, #616]

(945) 0x45fdf8 ADD	X26, X21, X30,LSL #4

(945) 0x45fdfc LDR	D0, [SP, #184]

(945) 0x45fe00 ADD	X19, X20, X30,LSL #3

(945) 0x45fe04 STR	D23, [SP, #584]

(945) 0x45fe08 LDR	D6, [SP, #192]

(945) 0x45fe0c STR	D27, [SP, #536]

(945) 0x45fe10 LDR	D3, [SP, #224]

(945) 0x45fe14 STR	D5, [SP, #544]

(945) 0x45fe18 LDR	D21, [SP, #232]

(945) 0x45fe1c STR	D0, [SP, #592]

(945) 0x45fe20 LDR	D26, [SP, #240]

(945) 0x45fe24 STR	D6, [SP, #600]

(945) 0x45fe28 LDR	D29, [SP, #248]

(945) 0x45fe2c STR	D3, [SP, #568]

(945) 0x45fe30 STR	D21, [SP, #576]

(945) 0x45fe34 STR	D24, [SP, #640]

(945) 0x45fe38 STR	D26, [SP, #624]

(945) 0x45fe3c STR	D30, [SP, #648]

(945) 0x45fe40 STR	D29, [SP, #632]

(945) 0x45fe44 LDR	X3, [X9, #32]

(945) 0x45fe48 LDP	X11, X13, [X9, #16]

(945) 0x45fe4c CBZ	X2, 45ff58

(945) 0x45fe50 MOVZ	W1, #0

(945) 0x45fe54 ORR	X0, XZR, X28

(945) 0x45fe58 STP	X2, X9, [SP, #168]

(945) 0x45fe5c STR	D22, [SP, #184]

(945) 0x45fe60 STR	W10, [SP, #192]

(945) 0x45fe64 STR	D25, [SP, #216]

(945) 0x45fe68 STR	W8, [SP, #224]

(945) 0x45fe6c STR	D31, [SP, #232]

(945) 0x45fe70 STP	X11, X13, [SP, #240]

(945) 0x45fe74 STP	X3, X4, [SP, #256]

(945) 0x45fe78 STR	X12, [SP, #272]

(945) 0x45fe7c STP	D7, D17, [SP, #280]

(945) 0x45fe80 STP	D16, D18, [SP, #296]

(945) 0x45fe84 STP	X6, X5, [SP, #312]

(945) 0x45fe88 BL	4104e0

(945) 0x45fe8c LDR	X2, [SP, #168]

(945) 0x45fe90 MOVZ	W1, #0

(945) 0x45fe94 ORR	X0, XZR, X21

(945) 0x45fe98 BL	4104e0

(945) 0x45fe9c LDR	X2, [SP, #168]

(945) 0x45fea0 MOVZ	W1, #0

(945) 0x45fea4 ORR	X0, XZR, X25

(945) 0x45fea8 BL	4104e0

(945) 0x45feac LDR	X2, [SP, #168]

(945) 0x45feb0 MOVZ	W1, #0

(945) 0x45feb4 ORR	X0, XZR, X26

(945) 0x45feb8 BL	4104e0

(945) 0x45febc LDR	X2, [SP, #168]

(945) 0x45fec0 MOVZ	W1, #0

(945) 0x45fec4 ORR	X0, XZR, X20

(945) 0x45fec8 BL	4104e0

(945) 0x45fecc LDR	X2, [SP, #168]

(945) 0x45fed0 MOVZ	W1, #0

(945) 0x45fed4 ORR	X0, XZR, X19

(945) 0x45fed8 BL	4104e0

(945) 0x45fedc LDR	X2, [SP, #168]

(945) 0x45fee0 MOVZ	W1, #0

(945) 0x45fee4 ORR	X0, XZR, X22

(945) 0x45fee8 BL	4104e0

(945) 0x45feec LDR	X2, [SP, #168]

(945) 0x45fef0 MOVZ	W1, #0

(945) 0x45fef4 ORR	X0, XZR, X24

(945) 0x45fef8 BL	4104e0

(945) 0x45fefc LDR	X2, [SP, #168]

(945) 0x45ff00 MOVZ	W1, #0

(945) 0x45ff04 ORR	X0, XZR, X23

(945) 0x45ff08 BL	4104e0

(945) 0x45ff0c LDR	X2, [SP, #168]

(945) 0x45ff10 ORR	X0, XZR, X27

(945) 0x45ff14 MOVZ	W1, #0

(945) 0x45ff18 BL	4104e0

(945) 0x45ff1c LDR	D22, [SP, #184]

(945) 0x45ff20 ADRP	X18,

(945) 0x45ff24 LDP	X2, X9, [SP, #168]

(945) 0x45ff28 LDP	X11, X13, [SP, #240]

(945) 0x45ff2c LDP	X3, X4, [SP, #256]

(945) 0x45ff30 LDP	X6, X5, [SP, #312]

(945) 0x45ff34 LDR	D25, [SP, #216]

(945) 0x45ff38 LDR	D31, [SP, #232]

(945) 0x45ff3c LDP	D7, D17, [SP, #280]

(945) 0x45ff40 LDP	D16, D18, [SP, #296]

(945) 0x45ff44 LDR	X12, [SP, #272]

(945) 0x45ff48 LDR	W10, [SP, #192]

(945) 0x45ff4c LDR	W8, [SP, #224]

(945) 0x45ff50 LDR	D1, [X18, #3408]

(945) 0x45ff54 ADD	X18, SP, #624

(945) 0x45ff58 MUL	X16, X3, X12

(945) 0x45ff5c LDR	W1, [SP, #380]

(945) 0x45ff60 LDR	X9, [X9, #8]

(945) 0x45ff64 CMP	W1, #0

(945) 0x45ff68 B.LE	460734

(945) 0x45ff6c SBFM	X14, X8, #0, #31

(945) 0x45ff70 ADD	X30, X3, X3,LSL #1

(945) 0x45ff74 SBFM	X0, X10, #0, #31

(945) 0x45ff78 SUB	X15, XZR, X3,LSL #3

(945) 0x45ff7c UBFM	X10, X13, #61, #60

(945) 0x45ff80 MOVZ	X12, #1

(945) 0x45ff84 MUL	X8, X14, X13

(945) 0x45ff88 ADD	X17, SP, #528

(945) 0x45ff8c ADD	X14, SP, #496

(945) 0x45ff90 MADD	X0, X0, X11, X16

(945) 0x45ff94 ADD	X13, SP, #560

(945) 0x45ff98 ADD	X16, SP, #592

(945) 0x45ff9c STP	D22, D25, [SP, #216]

(945) 0x45ffa0 ADD	X7, X8, X3,LSL #1

(945) 0x45ffa4 ADD	X1, X30, X8

(945) 0x45ffa8 ADD	X3, X3, X8

(945) 0x45ffac ADD	X8, X9, X3,LSL #3

(945) 0x45ffb0 ADD	X30, SP, #464

(945) 0x45ffb4 STP	X4, X6, [SP, #232]

(945) 0x45ffb8 ADD	X7, X9, X7,LSL #3

(945) 0x45ffbc ADD	X9, X9, X1,LSL #3

(945) 0x45ffc0 STR	X5, [SP, #248]

(945) 0x45ffc4 STP	X7, X8, [SP, #184]

(945) 0x45ffc8 STP	X11, X9, [SP, #168]

  (948) 0x45ffcc ADD	X6, X30, X12,LSL #3

  (948) 0x45ffd0 MOVZ	X7, #1

  (948) 0x45ffd4 ADD	X5, X16, X12,LSL #3

  (948) 0x45ffd8 LDR	X8, [SP, #176]

  (948) 0x45ffdc ADD	X4, X17, X12,LSL #3

  (948) 0x45ffe0 LDR	X1, [SP, #184]

  (948) 0x45ffe4 LDR	X11, [SP, #192]

  (948) 0x45ffe8 LDUR	D5, [X6, #504]

  (948) 0x45ffec LDUR	D3, [X5, #504]

  (948) 0x45fff0 ADD	X5, X1, X0,LSL #3

  (948) 0x45fff4 ADD	X3, X11, X0,LSL #3

  (948) 0x45fff8 LDUR	D4, [X4, #504]

  (948) 0x45fffc ADD	X4, X8, X0,LSL #3

    (947) 0x460000 ADD	X11, X14, X7,LSL #3

    (947) 0x460004 MOVZ	X1, #0

    (947) 0x460008 ADD	X6, X3, X15

    (947) 0x46000c ADD	X9, X13, X7,LSL #3

    (947) 0x460010 ADD	X8, X18, X7,LSL #3

    (947) 0x460014 LDUR	D28, [X11, #504]

    (947) 0x460018 LDUR	D22, [X8, #504]

    (947) 0x46001c LDUR	D25, [X9, #504]

    (947) 0x460020 FMUL	D6, D3, D28

    (947) 0x460024 FMUL	D21, D28, D4

    (947) 0x460028 FMUL	D23, D28, D5

    (947) 0x46002c FMUL	D20, D5, D22

    (947) 0x460030 FMUL	D19, D4, D25

    (947) 0x460034 FMUL	D22, D5, D25

    (947) 0x460038 HINT	#0

    (947) 0x46003c HINT	#0

      (946) 0x460040 LDR	D2, [X3, X1]

      (946) 0x460044 LDR	D29, [X4, X1]

      (946) 0x460048 LDR	D0, [X6, X1]

      (946) 0x46004c LDR	D26, [X5, X1]

      (946) 0x460050 FMUL	D30, D2, D7

      (946) 0x460054 FMUL	D24, D2, D16

      (946) 0x460058 FMUL	D27, D2, D9

      (946) 0x46005c FMUL	D2, D29, D17

      (946) 0x460060 LDR	D25, [X20, X1]

      (946) 0x460064 FMUL	D28, D29, D10

      (946) 0x460068 FMUL	D29, D29, D15

      (946) 0x46006c FMADD	D30, D0, D11, D30

      (946) 0x460070 FMADD	D24, D0, D14, D24

      (946) 0x460074 FMADD	D27, D0, D13, D27

      (946) 0x460078 LDR	D0, [X21, X1]

      (946) 0x46007c FMADD	D2, D26, D8, D2

      (946) 0x460080 FMADD	D28, D26, D18, D28

      (946) 0x460084 FMADD	D29, D26, D12, D29

      (946) 0x460088 LDR	D26, [X28, X1]

      (946) 0x46008c FADD	D30, D30, D2

      (946) 0x460090 FADD	D24, D28, D24

      (946) 0x460094 FADD	D2, D27, D29

      (946) 0x460098 FMADD	D25, D6, D30, D25

      (946) 0x46009c FMADD	D27, D21, D30, D0

      (946) 0x4600a0 FMADD	D28, D23, D30, D26

      (946) 0x4600a4 STR	D25, [X20, X1]

      (946) 0x4600a8 LDR	D29, [X19, X1]

      (946) 0x4600ac STR	D27, [X21, X1]

      (946) 0x4600b0 LDR	D0, [X25, X1]

      (946) 0x4600b4 STR	D28, [X28, X1]

      (946) 0x4600b8 FMADD	D25, D19, D30, D29

      (946) 0x4600bc FMADD	D26, D22, D30, D0

      (946) 0x4600c0 STR	D25, [X19, X1]

      (946) 0x4600c4 LDR	D27, [X22, X1]

      (946) 0x4600c8 STR	D26, [X25, X1]

      (946) 0x4600cc LDR	D28, [X26, X1]

      (946) 0x4600d0 FMADD	D29, D21, D24, D27

      (946) 0x4600d4 FMADD	D0, D23, D24, D28

      (946) 0x4600d8 STR	D29, [X22, X1]

      (946) 0x4600dc LDR	D25, [X24, X1]

      (946) 0x4600e0 STR	D0, [X26, X1]

      (946) 0x4600e4 FMADD	D30, D20, D30, D25

      (946) 0x4600e8 STR	D30, [X24, X1]

      (946) 0x4600ec LDR	D26, [X23, X1]

      (946) 0x4600f0 FMADD	D24, D22, D24, D26

      (946) 0x4600f4 STR	D24, [X23, X1]

      (946) 0x4600f8 LDR	D27, [X27, X1]

      (946) 0x4600fc FMADD	D2, D23, D2, D27

      (946) 0x460100 STR	D2, [X27, X1]

      (946) 0x460104 ADD	X1, X1, #8

      (946) 0x460108 CMP	X2, X1

      (946) 0x46010c B.NE	460040

    (947) 0x460110 ADD	X7, X7, #1

    (947) 0x460114 ADD	X3, X3, X10

    (947) 0x460118 ADD	X5, X5, X10

    (947) 0x46011c ADD	X4, X4, X10

    (947) 0x460120 CMP	X7, #5

    (947) 0x460124 B.NE	460000

  (948) 0x460128 LDR	X7, [SP, #168]

  (948) 0x46012c ADD	X12, X12, #1

  (948) 0x460130 ADD	X0, X0, X7

  (948) 0x460134 CMP	X12, #5

  (948) 0x460138 B.NE	45ffcc

(945) 0x46013c LDP	D22, D25, [SP, #216]

(945) 0x460140 LDP	X4, X6, [SP, #232]

(945) 0x460144 LDR	X5, [SP, #248]

(945) 0x460148 FMUL	D3, D22, D22

(945) 0x46014c FMUL	D4, D25, D25

(945) 0x460150 MOVZ	X3, #0

(945) 0x460154 FMUL	D5, D31, D31

(945) 0x460158 FMUL	D7, D22, D25

(945) 0x46015c FMUL	D8, D22, D31

(945) 0x460160 FMUL	D9, D25, D31

(945) 0x460164 TBZ	W2, #3, 4601e0

(945) 0x460168 LDR	D10, [X20]

(945) 0x46016c MOVZ	X3, #8

(945) 0x460170 LDR	D12, [X21]

(945) 0x460174 FMUL	D11, D10, D3

(945) 0x460178 FMUL	D13, D12, D22

(945) 0x46017c STR	D11, [X20]

(945) 0x460180 LDR	D14, [X22, X4]

(945) 0x460184 STR	D13, [X21]

(945) 0x460188 LDR	D28, [X21, X4]

(945) 0x46018c FMUL	D15, D14, D4

(945) 0x460190 FMUL	D29, D28, D25

(945) 0x460194 STR	D15, [X22, X4]

(945) 0x460198 LDR	D16, [X23, X4]

(945) 0x46019c STR	D29, [X21, X4]

(945) 0x4601a0 LDR	D0, [X25, X4]

(945) 0x4601a4 FMUL	D17, D16, D5

(945) 0x4601a8 FMUL	D30, D0, D31

(945) 0x4601ac STR	D17, [X23, X4]

(945) 0x4601b0 LDR	D18, [X20, X4]

(945) 0x4601b4 STR	D30, [X25, X4]

(945) 0x4601b8 FMUL	D20, D18, D7

(945) 0x4601bc STR	D20, [X20, X4]

(945) 0x4601c0 LDR	D19, [X19, X4]

(945) 0x4601c4 FMUL	D6, D19, D8

(945) 0x4601c8 STR	D6, [X19, X4]

(945) 0x4601cc LDR	D21, [X24, X4]

(945) 0x4601d0 FMUL	D23, D21, D9

(945) 0x4601d4 STR	D23, [X24, X4]

(945) 0x4601d8 CMP	X3, X2

(945) 0x4601dc B.EQ	4602c8

  (944) 0x4601e0 LDR	D26, [X20, X3]

  (944) 0x4601e4 ADD	X10, X3, #8

  (944) 0x4601e8 LDR	D24, [X21, X3]

  (944) 0x4601ec FMUL	D27, D26, D3

  (944) 0x4601f0 FMUL	D2, D24, D22

  (944) 0x4601f4 STR	D27, [X20, X3]

  (944) 0x4601f8 LDR	D10, [X24, X3]

  (944) 0x4601fc STR	D2, [X21, X3]

  (944) 0x460200 LDR	D11, [X25, X3]

  (944) 0x460204 FMUL	D12, D10, D4

  (944) 0x460208 FMUL	D13, D11, D25

  (944) 0x46020c STR	D12, [X24, X3]

  (944) 0x460210 LDR	D14, [X27, X3]

  (944) 0x460214 STR	D13, [X25, X3]

  (944) 0x460218 LDR	D15, [X26, X3]

  (944) 0x46021c FMUL	D16, D14, D5

  (944) 0x460220 FMUL	D17, D15, D31

  (944) 0x460224 STR	D16, [X27, X3]

  (944) 0x460228 LDR	D18, [X19, X3]

  (944) 0x46022c STR	D17, [X26, X3]

  (944) 0x460230 LDR	D20, [X21, X10]

  (944) 0x460234 FMUL	D19, D18, D7

  (944) 0x460238 FMUL	D6, D20, D22

  (944) 0x46023c STR	D19, [X19, X3]

  (944) 0x460240 LDR	D21, [X22, X3]

  (944) 0x460244 STR	D6, [X21, X10]

  (944) 0x460248 LDR	D23, [X25, X10]

  (944) 0x46024c FMUL	D28, D21, D8

  (944) 0x460250 FMUL	D29, D23, D25

  (944) 0x460254 STR	D28, [X22, X3]

  (944) 0x460258 LDR	D0, [X23, X3]

  (944) 0x46025c STR	D29, [X25, X10]

  (944) 0x460260 LDR	D26, [X26, X10]

  (944) 0x460264 FMUL	D30, D0, D9

  (944) 0x460268 FMUL	D24, D26, D31

  (944) 0x46026c STR	D30, [X23, X3]

  (944) 0x460270 ADD	X3, X10, #8

  (944) 0x460274 LDR	D27, [X20, X10]

  (944) 0x460278 STR	D24, [X26, X10]

  (944) 0x46027c FMUL	D2, D27, D3

  (944) 0x460280 STR	D2, [X20, X10]

  (944) 0x460284 LDR	D10, [X24, X10]

  (944) 0x460288 FMUL	D11, D10, D4

  (944) 0x46028c STR	D11, [X24, X10]

  (944) 0x460290 LDR	D12, [X27, X10]

  (944) 0x460294 FMUL	D13, D12, D5

  (944) 0x460298 STR	D13, [X27, X10]

  (944) 0x46029c LDR	D14, [X19, X10]

  (944) 0x4602a0 FMUL	D15, D14, D7

  (944) 0x4602a4 STR	D15, [X19, X10]

  (944) 0x4602a8 LDR	D16, [X22, X10]

  (944) 0x4602ac FMUL	D17, D16, D8

  (944) 0x4602b0 STR	D17, [X22, X10]

  (944) 0x4602b4 LDR	D18, [X23, X10]

  (944) 0x4602b8 FMUL	D20, D18, D9

  (944) 0x4602bc STR	D20, [X23, X10]

  (944) 0x4602c0 CMP	X3, X2

  (944) 0x4602c4 B.NE	4601e0

(945) 0x4602c8 LDR	X13, [SP, #200]

(945) 0x4602cc ADD	X5, X5, #8

(945) 0x4602d0 ADD	X6, X6, #40

(945) 0x4602d4 LDR	X15, [SP, #368]

(945) 0x4602d8 ADD	X14, X13, #24

(945) 0x4602dc STR	X14, [SP, #200]

(945) 0x4602e0 CMP	X15, X5

(945) 0x4602e4 B.NE	45fb24

0x4602e8 LDP	D8, D9, [SP, #96]

0x4602ec LDP	X24, X20, [SP, #392]

0x4602f0 LDP	X23, X22, [SP, #408]

0x4602f4 LDP	D10, D11, [SP, #112]

0x4602f8 LDP	D12, D13, [SP, #128]

0x4602fc LDP	D14, D15, [SP, #144]

0x460300 LDR	X21, [SP, #424]

0x460304 ORR	X0, XZR, X24

0x460308 BL	4cfaa0

0x46030c LDR	W24, [X20, #48]

0x460310 CMP	W24, #0

0x460314 B.LE	460530

0x460318 LDR	W27, [X20, #64]

0x46031c MOVZ	W18, #24

0x460320 MOVZ	X2, #0

0x460324 MOVZ	X17, #0

0x460328 MOVZ	X16, #0

0x46032c LDR	W19, [X20, #8]

0x460330 UMULL	X18, W24, W18

0x460334 MOVZ	X15, #0

0x460338 UBFM	X28, X24, #61, #31

0x46033c MOVZ	W14, #0

0x460340 STR	X2, [SP, #168]

0x460344 ORR	W4, WZR, W27

(942) 0x460348 CMP	W4, W19

(942) 0x46034c CSEL	W25, W4, W19, #13

(942) 0x460350 CMP	W14, W25

(942) 0x460354 B.GE	460508

(942) 0x460358 LDR	X11, [X20, #808]

(942) 0x46035c SUB	W26, W25, W14

(942) 0x460360 MOVZ	X0, #0

(942) 0x460364 ANDS	X25, X26, #0x3

(942) 0x460368 LDR	X9, [X20, #832]

(942) 0x46036c LDR	X3, [X21, #24]

(942) 0x460370 ADD	X8, X11, X16

(942) 0x460374 LDR	X5, [X22, #24]

(942) 0x460378 ADD	X1, X9, X16

(942) 0x46037c LDR	X6, [X23, #24]

(942) 0x460380 LDR	X2, [SP, #168]

(942) 0x460384 LDR	X30, [X20, #784]

(942) 0x460388 LDRSW	X7, [X8, #8]

(942) 0x46038c ADD	X13, X6, X2

(942) 0x460390 ADD	X11, X3, X2

(942) 0x460394 LDR	X8, [X8, #24]

(942) 0x460398 LDR	X10, [X30, X15]

(942) 0x46039c UBFM	X2, X7, #60, #59

(942) 0x4603a0 UBFM	X30, X7, #61, #60

(942) 0x4603a4 LDR	X9, [X1, #24]

(942) 0x4603a8 ADD	X1, X5, X17

(942) 0x4603ac ADD	X12, X8, X7,LSL #3

(942) 0x4603b0 ADD	X7, X8, X7,LSL #4

(942) 0x4603b4 B.EQ	460458

(942) 0x4603b8 CMP	X25, #1

(942) 0x4603bc B.EQ	460424

(942) 0x4603c0 CMP	X25, #2

(942) 0x4603c4 B.EQ	4603f8

(942) 0x4603c8 LDR	D1, [X10]

(942) 0x4603cc MOVZ	X0, #1

(942) 0x4603d0 ADD	X1, X1, #24

(942) 0x4603d4 LDR	X25, [SP, #168]

(942) 0x4603d8 STR	D1, [X6, X25]

(942) 0x4603dc LDR	D25, [X8]

(942) 0x4603e0 LDR	D22, [X8, X30]

(942) 0x4603e4 LDR	D31, [X8, X2]

(942) 0x4603e8 STR	D25, [X5, X17]

(942) 0x4603ec STP	D22, D31, [X1, #1008]

(942) 0x4603f0 LDR	D3, [X9]

(942) 0x4603f4 STR	D3, [X3, X25]

(942) 0x4603f8 LDR	D4, [X10, X0,LSL #3]

(942) 0x4603fc ADD	X1, X1, #24

(942) 0x460400 STR	D4, [X13, X0,LSL #3]

(942) 0x460404 LDR	D5, [X8, X0,LSL #3]

(942) 0x460408 LDR	D7, [X12, X0,LSL #3]

(942) 0x46040c LDR	D19, [X7, X0,LSL #3]

(942) 0x460410 STP	D5, D7, [X1, #1000]

(942) 0x460414 STUR	D19, [X1, #504]

(942) 0x460418 LDR	D6, [X9, X0,LSL #3]

(942) 0x46041c STR	D6, [X11, X0,LSL #3]

(942) 0x460420 ADD	X0, X0, #1

(942) 0x460424 LDR	D21, [X10, X0,LSL #3]

(942) 0x460428 ADD	X1, X1, #24

(942) 0x46042c STR	D21, [X13, X0,LSL #3]

(942) 0x460430 LDR	D23, [X8, X0,LSL #3]

(942) 0x460434 LDR	D28, [X12, X0,LSL #3]

(942) 0x460438 LDR	D29, [X7, X0,LSL #3]

(942) 0x46043c STP	D23, D28, [X1, #1000]

(942) 0x460440 STUR	D29, [X1, #504]

(942) 0x460444 LDR	D0, [X9, X0,LSL #3]

(942) 0x460448 STR	D0, [X11, X0,LSL #3]

(942) 0x46044c ADD	X0, X0, #1

(942) 0x460450 CMP	X26, X0

(942) 0x460454 B.EQ	460508

  (943) 0x460458 LDR	D26, [X10, X0,LSL #3]

  (943) 0x46045c ADD	X30, X0, #1

  (943) 0x460460 ADD	X5, X0, #2

  (943) 0x460464 ADD	X3, X0, #3

  (943) 0x460468 ADD	X2, X1, #72

  (943) 0x46046c ADD	X1, X1, #96

  (943) 0x460470 STR	D26, [X13, X0,LSL #3]

  (943) 0x460474 LDR	D24, [X8, X0,LSL #3]

  (943) 0x460478 LDR	D30, [X12, X0,LSL #3]

  (943) 0x46047c LDR	D27, [X7, X0,LSL #3]

  (943) 0x460480 STP	D24, D30, [X1, #928]

  (943) 0x460484 STUR	D27, [X1, #432]

  (943) 0x460488 LDR	D2, [X9, X0,LSL #3]

  (943) 0x46048c STR	D2, [X11, X0,LSL #3]

  (943) 0x460490 ADD	X0, X0, #4

  (943) 0x460494 LDR	D16, [X10, X30,LSL #3]

  (943) 0x460498 STR	D16, [X13, X30,LSL #3]

  (943) 0x46049c LDR	D17, [X8, X30,LSL #3]

  (943) 0x4604a0 LDR	D18, [X12, X30,LSL #3]

  (943) 0x4604a4 LDR	D20, [X7, X30,LSL #3]

  (943) 0x4604a8 STP	D17, D18, [X1, #952]

  (943) 0x4604ac STUR	D20, [X1, #456]

  (943) 0x4604b0 LDR	D1, [X9, X30,LSL #3]

  (943) 0x4604b4 STR	D1, [X11, X30,LSL #3]

  (943) 0x4604b8 LDR	D22, [X10, X5,LSL #3]

  (943) 0x4604bc STR	D22, [X13, X5,LSL #3]

  (943) 0x4604c0 LDR	D25, [X8, X5,LSL #3]

  (943) 0x4604c4 LDR	D3, [X12, X5,LSL #3]

  (943) 0x4604c8 LDR	D31, [X7, X5,LSL #3]

  (943) 0x4604cc STP	D25, D3, [X1, #976]

  (943) 0x4604d0 STUR	D31, [X1, #480]

  (943) 0x4604d4 LDR	D4, [X9, X5,LSL #3]

  (943) 0x4604d8 STR	D4, [X11, X5,LSL #3]

  (943) 0x4604dc LDR	D5, [X10, X3,LSL #3]

  (943) 0x4604e0 STR	D5, [X13, X3,LSL #3]

  (943) 0x4604e4 LDR	D19, [X12, X3,LSL #3]

  (943) 0x4604e8 LDR	D6, [X7, X3,LSL #3]

  (943) 0x4604ec LDR	D7, [X8, X3,LSL #3]

  (943) 0x4604f0 STUR	D7, [X1, #488]

  (943) 0x4604f4 STP	D19, D6, [X2, #8]

  (943) 0x4604f8 LDR	D21, [X9, X3,LSL #3]

  (943) 0x4604fc STR	D21, [X11, X3,LSL #3]

  (943) 0x460500 CMP	X26, X0

  (943) 0x460504 B.NE	460458

(942) 0x460508 LDR	X26, [SP, #168]

(942) 0x46050c ADD	X15, X15, #24

(942) 0x460510 ADD	W4, W4, W27

(942) 0x460514 ADD	W14, W14, W24

(942) 0x460518 ADD	X16, X16, #40

(942) 0x46051c ADD	X17, X17, X18

(942) 0x460520 ADD	X10, X26, X28

(942) 0x460524 STR	X10, [SP, #168]

(942) 0x460528 CMP	X18, X15

(942) 0x46052c B.NE	460348

0x460530 LDP	X29, X30, [SP]

0x460534 LDP	X19, X20, [SP, #16]

0x460538 LDP	X21, X22, [SP, #32]

0x46053c LDP	X23, X24, [SP, #48]

0x460540 LDP	X25, X26, [SP, #64]

0x460544 LDP	X27, X28, [SP, #80]

0x460548 ADD	SP, SP, #656

0x46054c RET

(945) 0x460550 MOVI	D10, #0

(945) 0x460554 FMOV	D12, #1.0000000

(945) 0x460558 LDR	D7, [SP, #208]

(945) 0x46055c FMOV	D8, D1

(945) 0x460560 FMOV	D9, #-2.0000000

(945) 0x460564 MOVZ	X12, #0

(945) 0x460568 FMOV	D11, D1

(945) 0x46056c FMOV	D18, #0.5000000

(945) 0x460570 FMOV	D14, #-0.5000000

(945) 0x460574 FMOV	D13, D12

(945) 0x460578 FMOV	D16, D10

(945) 0x46057c FMOV	D17, D10

(945) 0x460580 FMOV	D15, D10

(945) 0x460584 B	45fdac

(945) 0x460588 MOVI	D23, #0

(945) 0x46058c FMOV	D24, #1.0000000

(945) 0x460590 LDR	D2, [SP, #208]

(945) 0x460594 FMOV	D31, #-2.0000000

(945) 0x460598 FMOV	D11, #0.5000000

(945) 0x46059c MOVZ	W8, #0

(945) 0x4605a0 FMOV	D28, #-0.5000000

(945) 0x4605a4 FMOV	D19, D1

(945) 0x4605a8 FMOV	D4, D23

(945) 0x4605ac FMOV	D30, D23

(945) 0x4605b0 STP	D1, D23, [SP, #216]

(945) 0x4605b4 STR	D11, [SP, #232]

(945) 0x4605b8 STP	D24, D31, [SP, #240]

(945) 0x4605bc B	45fcf0

(945) 0x4605c0 MOVI	D21, #0

(945) 0x4605c4 FMOV	D26, #1.0000000

(945) 0x4605c8 LDR	D0, [SP, #208]

(945) 0x4605cc FMOV	D4, #-2.0000000

(945) 0x4605d0 FMOV	D2, #0.5000000

(945) 0x4605d4 MOVZ	W10, #0

(945) 0x4605d8 FMOV	D27, #-0.5000000

(945) 0x4605dc FMOV	D6, D1

(945) 0x4605e0 FMOV	D5, D1

(945) 0x4605e4 FMOV	D3, D21

(945) 0x4605e8 FMOV	D29, D21

(945) 0x4605ec STR	D21, [SP, #168]

(945) 0x4605f0 STR	D2, [SP, #176]

(945) 0x4605f4 STP	D26, D4, [SP, #184]

(945) 0x4605f8 B	45fc28

(945) 0x4605fc LDR	D10, [SP, #208]

(945) 0x460600 MOVI	D28, #0

(945) 0x460604 MOVN	X15, #3

(945) 0x460608 MOVN	X17, #7

(945) 0x46060c MOVN	X23, #3

(945) 0x460610 MOVZ	X27, #3

(945) 0x460614 MOVN	X30, #1

(945) 0x460618 MOVK	X15, #49151

(945) 0x46061c MOVK	X17, #16367

(945) 0x460620 MOVZ	X22, #15536

(945) 0x460624 MOVK	X23, #16351

(945) 0x460628 FMOV	D19, D28

(945) 0x46062c ADRP	X24,

(945) 0x460630 MOVZ	X26, #15556

(945) 0x460634 FMOV	D24, X15

(945) 0x460638 MOVK	X27, #49120

(945) 0x46063c MOVK	X30, #16367

(945) 0x460640 FMOV	D23, X23

(945) 0x460644 ADRP	X25,

(945) 0x460648 LDR	D4, [X24, #3392]

(945) 0x46064c FMOV	D30, X30

(945) 0x460650 LDR	D2, [X25, #3400]

(945) 0x460654 STR	D10, [SP, #216]

(945) 0x460658 STP	X27, X26, [SP, #224]

(945) 0x46065c STP	X22, X17, [SP, #240]

(945) 0x460660 B	45fcf0

(945) 0x460664 MOVI	D27, #0

(945) 0x460668 MOVN	X19, #3

(945) 0x46066c MOVN	X8, #7

(945) 0x460670 MOVN	X4, #3

(945) 0x460674 MOVZ	X1, #3

(945) 0x460678 LDR	D6, [SP, #208]

(945) 0x46067c MOVN	X12, #1

(945) 0x460680 MOVK	X19, #49151

(945) 0x460684 MOVK	X8, #16367

(945) 0x460688 MOVZ	X7, #15536

(945) 0x46068c MOVK	X4, #16351

(945) 0x460690 ADRP	X0,

(945) 0x460694 FMOV	D26, X19

(945) 0x460698 MOVZ	X3, #15556

(945) 0x46069c MOVK	X1, #49120

(945) 0x4606a0 FMOV	D5, D27

(945) 0x4606a4 MOVK	X12, #16367

(945) 0x4606a8 ADRP	X11,

(945) 0x4606ac FMOV	D21, X4

(945) 0x4606b0 LDR	D3, [X0, #3392]

(945) 0x4606b4 FMOV	D29, X12

(945) 0x4606b8 LDR	D0, [X11, #3400]

(945) 0x4606bc STP	X1, X3, [SP, #168]

(945) 0x4606c0 STP	X7, X8, [SP, #184]

(945) 0x4606c4 B	45fc28

(945) 0x4606c8 MOVI	D14, #0

(945) 0x4606cc MOVN	X0, #7

(945) 0x4606d0 MOVN	X1, #3

(945) 0x4606d4 MOVK	X0, #16367

(945) 0x4606d8 MOVN	X13, #3

(945) 0x4606dc LDR	D8, [SP, #208]

(945) 0x4606e0 MOVZ	X16, #3

(945) 0x4606e4 MOVK	X1, #49151

(945) 0x4606e8 MOVZ	X11, #15536

(945) 0x4606ec MOVK	X13, #16351

(945) 0x4606f0 FMOV	D9, X0

(945) 0x4606f4 ADRP	X3,

(945) 0x4606f8 MOVZ	X14, #15556

(945) 0x4606fc FMOV	D12, X1

(945) 0x460700 MOVK	X16, #49120

(945) 0x460704 ADD	X15, X0, #6

(945) 0x460708 FMOV	D13, X11

(945) 0x46070c ADRP	X17,

(945) 0x460710 FMOV	D10, X13

(945) 0x460714 SBFM	X12, X12, #0, #31

(945) 0x460718 FMOV	D18, X14

(945) 0x46071c FMOV	D16, X16

(945) 0x460720 FMOV	D15, X15

(945) 0x460724 LDR	D17, [X3, #3392]

(945) 0x460728 FMOV	D11, D14

(945) 0x46072c LDR	D7, [X17, #3400]

(945) 0x460730 B	45fdac

(945) 0x460734 LDR	X28, [SP, #384]

(945) 0x460738 CBNZ	X28, 460148

(945) 0x46073c LDR	X13, [SP, #200]

(945) 0x460740 ADD	X5, X5, #8

(945) 0x460744 ADD	X6, X6, #40

(945) 0x460748 LDR	X15, [SP, #368]

(945) 0x46074c ADD	X14, X13, #24

(945) 0x460750 STR	X14, [SP, #200]

(945) 0x460754 CMP	X15, X5

(945) 0x460758 B.NE	45fb24

0x46075c B	4602e8

Coverage (%)	Name	Source Location	Module
►41.46+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►41.21+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►7.90+	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:144	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main._omp_fn.0	miniqmc.cpp:397	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►7.87+	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:144	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main._omp_fn.0	miniqmc.cpp:397	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run gcc_1

Source file and lines	einspline_spo_ref.hpp:203-230
Module	exec

The function is defined in:

/usr/include/c++/14/bits/stl_algobase.h:238,951-952
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53-66
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:203-211,219-230
/usr/include/c++/14/bits/stl_vector.h:1131,1263
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,265,271
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:187-192,199-215,226-262,269-286
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:168-174
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:68-79

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.50 to 11.00 cycles (2.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 41% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 23.50 to 10.88 cycles (2.16x speedup).

Details

24% of VPU instructions are used in vector version (process two or more data elements in vector registers):

32% of VPU loads are used in vector version.
19% of VPU stores are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
25% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249

Matching between your function (in the source code) and the binary function

The binary function is composed of 23 FP arithmetical operations:

14: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 82 bytes. The binary function is storing 67 bytes.

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	146
nb uops	146
loop length	584
used w registers	14
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	30
used q registers	0
used v registers	0
used z registers	5
nb stack references	44
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.25 cycles
front end	18.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	12.00	12.00	12.00	12.00	11.00	11.00	6.00	6.00	23.50	23.17	23.33	9.50	9.50
cycles	4.00	4.00	12.00	12.00	12.00	12.00	11.00	11.00	6.00	6.00	23.50	23.17	23.33	9.50	9.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.25
Dispatch	23.50
Overall L1	23.50

Vectorization ratios

INT

all	21%
load	32%
store	19%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	44%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	100%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

INT+FP

all	24%
load	32%
store	19%
mul	0%
add-sub	50%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Vector efficiency ratios

INT

all	38%
load	38%
store	39%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	58%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	100%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	89%

INT+FP

all	41%
load	38%
store	39%
mul	25%
add-sub	62%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles. At this rate:

3% of peak load performance is reached (3.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.85 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 45f960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W19, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X23, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X25, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X24, [X0, #856]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4cf800 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W0, [X25, #292]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X25, #296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W19, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 45f9c0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X25, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SMADDL X4, W19, W1, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP D28, D27, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVZ W5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, SP, #624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P4.D, WZR, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
MOVZ X3, #48304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP D26, D6, [X20, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
DUP Z30.D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
CNTD X6, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
WHILELO P5.D, W6, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LDP D4, D2, [X20, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D5, D3, [X20, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMUL D0, D27, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR D24, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D1, D27, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMUL D7, D27, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR D22, [X20, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP D23, D25, [X20, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMADD D18, D28, D5, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D16, D28, D3, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D17, D28, D26, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D19, D24, D23, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D20, D24, D25, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D21, D24, D22, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D19, [SP, #624]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STR D20, [SP, #632]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STR D21, [SP, #640]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LD1D {Z29.D}, P4/Z, [X18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FCMLT P6.D, P7/Z, Z29.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z31, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
FRINTM Z31.D, P7/M, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	vect (100.0%)
FCMGT P0.D, P6/Z, Z29.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P1.B, P7/Z, P0.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
MOVPRFX Z31.D, P1/Z, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FSUBR Z31.D, P1/M, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z31.D}, P4, [X18, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B.EQ 45fa78 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z28.D}, P5/Z, [X18, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FCMLT P6.D, P7/Z, Z28.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z27, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
FRINTM Z27.D, P7/M, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	vect (100.0%)
FCMGT P15.D, P6/Z, Z28.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P2.B, P7/Z, P15.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
MOVPRFX Z27.D, P2/Z, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FSUBR Z27.D, P2/M, Z27.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z27.D}, P5, [X18, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X8, SP, #512	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, SP, #512	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W12, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDP X10, X11, [X8, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X10, X11, [X9, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D30, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D24, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR X11, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR D5, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D30, [SP, #344]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STR D24, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STR D5, [SP, #360]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 460304 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x9a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X13, XZR, #0x55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
ORR X14, XZR, #0x55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK X13, #16325	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
MOVK X14, #16357	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
MOVZ X6, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D1, X13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR W16, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR X21, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X20, #760]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X5, W12,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STP X24, X20, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SBFM X2, X16, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
STP X23, X22, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SBFM X22, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
LDR X17, [X20, #784]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X20, #808]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X15, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X20, #832]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X17, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W16, [SP, #380]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X21, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X22, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X20, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X24, X20, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X22, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR X21, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4cfaa0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W24, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 460530 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xbd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W27, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MOVZ W18, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W19, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
UMULL X18, W24, W18	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
MOVZ X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X28, X24, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X2, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W4, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD SP, SP, #656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4602e8 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x988>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run gcc_1

Source file and lines	einspline_spo_ref.hpp:203-230
Module	exec

The function is defined in:

/usr/include/c++/14/bits/stl_algobase.h:238,951-952
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53-66
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:203-211,219-230
/usr/include/c++/14/bits/stl_vector.h:1131,1263
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,265,271
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:187-192,199-215,226-262,269-286
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:168-174
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:68-79

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

24% of VPU instructions are used in vector version (process two or more data elements in vector registers):

32% of VPU loads are used in vector version.
19% of VPU stores are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
25% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249

Matching between your function (in the source code) and the binary function

The binary function is composed of 23 FP arithmetical operations:

14: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 82 bytes. The binary function is storing 67 bytes.

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	146
nb uops	146
loop length	584
used w registers	14
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	30
used q registers	0
used v registers	0
used z registers	5
nb stack references	44
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.25 cycles
front end	18.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	12.00	12.00	12.00	12.00	11.00	11.00	6.00	6.00	23.50	23.17	23.33	9.50	9.50
cycles	4.00	4.00	12.00	12.00	12.00	12.00	11.00	11.00	6.00	6.00	23.50	23.17	23.33	9.50	9.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.25
Dispatch	23.50
Overall L1	23.50

Vectorization ratios

INT

all	21%
load	32%
store	19%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	44%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	100%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

INT+FP

all	24%
load	32%
store	19%
mul	0%
add-sub	50%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Vector efficiency ratios

INT

all	38%
load	38%
store	39%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	58%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	100%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	89%

INT+FP

all	41%
load	38%
store	39%
mul	25%
add-sub	62%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles. At this rate:

3% of peak load performance is reached (3.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.85 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 45f960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W19, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X23, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X25, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X24, [X0, #856]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4cf800 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W0, [X25, #292]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X25, #296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W19, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 45f9c0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X25, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SMADDL X4, W19, W1, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP D28, D27, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVZ W5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, SP, #624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P4.D, WZR, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
MOVZ X3, #48304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP D26, D6, [X20, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
DUP Z30.D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
CNTD X6, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
WHILELO P5.D, W6, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LDP D4, D2, [X20, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D5, D3, [X20, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMUL D0, D27, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR D24, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D1, D27, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMUL D7, D27, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR D22, [X20, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP D23, D25, [X20, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMADD D18, D28, D5, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D16, D28, D3, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D17, D28, D26, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D19, D24, D23, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D20, D24, D25, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D21, D24, D22, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D19, [SP, #624]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STR D20, [SP, #632]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STR D21, [SP, #640]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LD1D {Z29.D}, P4/Z, [X18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FCMLT P6.D, P7/Z, Z29.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z31, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
FRINTM Z31.D, P7/M, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	vect (100.0%)
FCMGT P0.D, P6/Z, Z29.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P1.B, P7/Z, P0.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
MOVPRFX Z31.D, P1/Z, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FSUBR Z31.D, P1/M, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z31.D}, P4, [X18, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B.EQ 45fa78 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z28.D}, P5/Z, [X18, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FCMLT P6.D, P7/Z, Z28.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z27, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
FRINTM Z27.D, P7/M, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	vect (100.0%)
FCMGT P15.D, P6/Z, Z28.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P2.B, P7/Z, P15.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
MOVPRFX Z27.D, P2/Z, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FSUBR Z27.D, P2/M, Z27.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z27.D}, P5, [X18, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X8, SP, #512	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, SP, #512	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W12, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDP X10, X11, [X8, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X10, X11, [X9, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D30, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D24, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR X11, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR D5, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D30, [SP, #344]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STR D24, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STR D5, [SP, #360]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 460304 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x9a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X13, XZR, #0x55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
ORR X14, XZR, #0x55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK X13, #16325	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
MOVK X14, #16357	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
MOVZ X6, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D1, X13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR W16, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR X21, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X20, #760]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X5, W12,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STP X24, X20, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SBFM X2, X16, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
STP X23, X22, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SBFM X22, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
LDR X17, [X20, #784]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X20, #808]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X15, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X20, #832]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X17, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W16, [SP, #380]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X21, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X22, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X20, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X24, X20, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X22, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR X21, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4cfaa0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W24, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 460530 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xbd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W27, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MOVZ W18, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W19, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
UMULL X18, W24, W18	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
MOVZ X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X28, X24, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X2, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W4, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD SP, SP, #656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4602e8 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x988>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator >...–	10.43	15.99
▼Loop 945 - einspline_spo_ref.hpp:206-230 - exec–	0.00	0.02
○Loop 944 - MultiBsplineRef.hpp:276-286 - exec	0.41	0.62
▼Loop 948 - MultiBsplineRef.hpp:226-262 - exec–	0.00	0.02
▼Loop 947 - MultiBsplineRef.hpp:227-262 - exec–	0.00	0.00
○Loop 946 - MultiBsplineRef.hpp:242-262 - exec	9.86	14.96
▼Loop 942 - einspline_spo_ref.hpp:219-227 - exec–	0.00	0.02
○Loop 943 - einspline_spo_ref.hpp:223-227 - exec	0.13	0.20

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