OV - exec - Loop 2531

	Loop Id: 2531	Module: exec	Source: ParticleBConds3DSoa.h:237-255	Coverage: 0.06%

0x4ffd10 LD1D	{Z27.D}, P6/Z, [X11, X2,LSL #3]    [3]

0x4ffd14 LD1D	{Z28.D}, P6/Z, [X9, X2,LSL #3]    [1]

0x4ffd18 LD1D	{Z26.D}, P6/Z, [X0, X2,LSL #3]    [4]

0x4ffd1c LD1RD	{Z1.D}, P7/Z, [X19, #13]    [8]

0x4ffd20 LD1RD	{Z2.D}, P7/Z, [X19, #12]    [8]

0x4ffd24 LD1RD	{Z24.D}, P7/Z, [X19, #10]    [8]

0x4ffd28 LD1RD	{Z25.D}, P7/Z, [X19, #9]    [8]

0x4ffd2c LD1RD	{Z17.D}, P7/Z, [X19, #16]    [8]

0x4ffd30 LD1RD	{Z18.D}, P7/Z, [X19, #15]    [8]

0x4ffd34 FSUB	Z3.D, Z27.D, Z30.D

0x4ffd38 FSUB	Z5.D, Z28.D, Z31.D

0x4ffd3c FSUB	Z6.D, Z26.D, Z29.D

0x4ffd40 LD1RD	{Z0.D}, P7/Z, [X19, #14]    [8]

0x4ffd44 LD1RD	{Z23.D}, P7/Z, [X19, #11]    [8]

0x4ffd48 LD1RD	{Z16.D}, P7/Z, [X19, #17]    [8]

0x4ffd4c FMUL	Z4.D, Z1.D, Z3.D

0x4ffd50 FMUL	Z7.D, Z24.D, Z3.D

0x4ffd54 FMLA	Z4.D, P7/M, Z2.D, Z5.D

0x4ffd58 FMLA	Z7.D, P7/M, Z25.D, Z5.D

0x4ffd5c FMAD	Z0.D, P7/M, Z6.D, Z4.D

0x4ffd60 FMAD	Z23.D, P7/M, Z6.D, Z7.D

0x4ffd64 FMUL	Z19.D, Z17.D, Z3.D

0x4ffd68 FMLA	Z19.D, P7/M, Z18.D, Z5.D

0x4ffd6c FMAD	Z16.D, P7/M, Z6.D, Z19.D

0x4ffd70 LD1RD	{Z20.D}, P7/Z, [X19, #1]    [8]

0x4ffd74 LD1RD	{Z3.D}, P7/Z, [X19]    [8]

0x4ffd78 LD1RD	{Z5.D}, P7/Z, [X19, #2]    [8]

0x4ffd7c ADD	X30, X16, X2,LSL #3

0x4ffd80 MOVPRFX	Z21, Z0

0x4ffd84 FRINTA	Z21.D, P7/M, Z0.D

0x4ffd88 MOVPRFX	Z22, Z23

0x4ffd8c FRINTA	Z22.D, P7/M, Z23.D

0x4ffd90 FSUB	Z27.D, Z0.D, Z21.D

0x4ffd94 FSUB	Z28.D, Z23.D, Z22.D

0x4ffd98 ADD	X1, X12, X2,LSL #3

0x4ffd9c MOVPRFX	Z4, Z16

0x4ffda0 FRINTA	Z4.D, P7/M, Z16.D

0x4ffda4 FMUL	Z1.D, Z20.D, Z27.D

0x4ffda8 FSUB	Z26.D, Z16.D, Z4.D

0x4ffdac FMLA	Z1.D, P7/M, Z3.D, Z28.D

0x4ffdb0 FMAD	Z5.D, P7/M, Z26.D, Z1.D

0x4ffdb4 ST1D	{Z5.D}, P6, [X30, MUL VL]    [2]

0x4ffdb8 LD1RD	{Z6.D}, P7/Z, [X19, #3]    [8]

0x4ffdbc LD1RD	{Z0.D}, P7/Z, [X19, #4]    [8]

0x4ffdc0 LD1RD	{Z2.D}, P7/Z, [X19, #5]    [8]

0x4ffdc4 FMUL	Z24.D, Z0.D, Z27.D

0x4ffdc8 FMLA	Z24.D, P7/M, Z6.D, Z28.D

0x4ffdcc FMAD	Z2.D, P7/M, Z26.D, Z24.D

0x4ffdd0 ST1D	{Z2.D}, P6, [X1, MUL VL]    [5]

0x4ffdd4 LD1RD	{Z7.D}, P7/Z, [X19, #7]    [8]

0x4ffdd8 LD1RD	{Z25.D}, P7/Z, [X19, #6]    [8]

0x4ffddc LD1RD	{Z17.D}, P7/Z, [X19, #8]    [8]

0x4ffde0 FMUL	Z23.D, Z7.D, Z27.D

0x4ffde4 FMLA	Z23.D, P7/M, Z25.D, Z28.D

0x4ffde8 FMAD	Z17.D, P7/M, Z26.D, Z23.D

0x4ffdec ST1D	{Z17.D}, P6, [X17, X2,LSL #3]    [6]

0x4ffdf0 LD1D	{Z18.D}, P6/Z, [X1, MUL VL]    [5]

0x4ffdf4 LD1D	{Z19.D}, P6/Z, [X30, MUL VL]    [2]

0x4ffdf8 FMUL	Z16.D, Z18.D, Z18.D

0x4ffdfc FMLA	Z16.D, P7/M, Z19.D, Z19.D

0x4ffe00 FMLA	Z16.D, P7/M, Z17.D, Z17.D

0x4ffe04 FSQRT	Z16.D, P7/M, Z16.D

0x4ffe08 ST1D	{Z16.D}, P6, [X18, X2,LSL #3]    [7]

0x4ffe0c ADD	X2, X2, X21

0x4ffe10 WHILELO	P6.D, W2, W7

0x4ffe14 B.NE	4ffd10

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 237 - 255

--------------------------------------------------------------------------------

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

Coverage (%)	Name	Source Location	Module
►98.99+	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:993	exec
○	main._omp_fn.0	miniqmc.cpp:397	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.01+	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:993	exec
○	main._omp_fn.0	miniqmc.cpp:397	exec
○	GOMP_parallel		libgomp.so.1.0.0
○	main	stl_vector.h:1128	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	miniqmc.cpp:529	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	qmcplusplus::SoaDistanceTableAAOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source	ParticleBConds3DSoa.h:237-255
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	17.00
Front-end cycles	8.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	17.00
P7 cycles	17.00
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	13.50
P11 cycles	13.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	6.99 - 14.08
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	66.00
Nb uops	66.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	9.88
Nb FLOP add-sub	24.00
Nb FLOP mul	28.00
Nb FLOP fma	56.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.94
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	7.00
Stride indirect	0.00
Vectorization ratio all	65.57
Vectorization ratio load	21.74
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	77.87
Vector-efficiency ratio load	41.30
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	qmcplusplus::SoaDistanceTableAAOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source	ParticleBConds3DSoa.h:237-255
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	17.00
Front-end cycles	8.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	17.00
P7 cycles	17.00
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	13.50
P11 cycles	13.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	6.99 - 14.08
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	66.00
Nb uops	66.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	9.88
Nb FLOP add-sub	24.00
Nb FLOP mul	28.00
Nb FLOP fma	56.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.94
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	7.00
Stride indirect	0.00
Vectorization ratio all	65.57
Vectorization ratio load	21.74
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	77.87
Vector-efficiency ratio load	41.30
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::SoaDistanceTableAAOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source file and lines	ParticleBConds3DSoa.h:237-255
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237-255.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 77% of vector register length is used (average across all VPU instructions).

Details

65% of VPU instructions are used in vector version (process two or more data elements in vector registers):

21% of VPU loads are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 56 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 168 FP arithmetical operations:

80: addition or subtraction (56 inside FMA instructions)
84: multiply (56 inside FMA instructions)
4: square root

The binary loop is loading 160 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.58 FP operations per loaded or stored byte.

General properties

nb instructions	66
nb uops	66
loop length	264
used w registers	2
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	24
nb stack references	0
ADD-SUB / MUL ratio	0.86

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.25 cycles
front end	8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	1.00	1.00	17.00	17.00	2.00	2.00	13.50	13.50	0.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	1.00	1.00	17.00	17.00	13.50	13.50	13.50	13.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.25
Dispatch	17.00
DIV/SQRT	6.99-14.08
Data deps.	1.00
Overall L1	17.00

Vectorization ratios

INT

all	30%
load	21%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	65%
load	21%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

Vector efficiency ratios

INT

all	55%
load	41%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	77%
load	41%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

9% of peak load performance is reached (9.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4ffd10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z27.D}, P6/Z, [X11, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z28.D}, P6/Z, [X9, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z26.D}, P6/Z, [X0, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1RD {Z1.D}, P7/Z, [X19, #13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z2.D}, P7/Z, [X19, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z24.D}, P7/Z, [X19, #10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z25.D}, P7/Z, [X19, #9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z17.D}, P7/Z, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z18.D}, P7/Z, [X19, #15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
FSUB Z3.D, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z5.D, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z6.D, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z0.D}, P7/Z, [X19, #14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z23.D}, P7/Z, [X19, #11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z16.D}, P7/Z, [X19, #17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
FMUL Z4.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z7.D, Z24.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z4.D, P7/M, Z2.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z7.D, P7/M, Z25.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z0.D, P7/M, Z6.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z23.D, P7/M, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z19.D, Z17.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z19.D, P7/M, Z18.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z16.D, P7/M, Z6.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1RD {Z20.D}, P7/Z, [X19, #1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z3.D}, P7/Z, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z5.D}, P7/Z, [X19, #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
ADD X30, X16, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVPRFX Z21, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FRINTA Z21.D, P7/M, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
MOVPRFX Z22, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FRINTA Z22.D, P7/M, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FSUB Z27.D, Z0.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z28.D, Z23.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADD X1, X12, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVPRFX Z4, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FRINTA Z4.D, P7/M, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FMUL Z1.D, Z20.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z26.D, Z16.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z1.D, P7/M, Z3.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z5.D, P7/M, Z26.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z5.D}, P6, [X30, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1RD {Z6.D}, P7/Z, [X19, #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z0.D}, P7/Z, [X19, #4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z2.D}, P7/Z, [X19, #5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
FMUL Z24.D, Z0.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z24.D, P7/M, Z6.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z2.D, P7/M, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z2.D}, P6, [X1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1RD {Z7.D}, P7/Z, [X19, #7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z25.D}, P7/Z, [X19, #6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z17.D}, P7/Z, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
FMUL Z23.D, Z7.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z23.D, P7/M, Z25.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z17.D, P7/M, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z17.D}, P6, [X17, X2,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z18.D}, P6/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P6/Z, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z16.D, Z18.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z16.D, P7/M, Z19.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z16.D, P7/M, Z17.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FSQRT Z16.D, P7/M, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
ST1D {Z16.D}, P6, [X18, X2,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X2, X2, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P6.D, W2, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.NE 4ffd10 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	qmcplusplus::SoaDistanceTableAAOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source file and lines	ParticleBConds3DSoa.h:237-255
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 77% of vector register length is used (average across all VPU instructions).

Details

65% of VPU instructions are used in vector version (process two or more data elements in vector registers):

21% of VPU loads are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 56 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 168 FP arithmetical operations:

80: addition or subtraction (56 inside FMA instructions)
84: multiply (56 inside FMA instructions)
4: square root

The binary loop is loading 160 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.58 FP operations per loaded or stored byte.

General properties

nb instructions	66
nb uops	66
loop length	264
used w registers	2
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	24
nb stack references	0
ADD-SUB / MUL ratio	0.86

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.25 cycles
front end	8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	1.00	1.00	17.00	17.00	2.00	2.00	13.50	13.50	0.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	1.00	1.00	17.00	17.00	13.50	13.50	13.50	13.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.25
Dispatch	17.00
DIV/SQRT	6.99-14.08
Data deps.	1.00
Overall L1	17.00

Vectorization ratios

INT

all	30%
load	21%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	65%
load	21%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

Vector efficiency ratios

INT

all	55%
load	41%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	77%
load	41%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

9% of peak load performance is reached (9.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4ffd10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z27.D}, P6/Z, [X11, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z28.D}, P6/Z, [X9, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z26.D}, P6/Z, [X0, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1RD {Z1.D}, P7/Z, [X19, #13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z2.D}, P7/Z, [X19, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z24.D}, P7/Z, [X19, #10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z25.D}, P7/Z, [X19, #9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z17.D}, P7/Z, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z18.D}, P7/Z, [X19, #15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
FSUB Z3.D, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z5.D, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z6.D, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z0.D}, P7/Z, [X19, #14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z23.D}, P7/Z, [X19, #11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z16.D}, P7/Z, [X19, #17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
FMUL Z4.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z7.D, Z24.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z4.D, P7/M, Z2.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z7.D, P7/M, Z25.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z0.D, P7/M, Z6.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z23.D, P7/M, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z19.D, Z17.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z19.D, P7/M, Z18.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z16.D, P7/M, Z6.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1RD {Z20.D}, P7/Z, [X19, #1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z3.D}, P7/Z, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z5.D}, P7/Z, [X19, #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
ADD X30, X16, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVPRFX Z21, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FRINTA Z21.D, P7/M, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
MOVPRFX Z22, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FRINTA Z22.D, P7/M, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FSUB Z27.D, Z0.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z28.D, Z23.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADD X1, X12, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVPRFX Z4, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FRINTA Z4.D, P7/M, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FMUL Z1.D, Z20.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z26.D, Z16.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z1.D, P7/M, Z3.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z5.D, P7/M, Z26.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z5.D}, P6, [X30, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1RD {Z6.D}, P7/Z, [X19, #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z0.D}, P7/Z, [X19, #4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z2.D}, P7/Z, [X19, #5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
FMUL Z24.D, Z0.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z24.D, P7/M, Z6.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z2.D, P7/M, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z2.D}, P6, [X1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1RD {Z7.D}, P7/Z, [X19, #7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z25.D}, P7/Z, [X19, #6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1RD {Z17.D}, P7/Z, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
FMUL Z23.D, Z7.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z23.D, P7/M, Z25.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z17.D, P7/M, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z17.D}, P6, [X17, X2,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z18.D}, P6/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P6/Z, [X30, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z16.D, Z18.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z16.D, P7/M, Z19.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z16.D, P7/M, Z17.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FSQRT Z16.D, P7/M, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
ST1D {Z16.D}, P6, [X18, X2,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X2, X2, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P6.D, W2, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.NE 4ffd10 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code