OV - exec - Loop 296

	Loop Id: 296	Module: exec	Source: BsplineFunctor.h:246-260 [...]	Coverage: 0.03%

0x42c248 LD1D	{Z29.D}, P5/Z, [X6, X3,LSL #3]    [2]

0x42c24c LD1D	{Z30.D}, P6/Z, [X4, X3,LSL #3]    [1]

0x42c250 FMUL	Z31.D, Z3.D, Z29.D

0x42c254 FMUL	Z13.D, Z3.D, Z30.D

0x42c258 MOVPRFX	Z8, Z31

0x42c25c FCVTZS	Z8.S, P7/M, Z31.D

0x42c260 MOVPRFX	Z9, Z13

0x42c264 FCVTZS	Z9.S, P7/M, Z13.D

0x42c268 MOVPRFX	Z0, Z31

0x42c26c FRINTZ	Z0.D, P7/M, Z31.D

0x42c270 UZP1	Z30.S, Z9.S, Z8.S

0x42c274 FSUB	Z31.D, Z31.D, Z0.D

0x42c278 MOVPRFX	Z12, Z30

0x42c27c ADD	Z12.S, Z12.S, #1

0x42c280 FMUL	Z29.D, Z31.D, Z31.D

0x42c284 SUNPKHI	Z8.D, Z12

0x42c288 FMUL	Z14.D, Z29.D, Z31.D

0x42c28c LD1D	{Z9.D}, P5/Z, [X16, Z8.D,LSL #3]    [3]

0x42c290 FMUL	Z10.D, Z17.D, Z29.D

0x42c294 FMLA	Z10.D, P7/M, Z16.D, Z14.D

0x42c298 MOVPRFX	Z11, Z19

0x42c29c FMLA	Z11.D, P7/M, Z18.D, Z31.D

0x42c2a0 FADD	Z0.D, Z10.D, Z11.D

0x42c2a4 FMUL	Z10.D, Z5.D, Z29.D

0x42c2a8 FMUL	Z0.D, Z0.D, Z9.D

0x42c2ac FMLA	Z10.D, P7/M, Z4.D, Z14.D

0x42c2b0 SUNPKHI	Z9.D, Z30

0x42c2b4 LD1D	{Z8.D}, P5/Z, [X16, Z9.D,LSL #3]    [3]

0x42c2b8 MOVPRFX	Z11, Z7

0x42c2bc FMLA	Z11.D, P7/M, Z6.D, Z31.D

0x42c2c0 FADD	Z11.D, Z11.D, Z10.D

0x42c2c4 FMUL	Z10.D, Z21.D, Z29.D

0x42c2c8 FMAD	Z11.D, P7/M, Z8.D, Z0.D

0x42c2cc FMLA	Z10.D, P7/M, Z14.D, Z20.D

0x42c2d0 MOVPRFX	Z0, Z23

0x42c2d4 FMLA	Z0.D, P7/M, Z31.D, Z22.D

0x42c2d8 FMUL	Z29.D, Z29.D, Z25.D

0x42c2dc FADD	Z8.D, Z10.D, Z0.D

0x42c2e0 FMAD	Z14.D, P7/M, Z24.D, Z29.D

0x42c2e4 MOVPRFX	Z10, Z30

0x42c2e8 ADD	Z10.S, Z10.S, #2

0x42c2ec FADD	Z1.D, P5/M, Z1.D, Z11.D

0x42c2f0 FMAD	Z31.D, P7/M, Z26.D, Z27.D

0x42c2f4 MOVPRFX	Z11, Z30

0x42c2f8 ADD	Z11.S, Z11.S, #3

0x42c2fc FADD	Z31.D, Z31.D, Z14.D

0x42c300 SUNPKHI	Z0.D, Z11

0x42c304 SUNPKHI	Z14.D, Z10

0x42c308 LD1D	{Z29.D}, P5/Z, [X16, Z0.D,LSL #3]    [3]

0x42c30c LD1D	{Z9.D}, P5/Z, [X16, Z14.D,LSL #3]    [3]

0x42c310 SUNPKLO	Z30.D, Z30

0x42c314 FMLA	Z1.D, P5/M, Z9.D, Z8.D

0x42c318 SUNPKLO	Z8.D, Z10

0x42c31c FMLA	Z1.D, P5/M, Z29.D, Z31.D

0x42c320 LD1D	{Z14.D}, P6/Z, [X16, Z8.D,LSL #3]    [3]

0x42c324 SUNPKLO	Z31.D, Z11

0x42c328 MOVPRFX	Z9, Z13

0x42c32c FRINTZ	Z9.D, P7/M, Z13.D

0x42c330 LD1D	{Z11.D}, P6/Z, [X16, Z30.D,LSL #3]    [3]

0x42c334 FSUB	Z8.D, Z13.D, Z9.D

0x42c338 SUNPKLO	Z12.D, Z12

0x42c33c FMUL	Z29.D, Z8.D, Z8.D

0x42c340 FMUL	Z30.D, Z29.D, Z8.D

0x42c344 FMUL	Z13.D, Z17.D, Z29.D

0x42c348 FMLA	Z13.D, P7/M, Z16.D, Z30.D

0x42c34c LD1D	{Z10.D}, P6/Z, [X16, Z12.D,LSL #3]    [3]

0x42c350 ADD	X3, X3, X7

0x42c354 MOVPRFX	Z12, Z19

0x42c358 FMLA	Z12.D, P7/M, Z18.D, Z8.D

0x42c35c WHILELO	P5.D, W3, W15

0x42c360 FADD	Z9.D, Z12.D, Z13.D

0x42c364 MOVPRFX	Z13, Z7

0x42c368 FMLA	Z13.D, P7/M, Z6.D, Z8.D

0x42c36c LD1D	{Z0.D}, P6/Z, [X16, Z31.D,LSL #3]    [3]

0x42c370 FMUL	Z12.D, Z9.D, Z10.D

0x42c374 FMUL	Z31.D, Z5.D, Z29.D

0x42c378 FMUL	Z10.D, Z21.D, Z29.D

0x42c37c FMLA	Z31.D, P7/M, Z4.D, Z30.D

0x42c380 MOVPRFX	Z9, Z23

0x42c384 FMLA	Z9.D, P7/M, Z8.D, Z22.D

0x42c388 FADD	Z31.D, Z13.D, Z31.D

0x42c38c FMUL	Z29.D, Z29.D, Z25.D

0x42c390 FMAD	Z31.D, P7/M, Z11.D, Z12.D

0x42c394 FMAD	Z8.D, P7/M, Z26.D, Z27.D

0x42c398 MOVPRFX	Z11, Z10

0x42c39c FMLA	Z11.D, P7/M, Z30.D, Z20.D

0x42c3a0 FADD	Z28.D, P6/M, Z28.D, Z31.D

0x42c3a4 FMAD	Z30.D, P7/M, Z24.D, Z29.D

0x42c3a8 FADD	Z13.D, Z9.D, Z11.D

0x42c3ac FMLA	Z28.D, P6/M, Z14.D, Z13.D

0x42c3b0 FADD	Z14.D, Z30.D, Z8.D

0x42c3b4 FMLA	Z28.D, P6/M, Z0.D, Z14.D

0x42c3b8 WHILELO	P6.D, W3, W2

0x42c3bc B.NE	42c248

/usr/include/c++/14/bits/stl_vector.h: 1147 - 1147

--------------------------------------------------------------------------------

1147:       operator[](size_type __n) const _GLIBCXX_NOEXCEPT

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 246 - 260

--------------------------------------------------------------------------------

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

Coverage (%)	Name	Source Location	Module
►98.35+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:993	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	stl_vector.h:1147-1147,BsplineFunctor.h:246-260
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	40.00
CQA cycles if no scalar integer	40.00
CQA cycles if FP arith vectorized	40.00
CQA cycles if fully vectorized	40.00
Front-end cycles	11.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	2.00
P5 cycles	0.25
P6 cycles	40.00
P7 cycles	40.00
P8 cycles	25.00
P9 cycles	25.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	94.00
Nb uops	94.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	7.20
Nb FLOP add-sub	48.00
Nb FLOP mul	64.00
Nb FLOP fma	88.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.00
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	1.00
Vectorization ratio all	75.56
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	18.52
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	stl_vector.h:1147-1147,BsplineFunctor.h:246-260
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	40.00
CQA cycles if no scalar integer	40.00
CQA cycles if FP arith vectorized	40.00
CQA cycles if fully vectorized	40.00
Front-end cycles	11.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	2.00
P5 cycles	0.25
P6 cycles	40.00
P7 cycles	40.00
P8 cycles	25.00
P9 cycles	25.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	94.00
Nb uops	94.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	7.20
Nb FLOP add-sub	48.00
Nb FLOP mul	64.00
Nb FLOP fma	88.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.00
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	1.00
Vectorization ratio all	75.56
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	18.52
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	BsplineFunctor.h:246-260
Module	exec

The loop is defined in:

/usr/include/c++/14/bits/stl_vector.h:1147
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:246-260

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

18% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 88 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 288 FP arithmetical operations:

136: addition or subtraction (88 inside FMA instructions)
152: multiply (88 inside FMA instructions)

The binary loop is loading 320 bytes.

Arithmetic intensity

Arithmetic intensity is 0.90 FP operations per loaded or stored byte.

General properties

nb instructions	94
nb uops	94
loop length	376
used w registers	3
used x registers	5
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	30
nb stack references	0
ADD-SUB / MUL ratio	0.75

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.75 cycles
front end	11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	2.00	0.25	40.00	40.00	0.00	0.00	5.00	5.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	2.00	0.25	40.00	40.00	25.00	25.00	5.00	5.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	11.75
Dispatch	40.00
Data deps.	8.00
Overall L1	40.00

Vectorization ratios

INT

all	38%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	75%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Vector efficiency ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42c248

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z29.D}, P5/Z, [X6, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z30.D}, P6/Z, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z31.D, Z3.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z13.D, Z3.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
MOVPRFX Z8, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FCVTZS Z8.S, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
MOVPRFX Z9, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FCVTZS Z9.S, P7/M, Z13.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
MOVPRFX Z0, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FRINTZ Z0.D, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
UZP1 Z30.S, Z9.S, Z8.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FSUB Z31.D, Z31.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOVPRFX Z12, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
ADD Z12.S, Z12.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMUL Z29.D, Z31.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
SUNPKHI Z8.D, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z14.D, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z9.D}, P5/Z, [X16, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z10.D, Z17.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z10.D, P7/M, Z16.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z11, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z11.D, P7/M, Z18.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z0.D, Z10.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMUL Z10.D, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z0.D, Z0.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z10.D, P7/M, Z4.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
SUNPKHI Z9.D, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
LD1D {Z8.D}, P5/Z, [X16, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z11, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z11.D, P7/M, Z6.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z11.D, Z11.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMUL Z10.D, Z21.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMAD Z11.D, P7/M, Z8.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z10.D, P7/M, Z14.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z0, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z0.D, P7/M, Z31.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMUL Z29.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z8.D, Z10.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMAD Z14.D, P7/M, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z10, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
ADD Z10.S, Z10.S, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADD Z1.D, P5/M, Z1.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMAD Z31.D, P7/M, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z11, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
ADD Z11.S, Z11.S, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADD Z31.D, Z31.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
SUNPKHI Z0.D, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
SUNPKHI Z14.D, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
LD1D {Z29.D}, P5/Z, [X16, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z9.D}, P5/Z, [X16, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUNPKLO Z30.D, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z1.D, P5/M, Z9.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
SUNPKLO Z8.D, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z1.D, P5/M, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z14.D}, P6/Z, [X16, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUNPKLO Z31.D, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
MOVPRFX Z9, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FRINTZ Z9.D, P7/M, Z13.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
LD1D {Z11.D}, P6/Z, [X16, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z8.D, Z13.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
SUNPKLO Z12.D, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z29.D, Z8.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z30.D, Z29.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z13.D, Z17.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z13.D, P7/M, Z16.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z10.D}, P6/Z, [X16, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X3, X3, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVPRFX Z12, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z12.D, P7/M, Z18.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
WHILELO P5.D, W3, W15	1	0	0	0	0	1	0	0	0	0	0	3	2	N/A
FADD Z9.D, Z12.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOVPRFX Z13, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z13.D, P7/M, Z6.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z0.D}, P6/Z, [X16, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z12.D, Z9.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z31.D, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z10.D, Z21.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z31.D, P7/M, Z4.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z9, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z9.D, P7/M, Z8.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z31.D, Z13.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMUL Z29.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMAD Z31.D, P7/M, Z11.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMAD Z8.D, P7/M, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z11, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z11.D, P7/M, Z30.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z28.D, P6/M, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMAD Z30.D, P7/M, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z13.D, Z9.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z28.D, P6/M, Z14.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z14.D, Z30.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z28.D, P6/M, Z0.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
WHILELO P6.D, W3, W2	1	0	0	0	0	1	0	0	0	0	0	3	2	N/A
B.NE 42c248 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	BsplineFunctor.h:246-260
Module	exec

The loop is defined in:

/usr/include/c++/14/bits/stl_vector.h:1147
/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:246-260

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

18% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 88 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 288 FP arithmetical operations:

136: addition or subtraction (88 inside FMA instructions)
152: multiply (88 inside FMA instructions)

The binary loop is loading 320 bytes.

Arithmetic intensity

Arithmetic intensity is 0.90 FP operations per loaded or stored byte.

General properties

nb instructions	94
nb uops	94
loop length	376
used w registers	3
used x registers	5
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	30
nb stack references	0
ADD-SUB / MUL ratio	0.75

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.75 cycles
front end	11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	2.00	0.25	40.00	40.00	0.00	0.00	5.00	5.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	2.00	0.25	40.00	40.00	25.00	25.00	5.00	5.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	11.75
Dispatch	40.00
Data deps.	8.00
Overall L1	40.00

Vectorization ratios

INT

all	38%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	75%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Vector efficiency ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42c248

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z29.D}, P5/Z, [X6, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z30.D}, P6/Z, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z31.D, Z3.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z13.D, Z3.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
MOVPRFX Z8, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FCVTZS Z8.S, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
MOVPRFX Z9, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FCVTZS Z9.S, P7/M, Z13.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
MOVPRFX Z0, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FRINTZ Z0.D, P7/M, Z31.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
UZP1 Z30.S, Z9.S, Z8.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FSUB Z31.D, Z31.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOVPRFX Z12, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
ADD Z12.S, Z12.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMUL Z29.D, Z31.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
SUNPKHI Z8.D, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z14.D, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z9.D}, P5/Z, [X16, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z10.D, Z17.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z10.D, P7/M, Z16.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z11, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z11.D, P7/M, Z18.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z0.D, Z10.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMUL Z10.D, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z0.D, Z0.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z10.D, P7/M, Z4.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
SUNPKHI Z9.D, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
LD1D {Z8.D}, P5/Z, [X16, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z11, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z11.D, P7/M, Z6.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z11.D, Z11.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMUL Z10.D, Z21.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMAD Z11.D, P7/M, Z8.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z10.D, P7/M, Z14.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z0, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z0.D, P7/M, Z31.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMUL Z29.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z8.D, Z10.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMAD Z14.D, P7/M, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z10, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
ADD Z10.S, Z10.S, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADD Z1.D, P5/M, Z1.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMAD Z31.D, P7/M, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z11, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
ADD Z11.S, Z11.S, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADD Z31.D, Z31.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
SUNPKHI Z0.D, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
SUNPKHI Z14.D, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
LD1D {Z29.D}, P5/Z, [X16, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z9.D}, P5/Z, [X16, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUNPKLO Z30.D, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z1.D, P5/M, Z9.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
SUNPKLO Z8.D, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z1.D, P5/M, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z14.D}, P6/Z, [X16, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUNPKLO Z31.D, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
MOVPRFX Z9, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FRINTZ Z9.D, P7/M, Z13.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
LD1D {Z11.D}, P6/Z, [X16, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z8.D, Z13.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
SUNPKLO Z12.D, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z29.D, Z8.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z30.D, Z29.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z13.D, Z17.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z13.D, P7/M, Z16.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z10.D}, P6/Z, [X16, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X3, X3, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVPRFX Z12, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z12.D, P7/M, Z18.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
WHILELO P5.D, W3, W15	1	0	0	0	0	1	0	0	0	0	0	3	2	N/A
FADD Z9.D, Z12.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOVPRFX Z13, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z13.D, P7/M, Z6.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z0.D}, P6/Z, [X16, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z12.D, Z9.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z31.D, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z10.D, Z21.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z31.D, P7/M, Z4.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z9, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z9.D, P7/M, Z8.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z31.D, Z13.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMUL Z29.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMAD Z31.D, P7/M, Z11.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMAD Z8.D, P7/M, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z11, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z11.D, P7/M, Z30.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z28.D, P6/M, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMAD Z30.D, P7/M, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z13.D, Z9.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z28.D, P6/M, Z14.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z14.D, Z30.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z28.D, P6/M, Z0.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
WHILELO P6.D, W3, W2	1	0	0	0	0	1	0	0	0	0	0	3	2	N/A
B.NE 42c248 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code