OV - exec - Function qmcplusplus::BsplineAllocator<double, 32ul, qmcplusplus::Mallocator<double, 32ul> >::setCoefficientsForOrbitals(int, int, Array<double, 3u>&, multi_UBspline_3d_d*) [clone .omp

	Function: qmcplusplus::BsplineAllocator<double, 32ul, qmcplusplus::Mallocator<double, 32ul> >::setCo ...	Module: exec	Source: BsplineAllocator.hpp:171-180	Coverage (incl. loops): 0.10% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/BsplineAllocator.hpp: 171 - 180

--------------------------------------------------------------------------------

171: #pragma omp parallel for collapse(3)

172:   for (int ix = 0; ix < spline->x_grid.num + 3; ix++)

173:     for (int iy = 0; iy < spline->y_grid.num + 3; iy++)

174:       for (int iz = 0; iz < spline->z_grid.num + 3; iz++)

175:       {

176:         intptr_t xs = spline->x_stride;

177:         intptr_t ys = spline->y_stride;

178:         intptr_t zs = spline->z_stride;

179:         for (int ind = first; ind < last; ind++)

180:           spline->coefs[ix * xs + iy * ys + iz * zs + ind] = coeff(ix, iy, iz) * prefactor[ind];

0x439b40 LDR	X10, [X2]

0x439b44 LDR	W8, [X10, #56]

0x439b48 LDR	W9, [X10, #96]

0x439b4c LDR	W10, [X10, #136]

0x439b50 CMN	W8, #2

0x439b54 CCMN	W9, #2, #8, #10

0x439b58 CCMN	W10, #2, #8, #10

0x439b5c B.LT	439f0c

0x439b60 SUB	SP, SP, #208

0x439b64 STP	X29, X30, [SP, #112]

0x439b68 STP	X28, X27, [SP, #128]

0x439b6c STP	X26, X25, [SP, #144]

0x439b70 STP	X24, X23, [SP, #160]

0x439b74 STP	X22, X21, [SP, #176]

0x439b78 STP	X20, X19, [SP, #192]

0x439b7c ADD	X29, SP, #112

0x439b80 ADD	W19, W9, #3

0x439b84 ADD	W8, W8, #3

0x439b88 ADD	W9, W10, #3

0x439b8c LDR	W1, [X0]

0x439b90 ORR	X20, XZR, X4

0x439b94 ORR	X21, XZR, X3

0x439b98 ORR	X25, XZR, X2

0x439b9c ORR	X23, XZR, X6

0x439ba0 UMULL	X8, W19, W8

0x439ba4 SBFM	X22, X9, #0, #31

0x439ba8 MOVN	X9, #0

0x439bac ORR	X24, XZR, X5

0x439bb0 ADRP	X0,

0x439bb4 ADD	X0, X0, #1376

0x439bb8 STUR	WZR, [X29, #484]

0x439bbc SUB	X3, X29, #28

0x439bc0 SUB	X4, X29, #8

0x439bc4 SUB	X5, X29, #16

0x439bc8 SUB	X6, X29, #24

0x439bcc STR	W1, [SP, #20]

0x439bd0 MADD	X26, X8, X22, X9

0x439bd4 MOVZ	W8, #1

0x439bd8 MOVZ	W2, #34

0x439bdc MOVZ	W7, #1

0x439be0 STUR	X8, [X29, #488]

0x439be4 STR	X8, [SP]

0x439be8 STP	X26, XZR, [X29, #1008]

0x439bec BL	410860

0x439bf0 LDP	X8, X9, [X29, #1008]

0x439bf4 CMP	X8, X26

0x439bf8 CSEL	X8, X8, X26, #11

0x439bfc CMP	X9, X8

0x439c00 STUR	X8, [X29, #496]

0x439c04 B.GT	439ee0

0x439c08 LDRSW	X0, [X21]

0x439c0c LDRSW	X11, [X20]

0x439c10 CMP	W0, W11

0x439c14 B.GE	439ee0

0x439c18 LDR	X10, [X25]

0x439c1c CNTW	X14, ALL

0x439c20 MOVZ	W17, #12

0x439c24 SUB	X13, X11, X0

0x439c28 LDP	X4, X15, [X24, #16]

0x439c2c LDR	X16, [X23]

0x439c30 MUL	W12, W22, W19

0x439c34 PTRUE	P0.D, ALL

0x439c38 SUB	W27, WZR, W19

0x439c3c CMP	X14, #12

0x439c40 CSEL	X17, X14, X17, #8

0x439c44 SUB	X18, XZR, X14

0x439c48 STUR	X17, [X29, #472]

0x439c4c AND	X18, X13, X18

0x439c50 LDP	X13, X17, [X10, #24]

0x439c54 LDP	X3, X1, [X10, #8]

0x439c58 LDR	X10, [X24, #8]

0x439c5c ADD	X20, X16, X0,LSL #3

0x439c60 STUR	X10, [X29, #464]

0x439c64 UBFM	X10, X4, #61, #60

0x439c68 STP	X17, X13, [SP, #48]

0x439c6c UBFM	X24, X17, #61, #60

0x439c70 UBFM	X25, X13, #61, #60

0x439c74 UBFM	X26, X1, #61, #60

0x439c78 STP	X10, X1, [SP, #32]

0x439c7c RDVL	X10, #1

0x439c80 ADD	X10, X10, X0,LSL #3

0x439c84 ADD	X13, X3, X10

0x439c88 ADD	X30, X16, X10

0x439c8c STR	X13, [SP, #24]

0x439c90 B	439cac

0x439c94 HINT	#0

0x439c98 HINT	#0

0x439c9c HINT	#0

  (787) 0x439ca0 CMP	X9, X8

  (787) 0x439ca4 ADD	X9, X9, #1

  (787) 0x439ca8 B.EQ	439ee0

  (787) 0x439cac SDIV	X19, X9, X12

  (787) 0x439cb0 SUB	X13, X11, X0

  (787) 0x439cb4 ORR	X7, XZR, X0

  (787) 0x439cb8 SBFM	X21, X19, #0, #31

  (787) 0x439cbc MSUB	X10, X19, X12, X9

  (787) 0x439cc0 SDIV	X23, X10, X22

  (787) 0x439cc4 MSUB	X1, X23, X22, X10

  (787) 0x439cc8 SBFM	X28, X23, #0, #31

  (787) 0x439ccc LDP	X10, X17, [X29, #976]

  (787) 0x439cd0 ADD	X6, X15, W1,SXTW #3

  (787) 0x439cd4 MADD	X10, X10, X21, X28

  (787) 0x439cd8 CMP	X13, X17

  (787) 0x439cdc MUL	X2, X10, X4

  (787) 0x439ce0 ADD	X6, X6, X2,LSL #3

  (787) 0x439ce4 B.CS	439de0

  (787) 0x439ce8 SUB	W10, W11, W7

  (787) 0x439cec ANDS	X1, X10, #0x3

  (787) 0x439cf0 ORR	X10, XZR, X7

  (787) 0x439cf4 B.EQ	439d3c

  (787) 0x439cf8 SUB	W10, WZR, W23

  (787) 0x439cfc MUL	X13, X25, X28

  (787) 0x439d00 MADD	W10, W27, W19, W10

  (787) 0x439d04 MADD	W10, W22, W10, W9

  (787) 0x439d08 SBFM	X10, X10, #0, #31

  (787) 0x439d0c MADD	X10, X24, X10, X13

  (787) 0x439d10 MADD	X10, X26, X21, X10

  (787) 0x439d14 ADD	X10, X10, X7,LSL #3

  (787) 0x439d18 ADD	X2, X3, X10

  (787) 0x439d1c ORR	X10, XZR, X7

    (789) 0x439d20 LDR	D0, [X6]

    (789) 0x439d24 LDR	D1, [X16, X10,LSL #3]

    (789) 0x439d28 ADD	X10, X10, #1

    (789) 0x439d2c SUBS	X1, X1, #1

    (789) 0x439d30 FMUL	D0, D1, D0

    (789) 0x439d34 STR	D0, [X2], #8

    (789) 0x439d38 B.NE	439d20

  (787) 0x439d3c SUB	X13, X7, X11

  (787) 0x439d40 CMN	X13, #4

  (787) 0x439d44 B.HI	439ca0

  (787) 0x439d48 SUB	W13, WZR, W23

  (787) 0x439d4c MUL	X17, X25, X28

  (787) 0x439d50 SUB	X7, X11, X10

  (787) 0x439d54 MADD	W13, W27, W19, W13

  (787) 0x439d58 MADD	W13, W22, W13, W9

  (787) 0x439d5c SBFM	X13, X13, #0, #31

  (787) 0x439d60 MADD	X13, X24, X13, X17

  (787) 0x439d64 MUL	X17, X26, X21

  (787) 0x439d68 ADD	X13, X13, X17

  (787) 0x439d6c ADD	X17, X3, #16

  (787) 0x439d70 ADD	X13, X13, X10,LSL #3

  (787) 0x439d74 ADD	X1, X17, X13

  (787) 0x439d78 ADD	X13, X16, #16

  (787) 0x439d7c ADD	X10, X13, X10,LSL #3

    (788) 0x439d80 LDR	D0, [X6]

    (788) 0x439d84 LDUR	D1, [X10, #496]

    (788) 0x439d88 SUBS	X7, X7, #4

    (788) 0x439d8c FMUL	D0, D1, D0

    (788) 0x439d90 STUR	D0, [X1, #496]

    (788) 0x439d94 LDR	D0, [X6]

    (788) 0x439d98 LDUR	D1, [X10, #504]

    (788) 0x439d9c FMUL	D0, D1, D0

    (788) 0x439da0 STUR	D0, [X1, #504]

    (788) 0x439da4 LDR	D0, [X6]

    (788) 0x439da8 LDR	D1, [X10]

    (788) 0x439dac FMUL	D0, D1, D0

    (788) 0x439db0 STR	D0, [X1]

    (788) 0x439db4 LDR	D0, [X6]

    (788) 0x439db8 LDR	D1, [X10, #8]

    (788) 0x439dbc ADD	X10, X10, #32

    (788) 0x439dc0 FMUL	D0, D1, D0

    (788) 0x439dc4 STR	D0, [X1, #8]

    (788) 0x439dc8 ADD	X1, X1, #32

    (788) 0x439dcc B.NE	439d80

  (787) 0x439dd0 B	439ca0

0x439dd4 HINT	#0

0x439dd8 HINT	#0

0x439ddc HINT	#0

(786) 0x439de0 LDP	X13, X17, [SP, #40]

(786) 0x439de4 UBFM	X2, X1, #32, #31

(786) 0x439de8 SBFM	X1, X1, #0, #31

(786) 0x439dec ORR	X5, XZR, X15

(786) 0x439df0 ADD	X15, X3, X0,LSL #3

(786) 0x439df4 MUL	X7, X13, X21

(786) 0x439df8 LDR	X13, [SP, #56]

(786) 0x439dfc MUL	X17, X1, X17

(786) 0x439e00 MADD	X1, X24, X1, X15

(786) 0x439e04 ORR	X15, XZR, X5

(786) 0x439e08 MADD	X1, X25, X28, X1

(786) 0x439e0c ADD	X17, X17, X11

(786) 0x439e10 MADD	X1, X26, X21, X1

(786) 0x439e14 MUL	X13, X13, X28

(786) 0x439e18 ADD	X13, X7, X13

(786) 0x439e1c LDR	X7, [SP, #32]

(786) 0x439e20 ADD	X13, X17, X13

(786) 0x439e24 ADD	X17, X5, #8

(786) 0x439e28 ADD	X13, X3, X13,LSL #3

(786) 0x439e2c MADD	X10, X7, X10, X17

(786) 0x439e30 ORR	X7, XZR, X0

(786) 0x439e34 ADD	X17, X10, X2,ASR #29

(786) 0x439e38 ADD	X10, X16, X11,LSL #3

(786) 0x439e3c CMP	X1, X10

(786) 0x439e40 CCMP	X20, X13, #2, #3

(786) 0x439e44 CSINC	W10, WZR, WZR, #2

(786) 0x439e48 CMP	X6, X13

(786) 0x439e4c CCMP	X1, X17, #2, #3

(786) 0x439e50 B.CC	439ce8

(786) 0x439e54 ORR	X7, XZR, X0

(786) 0x439e58 TBNZ	W10, #0, 439ce8

(786) 0x439e5c MUL	X13, X25, X28

(786) 0x439e60 MUL	X17, X26, X21

(786) 0x439e64 LDR	D0, [X6]

(786) 0x439e68 ADD	X15, X3, X0,LSL #3

(786) 0x439e6c ORR	X10, XZR, XZR

(786) 0x439e70 ADD	X1, X13, X17

(786) 0x439e74 ADD	X13, X17, X13

(786) 0x439e78 SUB	W17, WZR, W23

(786) 0x439e7c MADD	W17, W27, W19, W17

(786) 0x439e80 ADD	X1, X15, X1

(786) 0x439e84 LDR	X15, [SP, #24]

(786) 0x439e88 MADD	W17, W22, W17, W9

(786) 0x439e8c DUP	Z0.D, Z0.D[0]

(786) 0x439e90 SBFM	X17, X17, #0, #31

(786) 0x439e94 ADD	X13, X15, X13

(786) 0x439e98 MUL	X17, X24, X17

(786) 0x439e9c ADD	X1, X1, X17

(786) 0x439ea0 ADD	X2, X13, X17

  (790) 0x439ea4 LD1D	{Z1.D}, P0/Z, [X20, X10,LSL #3]

  (790) 0x439ea8 LD1D	{Z2.D}, P0/Z, [X30, X10,LSL #3]

  (790) 0x439eac FMUL	Z1.D, Z1.D, Z0.D

  (790) 0x439eb0 FMUL	Z2.D, Z2.D, Z0.D

  (790) 0x439eb4 ST1D	{Z1.D}, P0, [X1, X10,LSL #3]

  (790) 0x439eb8 ST1D	{Z2.D}, P0, [X2, X10,LSL #3]

  (790) 0x439ebc ADD	X10, X10, X14

  (790) 0x439ec0 CMP	X18, X10

  (790) 0x439ec4 B.NE	439ea4

(786) 0x439ec8 SUB	X10, X11, X0

(786) 0x439ecc ADD	X7, X18, X0

(786) 0x439ed0 ORR	X15, XZR, X5

(786) 0x439ed4 CMP	X10, X18

(786) 0x439ed8 B.EQ	439ca0

(786) 0x439edc B	439ce8

0x439ee0 LDR	W1, [SP, #20]

0x439ee4 ADRP	X0,

0x439ee8 ADD	X0, X0, #1400

0x439eec BL	410770

0x439ef0 LDP	X20, X19, [SP, #192]

0x439ef4 LDP	X22, X21, [SP, #176]

0x439ef8 LDP	X24, X23, [SP, #160]

0x439efc LDP	X26, X25, [SP, #144]

0x439f00 LDP	X28, X27, [SP, #128]

0x439f04 LDP	X29, X30, [SP, #112]

0x439f08 ADD	SP, SP, #208

0x439f0c RET

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	qmcplusplus::BsplineAllocator<[...]	stl_vector.h:368	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:154	exec
○	qmcplusplus::build_SPOSet(bool[...]	Tensor.h:213	exec
○	main	unique_ptr.h:211	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:172	exec

Coverage (%)	Name	Source Location	Module
►85.71+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►14.29+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	qmcplusplus::BsplineAllocator<[...]	stl_vector.h:368	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:154	exec
○	qmcplusplus::build_SPOSet(bool[...]	Tensor.h:213	exec
○	main	unique_ptr.h:211	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:172	exec

Coverage (%)	Name	Source Location	Module
►83.33+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►16.67+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	qmcplusplus::BsplineAllocator<[...]	stl_vector.h:368	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:154	exec
○	qmcplusplus::build_SPOSet(bool[...]	Tensor.h:213	exec
○	main	unique_ptr.h:211	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:172	exec

Coverage (%)	Name	Source Location	Module
►71.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►28.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	qmcplusplus::BsplineAllocator<[...]	stl_vector.h:368	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:154	exec
○	qmcplusplus::build_SPOSet(bool[...]	Tensor.h:213	exec
○	main	unique_ptr.h:211	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:172	exec

Coverage (%)	Name	Module
►100.00+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

Coverage (%)	Name	Module
►100.00+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

Coverage (%)	Name	Module
►100.00+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	BsplineAllocator.hpp:171-180
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/BsplineAllocator.hpp:171-180.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.50 to 1.00 cycles (13.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 29% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 13.50 to 8.16 cycles (1.66x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/BsplineAllocator.hpp:171
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/BsplineAllocator.hpp:171

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 21 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	103
nb uops	97
loop length	412
used w registers	14
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.13 cycles
front end	12.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	13.50	13.50	13.50	13.50	0.00	0.00	0.00	0.00	12.83	12.50	12.67	8.50	8.50
cycles	3.50	3.50	13.50	13.50	13.50	13.50	0.00	0.00	0.00	0.00	12.83	12.50	12.67	8.50	8.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.13
Dispatch	13.50
Overall L1	13.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	29%
load	30%
store	36%
mul	18%
add-sub	20%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.50 cycles. At this rate:

1% of peak load performance is reached (1.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.44 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 439b40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X10, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X10, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W9, [X10, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W10, [X10, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMN W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CCMN W9, #2, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CCMN W10, #2, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LT 439f0c <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d.omp_outlined+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB SP, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W19, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W8, W8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X20, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UMULL X8, W19, W8	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
SBFM X22, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4fcbb0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1376	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MADD X26, X8, X22, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X26, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410860 <@plt_start@+0x840>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X8, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X8, X26, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 439ee0 <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d.omp_outlined+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDRSW X11, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W0, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 439ee0 <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d.omp_outlined+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTW X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W17, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X13, X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X4, X15, [X24, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MUL W12, W22, W19	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUB W27, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X14, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X17, X14, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X18, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X17, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
AND X18, X13, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X13, X17, [X10, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X3, X1, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X10, [X24, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X20, X16, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UBFM X10, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X17, X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UBFM X24, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X25, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X26, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X10, X1, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
RDVL X10, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X10, X10, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X3, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X30, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X13, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 439cac <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d.omp_outlined+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <4fcee4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410770 <@plt_start@+0x750>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	BsplineAllocator.hpp:171-180
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/BsplineAllocator.hpp:171-180.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/BsplineAllocator.hpp:171
- /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/BsplineAllocator.hpp:171

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 21 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	103
nb uops	97
loop length	412
used w registers	14
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.13 cycles
front end	12.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	13.50	13.50	13.50	13.50	0.00	0.00	0.00	0.00	12.83	12.50	12.67	8.50	8.50
cycles	3.50	3.50	13.50	13.50	13.50	13.50	0.00	0.00	0.00	0.00	12.83	12.50	12.67	8.50	8.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.13
Dispatch	13.50
Overall L1	13.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	29%
load	30%
store	36%
mul	18%
add-sub	20%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.50 cycles. At this rate:

1% of peak load performance is reached (1.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.44 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 439b40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X10, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X10, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W9, [X10, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W10, [X10, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMN W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CCMN W9, #2, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CCMN W10, #2, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LT 439f0c <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d.omp_outlined+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB SP, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W19, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W8, W8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X20, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UMULL X8, W19, W8	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
SBFM X22, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4fcbb0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1376	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MADD X26, X8, X22, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X26, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410860 <@plt_start@+0x840>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X8, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X8, X26, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 439ee0 <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d.omp_outlined+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDRSW X11, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W0, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 439ee0 <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d.omp_outlined+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTW X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W17, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X13, X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X4, X15, [X24, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MUL W12, W22, W19	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUB W27, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X14, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X17, X14, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X18, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X17, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
AND X18, X13, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X13, X17, [X10, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X3, X1, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X10, [X24, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X20, X16, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UBFM X10, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X17, X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UBFM X24, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X25, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X26, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X10, X1, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
RDVL X10, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X10, X10, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X3, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X30, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X13, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 439cac <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d.omp_outlined+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <4fcee4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410770 <@plt_start@+0x750>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
1	0	2.57	0	5.99	0	10.25	0	35.84	0	53.84	0	143.42	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.044999998062849	0.10243593901396
1x2	2	2.57	2.57	2	0.029999999329448	0.039525795727968
1x4	3	5.99	5.99	4	0.019999999552965	0.016588378697634
1x8	4	10.25	10.25	8	0.014999999664724	0.0089964028447866
1x16	2	35.84	35.84	16	0.010000000707805	0.0019579634536058
1x24	2	53.84	53.84	24	0.010000000707805	0.0010615156497806
1x32	1	143.42	143.42	32	0.0099999997764826	0.00033945313771255
1x40
1x48
1x56
1x64

Name	Coverage (%)	Time (s)
▼qmcplusplus::BsplineAllocator >::setCoefficientsForOrbitals(int, int, Array&, multi_UBspline_3d_d*) [clone .omp_outlined]–	0.10	0.04
▼Loop 786 - BsplineAllocator.hpp:172-180 - exec–	0.00	0.00
○Loop 790 - BsplineAllocator.hpp:179-180 - exec	0.10	0.04
▼Loop 787 - BsplineAllocator.hpp:172-180 - exec–	0.00	0.00
○Loop 788 - BsplineAllocator.hpp:179-180 - exec	0.00	0.00
○Loop 789 - BsplineAllocator.hpp:179-180 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency