OV - exec - Loop 354

	Loop Id: 354	Module: exec	Source: TwoBodyJastrowRef.h:397-398	Coverage: NA%

0x426144 ADD	X1, X24, X18

0x426148 LD1B	{Z0.B}, P2/Z, [X24, X18]    [6]

0x42614c LD1B	{Z2.B}, P2/Z, [X10, X18]    [4]

0x426150 SUBS	X0, X0, X23

0x426154 LD1B	{Z4.B}, P2/Z, [X12, X18]    [5]

0x426158 FMSB	Z0.D, P1/M, Z2.D, Z4.D

0x42615c LDR	Z1, [X1, #1, MUL VL]    [3]

0x426160 ADD	X1, X10, X18

0x426164 LDR	Z3, [X1, #1, MUL VL]    [2]

0x426168 ADD	X1, X12, X18

0x42616c LDR	Z5, [X1, #1, MUL VL]    [1]

0x426170 FMSB	Z1.D, P1/M, Z3.D, Z5.D

0x426174 ST1B	{Z0.B}, P2, [X12, X18]    [5]

0x426178 ADD	X18, X18, X26

0x42617c STR	Z1, [X1, #1, MUL VL]    [1]

0x426180 B.NE	426144

/home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 397 - 398

--------------------------------------------------------------------------------

397:         for (int jat = 0; jat < iat; jat++)

398:           save_g[jat] -= du[jat] * dX[jat];

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P10, P11,
Function	miniqmcreference::TwoBodyJastrowRef >::recompute(qmcplusplus::ParticleSet&)
Source	TwoBodyJastrowRef.h:397-398
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	8
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	4.00
Front-end cycles	2.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	1.25
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	4.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	6.00
Stride indirect	0.00
Vectorization ratio all	90.91
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	93.18
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P10, P11,
Function	miniqmcreference::TwoBodyJastrowRef >::recompute(qmcplusplus::ParticleSet&)
Source	TwoBodyJastrowRef.h:397-398
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	8
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	4.00
Front-end cycles	2.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	1.25
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	4.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	6.00
Stride indirect	0.00
Vectorization ratio all	90.91
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	93.18
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::recompute(qmcplusplus::ParticleSet&)
Source file and lines	TwoBodyJastrowRef.h:397-398
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:397-398.

The related source loop is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 93% of vector register length is used (average across all VPU instructions).

Details

90% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.

FMA

Detected 8 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 6 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 192 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	16
nb uops	16
loop length	64
used w registers	0
used x registers	8
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	6
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.00 cycles
front end	2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	1.00	1.00	1.00	1.00	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	1.00	1.00	1.00	1.00	4.00	4.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.00
Dispatch	4.00
Data deps.	1.00
Overall L1	4.00

Vectorization ratios

INT

all	88%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	90%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	91%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	93%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

50% of peak load performance is reached (48.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 426144

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ADD X1, X24, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1B {Z0.B}, P2/Z, [X24, X18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1B {Z2.B}, P2/Z, [X10, X18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUBS X0, X0, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (25.0%)
LD1B {Z4.B}, P2/Z, [X12, X18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMSB Z0.D, P1/M, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z1, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X1, X10, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z3, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X1, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z5, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMSB Z1.D, P1/M, Z3.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1B {Z0.B}, P2, [X12, X18]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X18, X18, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
STR Z1, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
B.NE 426144 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE+0x944>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::recompute(qmcplusplus::ParticleSet&)
Source file and lines	TwoBodyJastrowRef.h:397-398
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 93% of vector register length is used (average across all VPU instructions).

Details

90% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.

FMA

Detected 8 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 6 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 192 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	16
nb uops	16
loop length	64
used w registers	0
used x registers	8
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	6
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.00 cycles
front end	2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	1.00	1.00	1.00	1.00	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	1.00	1.00	1.00	1.00	4.00	4.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.00
Dispatch	4.00
Data deps.	1.00
Overall L1	4.00

Vectorization ratios

INT

all	88%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	90%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	91%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	93%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

50% of peak load performance is reached (48.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 426144

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ADD X1, X24, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1B {Z0.B}, P2/Z, [X24, X18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1B {Z2.B}, P2/Z, [X10, X18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUBS X0, X0, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (25.0%)
LD1B {Z4.B}, P2/Z, [X12, X18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMSB Z0.D, P1/M, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LDR Z1, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X1, X10, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z3, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X1, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z5, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMSB Z1.D, P1/M, Z3.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1B {Z0.B}, P2, [X12, X18]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X18, X18, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
STR Z1, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
B.NE 426144 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE+0x944>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-212-9071/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1782144418OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
		1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1
1x2	2	1	1	2	0.019999999552965	0.028232710435987
1x4	4	1	1	4	0.014999999664724	0.019353108480573
1x8	8	1	1	8	0.019999999552965	0.025704009458423
1x16	8	1	1	16	0.015000000596046	0.0097898170351982
1x24	8	1	1	24	0.015000000596046	0.0055729569867253
1x32	14	1	1	32	0.019999999552965	0.0056009767577052
1x40	5	1	1	40	0.025000000372529	0.0019962014630437
1x48	16	1	1	48	0.02000000141561	0.0044537936337292
1x56	18	1	1	56	0.02000000141561	0.0039316243492067
1x64	8	1	1	64	0.030000001192093	0.0017610768554732

Report Configuration

Vectorization

Details

FMA

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

FMA

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency