OV - - Loop 2550 - engine_linuxa64

	Loop Id: 2550	Module: engine_linuxa64_ompi	Source: roto.F:99-114	Coverage: 0.11%

0x1648c0 LD1D	{Z2.D}, P0/Z, [X11, X8,LSL #3]    [1]

0x1648c4 LD1D	{Z4.D}, P0/Z, [X12, X8,LSL #3]    [2]

0x1648c8 ADD	X0, X10, X8,LSL #3

0x1648cc FMUL	Z3.D, Z0.D, Z2.D

0x1648d0 LD1D	{Z5.D}, P0/Z, [X0, X15,LSL #3]    [4]

0x1648d4 LD1D	{Z16.D}, P0/Z, [X0, X16,LSL #3]    [4]

0x1648d8 LD1D	{Z1.D}, P0/Z, [X0, X14,LSL #3]    [4]

0x1648dc FMUL	Z6.D, Z4.D, Z4.D

0x1648e0 FMUL	Z17.D, Z2.D, Z2.D

0x1648e4 FMUL	Z3.D, Z3.D, Z4.D

0x1648e8 FMUL	Z7.D, Z5.D, Z6.D

0x1648ec FMUL	Z18.D, Z17.D, Z16.D

0x1648f0 FMUL	Z3.D, Z1.D, Z3.D

0x1648f4 FADD	Z7.D, Z7.D, Z18.D

0x1648f8 FMUL	Z18.D, Z6.D, Z16.D

0x1648fc FSUB	Z6.D, Z17.D, Z6.D

0x164900 FADD	Z3.D, Z3.D, Z7.D

0x164904 FMUL	Z7.D, Z17.D, Z5.D

0x164908 FADD	Z7.D, Z7.D, Z18.D

0x16490c FMUL	Z18.D, Z0.D, Z4.D

0x164910 FMUL	Z18.D, Z2.D, Z18.D

0x164914 FMUL	Z18.D, Z1.D, Z18.D

0x164918 FMUL	Z1.D, Z1.D, Z6.D

0x16491c FMUL	Z6.D, Z2.D, Z4.D

0x164920 FMUL	Z5.D, Z5.D, Z6.D

0x164924 FMUL	Z6.D, Z6.D, Z16.D

0x164928 LD1D	{Z16.D}, P0/Z, [X13, X8,LSL #3]    [3]

0x16492c FSUB	Z7.D, Z7.D, Z18.D

0x164930 FSUB	Z5.D, Z5.D, Z6.D

0x164934 FADD	Z1.D, Z1.D, Z5.D

0x164938 LD1D	{Z5.D}, P0/Z, [X0, X17,LSL #3]    [4]

0x16493c ST1D	{Z3.D}, P0, [X0, X16,LSL #3]    [4]

0x164940 ST1D	{Z7.D}, P0, [X0, X15,LSL #3]    [4]

0x164944 FMUL	Z17.D, Z4.D, Z16.D

0x164948 ST1D	{Z1.D}, P0, [X0, X14,LSL #3]    [4]

0x16494c FMUL	Z6.D, Z2.D, Z5.D

0x164950 FMUL	Z4.D, Z4.D, Z5.D

0x164954 FMUL	Z2.D, Z2.D, Z16.D

0x164958 FSUB	Z6.D, Z6.D, Z17.D

0x16495c FADD	Z2.D, Z4.D, Z2.D

0x164960 ST1D	{Z6.D}, P0, [X0, X17,LSL #3]    [4]

0x164964 ST1D	{Z2.D}, P0, [X13, X8,LSL #3]    [3]

0x164968 ADD	X8, X8, X18

0x16496c WHILELO	P0.D, X8, X9

0x164970 B.MI	1648c0

/home/eoseret/Applications/OpenRadioss/engine/source/airbag/roto.F: 99 - 114

--------------------------------------------------------------------------------

99:          S1 = DIR(I,1)*DIR(I,1)*SIG(I,1)

100:      .       +DIR(I,2)*DIR(I,2)*SIG(I,2)

101:      . + TWO*DIR(I,1)*DIR(I,2)*SIG(I,3)

102:          S2 = DIR(I,2)*DIR(I,2)*SIG(I,1)

103:      .       +DIR(I,1)*DIR(I,1)*SIG(I,2)

104:      .  -TWO*DIR(I,2)*DIR(I,1)*SIG(I,3)

105:          S3 =-DIR(I,1)*DIR(I,2)*SIG(I,1)

106:      .       +DIR(I,2)*DIR(I,1)*SIG(I,2)

107:      .      +(DIR(I,1)*DIR(I,1)-DIR(I,2)*DIR(I,2))*SIG(I,3)

108:          S4 =-DIR(I,2)*SIG(I,5)+DIR(I,1)*SIG(I,4)

109:          S5 = DIR(I,1)*SIG(I,5)+DIR(I,2)*SIG(I,4)

110:          SIG(I,1)=S1

111:          SIG(I,2)=S2

112:          SIG(I,3)=S3

113:          SIG(I,4)=S4

114:          SIG(I,5)=S5

Coverage (%)	Name	Source Location	Module
►94.83+	cmain3	cmain3.F:296	engine_linuxa64_ompi
○	czforc3	czforc3.F:547	engine_linuxa64_ompi
○	forintc	forintc.F:340	engine_linuxa64_ompi
○	__nv_resol__F1L4454_15	resol.F:28	engine_linuxa64_ompi
○	__kmp_invoke_microtask		libomp.so
►5.17+	cmain3	cmain3.F:296	engine_linuxa64_ompi
○	c3forc3	c3forc3.F:507	engine_linuxa64_ompi
○	forintc	forintc.F:556	engine_linuxa64_ompi
○	__nv_resol__F1L4454_15	resol.F:28	engine_linuxa64_ompi
○	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.42
Bottlenecks	P6, P7, P8, P9,
Function	rotov
Source	roto.F:99-114
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	14.50
CQA cycles if FP arith vectorized	14.50
CQA cycles if fully vectorized	14.50
Front-end cycles	5.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	1.00
P5 cycles	0.50
P6 cycles	14.50
P7 cycles	14.50
P8 cycles	14.50
P9 cycles	14.50
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	45.00
Nb loads	NA
Nb stores	5.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	36.00
Nb FLOP mul	80.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.48
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	160.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.42
Bottlenecks	P6, P7, P8, P9,
Function	rotov
Source	roto.F:99-114
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	14.50
CQA cycles if FP arith vectorized	14.50
CQA cycles if fully vectorized	14.50
Front-end cycles	5.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	1.00
P5 cycles	0.50
P6 cycles	14.50
P7 cycles	14.50
P8 cycles	14.50
P9 cycles	14.50
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	45.00
Nb loads	NA
Nb stores	5.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	36.00
Nb FLOP mul	80.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.48
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	160.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	rotov
Source file and lines	roto.F:99-114
Module	engine_linuxa64_ompi

The loop is defined in /home/eoseret/Applications/OpenRadioss/engine/source/airbag/roto.F:99-114.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 116 FP arithmetical operations:

36: addition or subtraction
80: multiply

The binary loop is loading 224 bytes. The binary loop is storing 160 bytes.

Arithmetic intensity

Arithmetic intensity is 0.30 FP operations per loaded or stored byte.

General properties

nb instructions	45
loop length	180
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	1.00	0.50	14.50	14.50	2.50	2.50	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	1.00	0.50	14.50	14.50	14.50	14.50	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.63
Data deps.	1.00
Overall L1	14.50

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

16% of peak load performance is reached (15.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (11.03 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 1648c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z2.D}, P0/Z, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P0/Z, [X12, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X0, X10, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMUL Z3.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z5.D}, P0/Z, [X0, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P0/Z, [X0, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z1.D}, P0/Z, [X0, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z6.D, Z4.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z17.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z7.D, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z18.D, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z3.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z7.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z18.D, Z6.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z6.D, Z17.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, Z3.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z7.D, Z17.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z7.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z18.D, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z18.D, Z2.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z18.D, Z1.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z1.D, Z1.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z6.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z5.D, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z6.D, Z6.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z16.D}, P0/Z, [X13, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z7.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z5.D, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z1.D, Z1.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z5.D}, P0/Z, [X0, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ST1D {Z3.D}, P0, [X0, X16,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z7.D}, P0, [X0, X15,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FMUL Z17.D, Z4.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z1.D}, P0, [X0, X14,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FMUL Z6.D, Z2.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z4.D, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z2.D, Z2.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z6.D, Z6.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z2.D, Z4.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z6.D}, P0, [X0, X17,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z2.D}, P0, [X13, X8,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X8, X8, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P0.D, X8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 1648c0 <rotov_+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	rotov
Source file and lines	roto.F:99-114
Module	engine_linuxa64_ompi

The loop is defined in /home/eoseret/Applications/OpenRadioss/engine/source/airbag/roto.F:99-114.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 116 FP arithmetical operations:

36: addition or subtraction
80: multiply

The binary loop is loading 224 bytes. The binary loop is storing 160 bytes.

Arithmetic intensity

Arithmetic intensity is 0.30 FP operations per loaded or stored byte.

General properties

nb instructions	45
loop length	180
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	1.00	0.50	14.50	14.50	2.50	2.50	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	1.00	0.50	14.50	14.50	14.50	14.50	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.63
Data deps.	1.00
Overall L1	14.50

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

16% of peak load performance is reached (15.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (11.03 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 1648c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z2.D}, P0/Z, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P0/Z, [X12, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X0, X10, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMUL Z3.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z5.D}, P0/Z, [X0, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P0/Z, [X0, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z1.D}, P0/Z, [X0, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z6.D, Z4.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z17.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z7.D, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z18.D, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z3.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z7.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z18.D, Z6.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z6.D, Z17.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, Z3.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z7.D, Z17.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z7.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z18.D, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z18.D, Z2.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z18.D, Z1.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z1.D, Z1.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z6.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z5.D, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z6.D, Z6.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z16.D}, P0/Z, [X13, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z7.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z5.D, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z1.D, Z1.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z5.D}, P0/Z, [X0, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ST1D {Z3.D}, P0, [X0, X16,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z7.D}, P0, [X0, X15,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FMUL Z17.D, Z4.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z1.D}, P0, [X0, X14,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FMUL Z6.D, Z2.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z4.D, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z2.D, Z2.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z6.D, Z6.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z2.D, Z4.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z6.D}, P0, [X0, X17,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z2.D}, P0, [X13, X8,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X8, X8, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P0.D, X8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 1648c0 <rotov_+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code