OV - - Loop 39611 - engine_linuxa64

	Loop Id: 39611	Module: engine_linuxa64_ompi	Source: sigeps02c.F:213-222	Coverage: 0.02%

0xd519c0 AND	P5.B, P3/Z, P3.B, P2.B

0xd519c4 LD1D	{Z16.D}, P5/Z, [X10, X9,LSL #3]    [1]

0xd519c8 FCMEQ	P4.D, P5/Z, Z16.D, Z6.D

0xd519cc FCMNE	P5.D, P5/Z, Z16.D, Z6.D

0xd519d0 LD1D	{Z18.D}, P4/Z, [X15, X9,LSL #3]    [5]

0xd519d4 LD1D	{Z19.D}, P4/Z, [X16, X9,LSL #3]    [6]

0xd519d8 LD1D	{Z17.D}, P4/Z, [X12, X9,LSL #3]    [2]

0xd519dc LD1D	{Z20.D}, P4/Z, [X17, X9,LSL #3]    [7]

0xd519e0 FSUB	Z19.D, Z18.D, Z19.D

0xd519e4 FADD	Z19.D, Z17.D, Z19.D

0xd519e8 FADD	Z17.D, Z17.D, Z18.D

0xd519ec LD1D	{Z18.D}, P4/Z, [X0, X9,LSL #3]    [9]

0xd519f0 FSUB	Z19.D, Z19.D, Z20.D

0xd519f4 LD1D	{Z20.D}, P4/Z, [X11, X9,LSL #3]    [13]

0xd519f8 FNEG	Z19.D, P1/M, Z19.D

0xd519fc FMUL	Z19.D, Z2.D, Z19.D

0xd51a00 FCMGE	P6.D, P1/Z, Z20.D, #0

0xd51a04 FDIV	Z19.D, P1/M, Z19.D, Z3.D

0xd51a08 SEL	Z20.D, P6, Z20.D, Z7.D

0xd51a0c FMUL	Z20.D, Z0.D, Z20.D

0xd51a10 FMUL	Z17.D, Z17.D, Z20.D

0xd51a14 FDIV	Z17.D, P1/M, Z17.D, Z18.D

0xd51a18 FSUB	Z17.D, Z19.D, Z17.D

0xd51a1c ST1D	{Z17.D}, P4, [X18, X9,LSL #3]    [8]

0xd51a20 LD1D	{Z16.D}, P5/Z, [X18, X9,LSL #3]    [8]

0xd51a24 AND	P5.B, P3/Z, P3.B, P0.B

0xd51a28 LD1D	{Z18.D}, P5/Z, [X1, X9,LSL #3]    [10]

0xd51a2c LD1D	{Z19.D}, P5/Z, [X2, X9,LSL #3]    [11]

0xd51a30 SEL	Z16.D, P4, Z17.D, Z16.D

0xd51a34 LD1D	{Z17.D}, P3/Z, [X3, X9,LSL #3]    [12]

0xd51a38 FADD	Z18.D, Z18.D, Z19.D

0xd51a3c LD1D	{Z19.D}, P5/Z, [X18, X9,LSL #3]    [8]

0xd51a40 FMUL	Z18.D, Z18.D, Z1.D

0xd51a44 FMUL	Z19.D, Z19.D, Z4.D

0xd51a48 FSUB	Z18.D, Z18.D, Z19.D

0xd51a4c FDIV	Z18.D, P1/M, Z18.D, Z5.D

0xd51a50 ST1D	{Z18.D}, P5, [X18, X9,LSL #3]    [8]

0xd51a54 SEL	Z16.D, P5, Z18.D, Z16.D

0xd51a58 LD1D	{Z18.D}, P3/Z, [X13, X9,LSL #3]    [3]

0xd51a5c FMUL	Z16.D, Z16.D, Z18.D

0xd51a60 FMUL	Z16.D, Z17.D, Z16.D

0xd51a64 LD1D	{Z17.D}, P3/Z, [X14, X9,LSL #3]    [4]

0xd51a68 FADD	Z16.D, Z17.D, Z16.D

0xd51a6c ST1D	{Z16.D}, P3, [X14, X9,LSL #3]    [4]

0xd51a70 ADD	X9, X9, X4

0xd51a74 WHILELO	P3.D, X9, X8

0xd51a78 B.MI	d519c0

/home/hbollore/apps/openradioss/OpenRadioss/engine/source/materials/mat/mat002/sigeps02c.F: 213 - 222

--------------------------------------------------------------------------------

213:         IF (INLOC > 0) THEN

214:           IF (LOFF(I) == ONE) THEN

215:             EZZ(I) = -NU*(SIGNXX(I)-SIGOXX(I)+SIGNYY(I)-SIGOYY(I))/YOUNG

216:             EZZ(I) = EZZ(I) - MAX(DPLANL(I),ZERO)*HALF*(SIGNXX(I)+SIGNYY(I))/YLD(I)

217:           ENDIF

218:         ELSE

219:           EZZ(I) = -(DEPSXX(I)+DEPSYY(I))*NU-(ONE - TWO*NU)*EZZ(I)

220:           EZZ(I) = EZZ(I)/(ONE-NU)

221:         ENDIF

222:         THK(I) = THK(I) + EZZ(I) * THKLYL(I)*OFF(I)

Coverage (%)	Name	Source Location	Module
►98.83+	mulawc	mulawc.F90:1113	engine_linuxa64_ompi
○	cmain3	cmain3.F:308	engine_linuxa64_ompi
○	czforc3	czforc3.F:570	engine_linuxa64_ompi
○	forintc	forintc.F:351	engine_linuxa64_ompi
○	__nv_resol__F1L4562_15	resol.F:28	engine_linuxa64_ompi
○	__kmp_invoke_microtask		libomp.so
►1.10+	mulawc	mulawc.F90:1113	engine_linuxa64_ompi
○	cmain3	cmain3.F:308	engine_linuxa64_ompi
○	c3forc3	c3forc3.F:531	engine_linuxa64_ompi
○	forintc	forintc.F:578	engine_linuxa64_ompi
○	__nv_resol__F1L4562_15	resol.F:28	engine_linuxa64_ompi
○	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.68 - 3.38
Bottlenecks	P6, P8,
Function	sigeps02c
Source	sigeps02c.F:213-222
Source loop unroll info	unrolled by 12
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	12
CQA cycles	20.98 - 42.25
CQA cycles if no scalar integer	20.98 - 42.25
CQA cycles if FP arith vectorized	20.98 - 42.25
CQA cycles if fully vectorized	20.98 - 42.25
Front-end cycles	5.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	3.00
P5 cycles	0.25
P6 cycles	12.50
P7 cycles	12.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	8.50
P11 cycles	8.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	20.98 - 42.25
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	47.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	3.43 - 1.70
Nb FLOP add-sub	32.00
Nb FLOP mul	28.00
Nb FLOP fma	0.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.87 - 25.93
Bytes prefetched	0.00
Bytes loaded	448.00
Bytes stored	96.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	13.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	96.02
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	80.56

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.68 - 3.38
Bottlenecks	P6, P8,
Function	sigeps02c
Source	sigeps02c.F:213-222
Source loop unroll info	unrolled by 12
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	12
CQA cycles	20.98 - 42.25
CQA cycles if no scalar integer	20.98 - 42.25
CQA cycles if FP arith vectorized	20.98 - 42.25
CQA cycles if fully vectorized	20.98 - 42.25
Front-end cycles	5.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	3.00
P5 cycles	0.25
P6 cycles	12.50
P7 cycles	12.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	8.50
P11 cycles	8.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	20.98 - 42.25
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	47.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	3.43 - 1.70
Nb FLOP add-sub	32.00
Nb FLOP mul	28.00
Nb FLOP fma	0.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.87 - 25.93
Bytes prefetched	0.00
Bytes loaded	448.00
Bytes stored	96.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	13.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	96.02
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	80.56

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	sigeps02c
Source file and lines	sigeps02c.F:213-222
Module	engine_linuxa64_ompi

The loop is defined in /home/hbollore/apps/openradioss/OpenRadioss/engine/source/materials/mat/mat002/sigeps02c.F:213-222.

The related source loop is unrolled by 12 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 96% register length (average across all VPU instructions).

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 13 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 72 FP arithmetical operations:

32: addition or subtraction
28: multiply
12: divide

The binary loop is loading 448 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	47
nb uops	47
loop length	188
used w registers	0
used x registers	16
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	13
nb stack references	0
ADD-SUB / MUL ratio	1.14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.88 cycles
front end	5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	3.00	0.25	12.50	12.50	1.50	1.50	8.50	8.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	3.00	0.25	12.50	12.50	7.50	7.50	8.50	8.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	20.98-42.25
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.88
Dispatch	12.50
DIV/SQRT	20.98-42.25
Data deps.	1.00
Overall L1	20.98-42.25

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	92%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	65%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	96%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	80%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 42.25 cycles. At this rate:

11% of peak load performance is reached (10.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: d519c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
AND P5.B, P3/Z, P3.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z16.D}, P5/Z, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMEQ P4.D, P5/Z, Z16.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FCMNE P5.D, P5/Z, Z16.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z18.D}, P4/Z, [X15, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P4/Z, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z17.D}, P4/Z, [X12, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P4/Z, [X17, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z19.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z19.D, Z17.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z18.D}, P4/Z, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z19.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z20.D}, P4/Z, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FNEG Z19.D, P1/M, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z19.D, Z2.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FCMGE P6.D, P1/Z, Z20.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FDIV Z19.D, P1/M, Z19.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
SEL Z20.D, P6, Z20.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z20.D, Z0.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z17.D, Z17.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z17.D, P1/M, Z17.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FSUB Z17.D, Z19.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z17.D}, P4, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z16.D}, P5/Z, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
AND P5.B, P3/Z, P3.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z18.D}, P5/Z, [X1, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P5/Z, [X2, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SEL Z16.D, P4, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z17.D}, P3/Z, [X3, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z19.D}, P5/Z, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z18.D, Z18.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z19.D, Z19.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z18.D, P1/M, Z18.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ST1D {Z18.D}, P5, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
SEL Z16.D, P5, Z18.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z18.D}, P3/Z, [X13, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z16.D, Z16.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z16.D, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z17.D}, P3/Z, [X14, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z16.D, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z16.D}, P3, [X14, X9,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X9, X9, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P3.D, X9, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI d519c0 <sigeps02c_+0x10a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	sigeps02c
Source file and lines	sigeps02c.F:213-222
Module	engine_linuxa64_ompi

The loop is defined in /home/hbollore/apps/openradioss/OpenRadioss/engine/source/materials/mat/mat002/sigeps02c.F:213-222.

The related source loop is unrolled by 12 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 96% register length (average across all VPU instructions).

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 13 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 72 FP arithmetical operations:

32: addition or subtraction
28: multiply
12: divide

The binary loop is loading 448 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	47
nb uops	47
loop length	188
used w registers	0
used x registers	16
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	13
nb stack references	0
ADD-SUB / MUL ratio	1.14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.88 cycles
front end	5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	3.00	0.25	12.50	12.50	1.50	1.50	8.50	8.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	3.00	0.25	12.50	12.50	7.50	7.50	8.50	8.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	20.98-42.25
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.88
Dispatch	12.50
DIV/SQRT	20.98-42.25
Data deps.	1.00
Overall L1	20.98-42.25

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	92%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	65%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	96%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	80%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 42.25 cycles. At this rate:

11% of peak load performance is reached (10.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: d519c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
AND P5.B, P3/Z, P3.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z16.D}, P5/Z, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMEQ P4.D, P5/Z, Z16.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FCMNE P5.D, P5/Z, Z16.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z18.D}, P4/Z, [X15, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P4/Z, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z17.D}, P4/Z, [X12, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P4/Z, [X17, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z19.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z19.D, Z17.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z18.D}, P4/Z, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z19.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z20.D}, P4/Z, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FNEG Z19.D, P1/M, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z19.D, Z2.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FCMGE P6.D, P1/Z, Z20.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FDIV Z19.D, P1/M, Z19.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
SEL Z20.D, P6, Z20.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z20.D, Z0.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z17.D, Z17.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z17.D, P1/M, Z17.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FSUB Z17.D, Z19.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z17.D}, P4, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z16.D}, P5/Z, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
AND P5.B, P3/Z, P3.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z18.D}, P5/Z, [X1, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P5/Z, [X2, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SEL Z16.D, P4, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z17.D}, P3/Z, [X3, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z19.D}, P5/Z, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z18.D, Z18.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z19.D, Z19.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z18.D, P1/M, Z18.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ST1D {Z18.D}, P5, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
SEL Z16.D, P5, Z18.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z18.D}, P3/Z, [X13, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z16.D, Z16.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z16.D, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z17.D}, P3/Z, [X14, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z16.D, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z16.D}, P3, [X14, X9,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X9, X9, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P3.D, X9, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI d519c0 <sigeps02c_+0x10a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code